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1. 发明申请

WO2013148927A1 UNIVERSAL INTERCONNECT FOOTPRINT FOR BONDING SEMICONDUCTOR SUBSTRATES 审中-公开
标题翻译：用于连接半导体衬底的通用互连接头
公开(公告)号：WO2013148927A1
公开(公告)日：2013-10-03
申请号：PCT/US2013/034235
申请日：2013-03-28
申请人： ADVANCED MICRO DEVICES, INC.
发明人： BLACK, Bryan , MCLELLAN, Neil , SU, Michael , SIEGEL, Joe , ALFANO, Michael
IPC分类号： H01L21/60 , H01L21/56
CPC分类号： H01L24/11 , H01L21/563 , H01L24/03 , H01L24/05 , H01L24/10 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/0345 , H01L2224/03452 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05681 , H01L2224/05687 , H01L2224/10 , H01L2224/10135 , H01L2224/10165 , H01L2224/11 , H01L2224/1146 , H01L2224/1147 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13164 , H01L2224/13169 , H01L2224/14131 , H01L2224/14132 , H01L2224/14136 , H01L2224/16146 , H01L2224/16235 , H01L2224/17181 , H01L2224/2732 , H01L2224/27334 , H01L2224/29076 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81007 , H01L2224/81139 , H01L2224/8114 , H01L2224/81193 , H01L2224/81203 , H01L2224/81815 , H01L2224/83102 , H01L2224/83855 , H01L2224/92125 , H01L2224/92143 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2225/06593 , H01L2924/15311 , H01L2924/15312 , H01L2924/15313 , H01L2924/00014 , H01L2924/04953 , H01L2924/01082 , H01L2924/01047 , H01L2924/01029 , H01L2924/00012 , H01L2924/00
摘要： A side (43) of a first semiconductor substrate (15) is provided with a first set (60) of interconnect structures (45a, 45b). The first semiconductor substrate (15) is operable to have at least one of plural semiconductor substrates (20, 155, 160) stacked on the side (43). The first set (60) of interconnect structures (45a, 45b) is arranged in a pattern. Each of the plural semiconductor substrates (20, 155, 160) has a second set (62) of interconnect structures (55a, 55b) arranged in the pattern, one of the plural semiconductor substrates (155) has a smallest footprint of the plural semiconductor substrates (20, 155, 160). The pattern of the first and second sets (60, 62) of interconnect structures (45a, 45b, 55a, 55b) has a footprint smaller than the smallest footprint (x3, y3) of the plural semiconductor substrates (20, 155, 160). In this way, the first semiconductor substrate (15), implemented as an interposer or otherwise, has an interconnect set (60) with a universal footprint capable of matching up with different sized dice (20, 155, 160) fabricated with matching interconnect sets (62) that share that universal footprint. The second semiconductor substrate (20) has overhangs (65a, 65b) that are lateral to the interconnect sets (60, 62). To provide support for the overhangs (65a, 65b), support structures (70a, 70b, 70c, 70d) may be provided at the periphery of the semiconductor substrate (20) and beneath the overhangs (65a, 65b). Alternatively, a support frame (182) may be provided.
摘要翻译：第一半导体衬底（15）的一侧（43）设置有互连结构（45a，45b）的第一组（60）。第一半导体衬底（15）可操作以具有堆叠在侧面（43）上的多个半导体衬底（20,155,160）中的至少一个。互连结构（45a，45b）的第一组（60）以图案布置。多个半导体衬底（20,155,160）中的每一个具有以图案排列的互连结构（55a，55b）的第二组（62），多个半导体衬底（155）中的一个具有多个半导体衬底（20,155,160）。互连结构（45a，45b，55a，55b）的第一和第二组（60,62）的图案具有小于多个半导体衬底（20,155,160）中的最小覆盖区（x3，y3）的占地面积，。以这种方式，实现为中介器或其他方式的第一半导体衬底（15）具有互连组件（60），该互连组件具有能与匹配的互连组合制成的不同尺寸的裸片（20,155,160）匹配的通用尺寸（62）共享这一普遍的足迹。第二半导体衬底（20）具有横向于互连组（60,62）的突出端（65a，65b）。为了提供对突出端（65a，65b）的支撑，支撑结构（70a，70b，70c，70d）可以设置在半导体衬底（20）的周边并且在突出部（65a，65b）的下方。或者，可以提供支撑框架（182）。

2. 发明申请

WO2012015885A3 OPTICAL CONNECTION THROUGH SINGLE ASSEMBLY OVERHANG FLIP CHIP OPTICS DIE WITH MICRO STRUCTURE ALIGNMENT 审中-公开
标题翻译：通过单组件进行光学连接带有微结构对准的OVERHANG FLIP CHIP OPTICS DIE
公开(公告)号：WO2012015885A3
公开(公告)日：2012-04-19
申请号：PCT/US2011045486
申请日：2011-07-27
申请人： INTEL CORP , KIM BRIAN H , LEE SIMON S
发明人： KIM BRIAN H , LEE SIMON S
IPC分类号： G02B6/42
CPC分类号： H01L23/544 , G02B6/3882 , G02B6/3885 , G02B6/4249 , G02B6/4261 , G02B6/4292 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2223/54426 , H01L2223/54473 , H01L2224/10135 , H01L2224/10165 , H01L2224/73204 , H01L2224/81007 , H01L2224/81141 , H01L2224/81815 , H01L2224/831 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01077 , H01L2924/014 , H01L2924/14 , H01L2924/00
摘要： A system includes an optical transceiver assembly, including a flip chip connection of a semiconductor die with a photonic transceiver that overhangs a substrate to which it is to be connected. The assembly further includes an alignment pin that is held to the semiconductor die at a micro-engineered structure in the semiconductor die. The alignment pin provides passive alignment of the photonic transceiver with an optical lens that interfaces the photonic transceiver to one or more optical channels.
摘要翻译：一种系统包括光收发器组件，其包括半导体管芯与光子收发器的倒装芯片连接，所述光子收发器突出到其将被连接到的衬底上。组件还包括在半导体管芯中以微型工程结构保持在半导体管芯上的对准销。对准引脚提供光子收发器与将光子收发器连接到一个或多个光学通道的光学透镜的被动对准。

3. 发明申请

WO2012030470A2 RAMP-STACK CHIP PACKAGE WITH STATIC BENDS 审中-公开
标题翻译： RAMP堆栈芯片包装与静态BENDS
公开(公告)号：WO2012030470A2
公开(公告)日：2012-03-08
申请号：PCT/US2011046519
申请日：2011-08-04
申请人： ORACLE INT CORP , HARADA JOHN A , DOUGLAS DAVID C , DROST ROBERT J
发明人： HARADA JOHN A , DOUGLAS DAVID C , DROST ROBERT J
IPC分类号： H01L23/52
CPC分类号： H01L25/0657 , G02B6/43 , H01L23/544 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L29/0657 , H01L2223/54426 , H01L2224/0401 , H01L2224/05555 , H01L2224/10135 , H01L2224/10165 , H01L2224/131 , H01L2224/1329 , H01L2224/133 , H01L2224/1601 , H01L2224/16105 , H01L2224/16135 , H01L2224/16151 , H01L2224/1703 , H01L2224/32145 , H01L2224/73203 , H01L2224/73253 , H01L2224/81007 , H01L2224/81141 , H01L2224/81385 , H01L2224/81815 , H01L2224/8185 , H01L2224/819 , H01L2224/8313 , H01L2224/83132 , H01L2224/83193 , H01L2224/8385 , H01L2225/06531 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/014 , H01L2924/1015 , H01L2924/10155 , H01L2924/151
摘要： A ramp-stack chip package is described. This chip package includes a vertical stack of semiconductor dies or chips that are offset from each other in a horizontal direction, thereby defining a terrace with exposed pads. A high-bandwidth ramp component, which is positioned approximately parallel to the terrace, is electrically and mechanically coupled to the exposed pads. For example, the ramp component may be coupled to the semiconductor dies using: solder, microsprings and/or an anisotropic conducting film. Furthermore, each of the semiconductor dies includes a static bend so that an end segment of each of the semiconductor dies is parallel to the direction and is mechanically coupled to the ramp component. These end segments may facilitate high-bandwidth communication of signals between the chips and the ramp component, for example, via proximity communication.
摘要翻译：描述了斜坡堆栈芯片封装。该芯片封装包括沿水平方向彼此偏移的半导体管芯或芯片的垂直堆叠，由此限定具有暴露焊盘的平台。大致平行于平台定位的高带宽斜坡部件电和机械耦合到暴露的焊盘。例如，斜坡部件可以使用：焊料，微弹簧和/或各向异性导电膜耦合到半导体管芯。此外，每个半导体管芯包括静态弯曲部，使得每个半导体管芯的端部部分平行于该方向并且机械地耦合到斜坡部件。这些末端段可以例如通过邻近通信促进芯片与斜坡组件之间的信号的高带宽通信。

4. 发明申请

WO2015094259A1 FLEXIBLY-WRAPPED INTEGRATED CIRCUIT DIE 审中-公开
标题翻译：柔性包裹式集成电路
公开(公告)号：WO2015094259A1
公开(公告)日：2015-06-25
申请号：PCT/US2013/076397
申请日：2013-12-19
申请人： INTEL CORPORATION , ALBERS, Sven , SKINNER, Michael , BARTH, Hans-Joachim , BAUMGARTNER, Peter , GOSSNER, Harald
发明人： ALBERS, Sven , SKINNER, Michael , BARTH, Hans-Joachim , BAUMGARTNER, Peter , GOSSNER, Harald
IPC分类号： H01L23/12
CPC分类号： H01L25/0652 , H01L23/367 , H01L23/3675 , H01L23/5226 , H01L23/5227 , H01L23/552 , H01L23/562 , H01L23/564 , H01L23/66 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/48 , H01L24/49 , H01L24/81 , H01L24/85 , H01L25/065 , H01L25/0657 , H01L27/0207 , H01L29/0657 , H01L2223/6677 , H01L2224/131 , H01L2224/1319 , H01L2224/16105 , H01L2224/16113 , H01L2224/16225 , H01L2224/16227 , H01L2224/48091 , H01L2224/481 , H01L2224/48106 , H01L2224/4813 , H01L2224/48137 , H01L2224/48145 , H01L2224/48225 , H01L2224/48227 , H01L2224/48482 , H01L2224/49 , H01L2224/73257 , H01L2224/81001 , H01L2224/81007 , H01L2224/8114 , H01L2224/81801 , H01L2224/8185 , H01L2224/85801 , H01L2225/06506 , H01L2225/0651 , H01L2225/06551 , H01L2225/06589 , H01L2924/00014 , H01L2924/19104 , H01L2224/45099 , H01L2224/05599 , H01L2224/45015 , H01L2924/207 , H01L2924/014 , H01L2924/00012
摘要： Embodiments of a flexibly-wrapped integrated circuit die device and a method for mounting a flexibly-wrapped integrated circuit die to a substrate are disclosed. In some embodiments, the flexibly-wrapped integrated circuit die device includes a substrate and a flexible integrated circuit die coupled to the substrate in a substantially vertical orientation with reference to a surface of the substrate.
摘要翻译：公开了一种柔性包裹的集成电路管芯器件的实施例和用于将柔性封装的集成电路管芯安装到衬底的方法。在一些实施例中，柔性包裹的集成电路管芯器件包括基板和柔性集成电路管芯，所述基板和基板相对于基板的表面以基本垂直的取向联接到基板。

5. 发明申请

WO2015064953A1 전자 부품의 제조 방법 审中-公开
标题翻译：制造电子元件的方法
公开(公告)号：WO2015064953A1
公开(公告)日：2015-05-07
申请号：PCT/KR2014/009947
申请日：2014-10-22
申请人： 하나마이크론(주)
发明人： 임재성 , 김주형
IPC分类号： H01L21/48 , H01L21/58
CPC分类号： H01L24/80 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/3677 , H01L23/3736 , H01L23/4985 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/97 , H01L2221/68318 , H01L2221/68327 , H01L2221/6834 , H01L2221/68377 , H01L2221/68381 , H01L2224/73204 , H01L2224/73265 , H01L2224/75252 , H01L2224/75315 , H01L2224/80203 , H01L2224/81005 , H01L2224/81007 , H01L2224/81191 , H01L2224/81203 , H01L2224/83005 , H01L2224/83007 , H01L2224/83203 , H01L2224/97 , H01L2924/3511 , H01L2224/81 , H01L2224/83
摘要： 유연한 구조를 갖는 전자 부품의 제조 방법은 휘어지거나 펼칠 수 있는 유연한 구조로 이루어지면서 열전달이 가능한 열전달부가 패터닝되는 구조를 갖는 제1 기판, 휘어지거나 펼칠 수 있는 유연한 구조로 이루어지면서 일면에 전기 연결이 가능한 제1 패드가 구비되는 집적회로 소자, 및 휘어지거나 펼칠 수 있는 유연한 구조로 이루어지면서 상기 기판과 상기 집적회로 소자가 서로 접착되도록 상기 기판과 상기 집적회로 소자 사이에 구비되는 접착 필름을 포함하는 휘어지거나 펼칠 수 있는 유연한 구조를 갖는 집적회로 소자 패키지를 형성하는 단계; 휘어지거나 펼칠 수 있는 유연한 구조로 이루어지면서 일면에 전기 연결이 가능한 제2 패드가 구비되는 제2 기판을 형성하는 단계; 및 상기 집적회로 소자의 제1 패드와 상기 제2 기판의 제2 패드를 서로 면접시켜 전기적으로 연결시키면서 상기 제2 기판에 상기 집적회로 소자 패키지가 접착되도록 열압착(thermo-compression) 공정을 수행하고, 상기 열압착 공정을 수행할 때 상기 열전달부를 통하여 상기 제1 기판으로부터 상기 제2 기판으로 열전달이 이루어지는 단계를 포함할 수 있다.
摘要翻译：一种用于制造具有柔性结构的电子部件的方法可以包括以下步骤：形成具有可折叠且可扩展的柔性结构的集成电路元件封装，所述集成电路元件封装包括具有可折叠且可扩展的柔性结构的第一基板，具有能够传递热量的传热部件的结构被图案化，集成电路元件具有可折叠且可扩张的柔性结构，并且具有一个表面可电连接的第一焊盘，以及具有可折叠和可扩展的粘合膜，柔性结构，其设置在基板和集成电路元件之间，使得基板和集成电路元件可以彼此粘合; 形成具有可折叠和可扩张的柔性结构的第二基底，并具有第二垫，其中一个表面可电连接; 以及进行热压缩处理，以便将集成电路元件封装粘附到第二基板，同时通过表面接触将集成电路元件的第一焊盘与第二焊盘的第二焊盘电连接，其中热量从第一焊盘当进行热压缩处理时，经由传热部分将第二基板的基板接合到第二基板。

6. 发明申请

WO2015060978A1 TECHNIQUE FOR CONTROLLING POSITIONS OF STACKED DIES 审中-公开
标题翻译：控制堆叠位置的技术
公开(公告)号：WO2015060978A1
公开(公告)日：2015-04-30
申请号：PCT/US2014/057237
申请日：2014-09-24
申请人： ORACLE INTERNATIONAL CORPORATION
发明人： DAYRINGER, Michael, H., S. , HOPKINS, R., David , CHOW, Alex
IPC分类号： H01L25/065 , H01L21/98
CPC分类号： H01L25/50 , H01L23/544 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/72 , H01L24/75 , H01L24/81 , H01L25/0652 , H01L25/0657 , H01L2223/54426 , H01L2224/0401 , H01L2224/05555 , H01L2224/0557 , H01L2224/10135 , H01L2224/10165 , H01L2224/131 , H01L2224/1329 , H01L2224/133 , H01L2224/1601 , H01L2224/16105 , H01L2224/16135 , H01L2224/16151 , H01L2224/1703 , H01L2224/2919 , H01L2224/29193 , H01L2224/32145 , H01L2224/73103 , H01L2224/73203 , H01L2224/73257 , H01L2224/75705 , H01L2224/7598 , H01L2224/81007 , H01L2224/81129 , H01L2224/81141 , H01L2224/81815 , H01L2224/8185 , H01L2224/81898 , H01L2224/819 , H01L2224/8313 , H01L2224/83132 , H01L2224/83136 , H01L2224/83193 , H01L2224/8385 , H01L2224/92143 , H01L2225/06517 , H01L2225/06531 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2225/06589 , H01L2924/10253 , H01L2924/1431 , H01L2924/1434 , H01L2924/1436 , H01L2924/37001
摘要： An assembly component (100) and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies (310-1 - 310-N) that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terrace (112-1) at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component (100). In particular, the assembly component may include a pair of stepped terraces (112-1,112-2) that approximately mirror the stepped terrace of the chip package and which provide vertical position references for an assembly tool that positions the set of semiconductor dies in the vertical stack during assembly of the chip package.
摘要翻译：描述了组装部件（100）和使用组件部件组装芯片封装的技术。该芯片封装包括沿垂直方向布置成堆叠的一组半导体管芯（310-1-310-N），它们在水平方向上彼此偏移以限定位于垂直堆叠的一侧。此外，芯片封装可以使用组装部件（100）组装。特别地，组件部件可以包括一对阶梯式台阶（112-1,112-2），其近似地反映了芯片封装的阶梯式台阶，并且为组装工具提供垂直位置参考，该组装工具将该组半导体管芯定位在垂直方向在组装芯片封装期间堆叠。

7. 发明申请

WO2014204771A1 METHOD OF FORMING A MICROELECTRONIC ASSEMBLY BY PLATING METAL CONNECTORS AFTER ASSEMBLYING FIRST AND SECOND COMPONENTS AND CORRESPONDING DEVICE 审中-公开
标题翻译：在组装第一和第二组件和相应设备之后通过金属连接器的形成形成微电子组件的方法
公开(公告)号：WO2014204771A1
公开(公告)日：2014-12-24
申请号：PCT/US2014/042064
申请日：2014-06-12
申请人： INVENSAS CORPORATION
发明人： HABA, Belgacem , WOYCHIK, Charles, G. , UZOH, Cyprian, Emeka , NEWMAN, Michael , CASKEY, Terrence
IPC分类号： H01L21/60 , H01L23/485 , H01L21/98 , H01L25/065
CPC分类号： H01L24/13 , H01L21/563 , H01L23/564 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L2224/02372 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/0347 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/05147 , H01L2224/05155 , H01L2224/05557 , H01L2224/05568 , H01L2224/05571 , H01L2224/05609 , H01L2224/05611 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05657 , H01L2224/05664 , H01L2224/10145 , H01L2224/1146 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11903 , H01L2224/13024 , H01L2224/13025 , H01L2224/13109 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/13164 , H01L2224/1319 , H01L2224/14517 , H01L2224/1601 , H01L2224/16057 , H01L2224/16058 , H01L2224/16104 , H01L2224/16105 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16503 , H01L2224/17505 , H01L2224/17517 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81001 , H01L2224/81007 , H01L2224/811 , H01L2224/81139 , H01L2224/8192 , H01L2224/83104 , H01L2224/9201 , H01L2224/9212 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2924/00014 , H05K1/181 , H05K3/30 , Y10T29/4913 , H01L2924/00012 , H01L2924/01015 , H01L2924/01074 , H01L2224/05552
摘要： Microelectronic assemblies and methods for making the same are disclosed herein. In one embodiment, a method of forming a microelectronic assembly comprises: assembling first and second components (102, 128) to have first major surfaces (104, 130) of the first and second components (102, 128) facing one another and spaced apart from one another by a predetermined spacing, the first component (102) having first and second oppositely-facing major surfaces (104, 106), a first thickness extending in a first direction between the first and second major surfaces (104, 106), and a plurality of first metal connection elements (112) at the first major surface (104), the second component (128) having a plurality of second metal connection elements (132) at the first major surface (130) of the second component (128); and then plating (electroplating or electroless plating) a plurality of metal connector regions (146) each connecting and extending continuously between a respective first connection element (112) and a corresponding second connection element (132) opposite the respective first connection element (112) in the first direction. The first and second metal connection elements (112, 132) may comprise metal vias (116, 134) in the components (102, 128) or metal pads (118) at the surface of the components (102, 128), the metal vias (116, 134) or the metal pads (118) being covered by plated metal regions (114). A first seed layer (126) may be formed overlying the major surface of the first component (102) before the plating process, wherein uncovered portions of the first seed layer (126) are removed after plating the metal connector regions (146). Similarly, a second seed layer (144) may be formed overlying the major surface of the second component (128). A plurality of barrier regions (152) may overlie the sidewalls of at least one of the metal connector regions (146), the first plated metal regions (114) or the second plated metal regions. At least some corresponding first and second metal connection elements (112, 132) may optionally not share a common axis. At least some first and second surfaces (113, 131) of the first metal connection elements (112) and the respective second metal connection elements (132) connected thereto may optionally not be parallel to a common plane.
摘要翻译：本文公开了微电子组件及其制造方法。在一个实施例中，形成微电子组件的方法包括：组装第一和第二部件（102,128）以使第一和第二部件（102,128）彼此面对并间隔开的第一主表面（104,130）第一部件（102）具有第一和第二相对的主表面（104,106），在第一和第二主表面（104,106）之间沿第一方向延伸的第一厚度，以及在所述第一主表面（104）处的多个第一金属连接元件（112），所述第二部件（128）在所述第二部件的所述第一主表面（130）处具有多个第二金属连接元件（132） 128）; 然后电镀（电镀或化学镀）多个金属连接器区域（146），每个金属连接器区域在相应的第一连接元件（112）和与相应的第一连接元件（112）相对的对应的第二连接元件（132）之间连续延伸并延伸，在第一个方向。第一和第二金属连接元件（112,132）可以包括组件（102,128）中的金属通孔（116,134）或元件（102,128）的表面处的金属焊盘（118），金属通孔（116,134）或金属焊盘（118）被电镀金属区域（114）覆盖。可以在电镀工艺之前，在第一部件（102）的主表面上形成第一种子层（126），其中在镀覆金属连接器区域（146）之后，去除第一籽晶层（126）的未覆盖部分。类似地，可以形成第二种子层（144），覆盖第二部件（128）的主表面。多个阻挡区域（152）可以覆盖金属连接器区域（146），第一电镀金属区域（114）或第二电镀金属区域中的至少一个的侧壁。至少一些对应的第一和第二金属连接元件（112,132）可以可选地不共享公共轴线。第一金属连接元件（112）和连接到其上的相应的第二金属连接元件（132）的至少一些第一和第二表面（113,131）可以可选地不平行于公共平面。

8. 发明申请

WO2012102270A1 半導体装置の製造方法审中-公开
标题翻译：生产半导体器件的方法
公开(公告)号：WO2012102270A1
公开(公告)日：2012-08-02
申请号：PCT/JP2012/051444
申请日：2012-01-24
申请人：日東電工株式会社 , 高本尚英 , 浅井文輝 , 志賀豪士
发明人：高本　尚英 , 浅井　文輝 , 志賀　豪士
IPC分类号： H01L21/02 , H01L21/301 , H01L23/00
CPC分类号： H01L23/544 , C09J2203/326 , H01L21/6836 , H01L23/3164 , H01L24/81 , H01L2221/68327 , H01L2221/68377 , H01L2223/54433 , H01L2223/5448 , H01L2224/131 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/81007 , H01L2224/81193 , H01L2224/81815 , H01L2224/83102 , H01L2224/83862 , H01L2224/92125 , H01L2924/01082 , H01L2924/00014 , H01L2924/01047 , H01L2924/01029 , H01L2924/0103 , H01L2924/01083 , H01L2924/014
摘要：フリップチップ型半導体裏面用フィルムに効率よくレーザーマーキングを行うことが可能な半導体装置の製造方法を提供することを目的とする。半導体装置の製造方法であって、フリップチップ型半導体裏面用フィルムと、フリップチップ型半導体裏面用フィルムの外周上に設けられたリング状の粘着剤層とを有する粘着剤層付き半導体裏面用フィルムを用意する工程Ａと、粘着剤層よりも内側の、粘着剤層が積層されていないフリップチップ型半導体裏面用フィルム上に、半導体ウエハを貼り付ける工程Ｂと、粘着剤層にダイシングリングを貼り付ける工程Ｃと、工程Ｂ及び工程Ｃの後に、フリップチップ型半導体裏面用フィルムにレーザーマーキングを行う工程Ｄとを具備する。
摘要翻译：其目的是提供一种用于制造半导体器件的方法，其可以有效地对用于倒装芯片半导体的后表面的膜进行激光标记。一种制造半导体器件的方法具有：制备具有倒装芯片半导体后表面膜和设置在倒装芯片半导体周边周围的环状粘合层的含粘合剂层的半导体背面膜的工序（A）后表面膜; 步骤（B），用于将半导体晶片粘贴到不具有粘合剂层的区域中的倒装芯片半导体后表面膜上，并且比粘合剂层更内侧; 用于将切割环粘贴在粘合剂层上的步骤（C）; 以及在步骤（B）和步骤（C）完成之后对倒装芯片半导体后表面膜进行激光标记的步骤（D）。

9. 发明申请

WO2016123609A3 LOCALIZED SEALING OF INTERCONNECT STRUCTURES IN SMALL GAPS 审中-公开
标题翻译：小间隙中互连结构的局部密封
公开(公告)号：WO2016123609A3
公开(公告)日：2016-09-29
申请号：PCT/US2016015951
申请日：2016-02-01
申请人： INVENSAS CORP
发明人： KATKAR RAJESH , UZOH CYPRIAN EMEKA , SITARAM ARKALGUD R
IPC分类号： H01L23/485 , H01L21/60 , H01L25/065
CPC分类号： H01L24/81 , H01L21/768 , H01L23/49838 , H01L23/528 , H01L24/11 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L25/50 , H01L2224/10126 , H01L2224/1182 , H01L2224/13023 , H01L2224/13105 , H01L2224/13109 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13184 , H01L2224/13562 , H01L2224/1357 , H01L2224/1379 , H01L2224/13809 , H01L2224/13811 , H01L2224/13847 , H01L2224/13855 , H01L2224/1601 , H01L2224/16014 , H01L2224/16058 , H01L2224/16145 , H01L2224/16227 , H01L2224/16238 , H01L2224/16503 , H01L2224/16507 , H01L2224/81007 , H01L2224/81048 , H01L2224/81143 , H01L2224/81193 , H01L2224/8181 , H01L2224/8182 , H01L2224/81862 , H01L2224/81895 , H01L2224/81903 , H01L2224/81905 , H01L2224/94 , H01L2924/01029 , H01L2924/01051 , H01L2924/01327 , H01L2924/364 , H01L2224/11 , H01L2224/81 , H01L2924/00014 , H01L2924/2064
摘要： An apparatus relates generally to a microelectronic device. In such an apparatus, a first substrate has a first surface with first interconnects located on the first surface, and a second substrate has a second surface spaced apart from the first surface with a gap between the first surface and the second surface. Second interconnects are located on the second surface. Lower surfaces of the first interconnects and upper surfaces of the second interconnects are coupled to one another for electrical conductivity between the first substrate and the second substrate. A conductive collar is around sidewalls of the first and second interconnects, and a dielectric layer is around the conductive collar.
摘要翻译：装置一般涉及微电子器件。在这样的装置中，第一基板具有第一表面，第一表面具有位于第一表面上的第一互连，并且第二基板具有第二表面，第二表面与第一表面隔开，第一表面与第二表面之间具有间隙。第二个互连位于第二个表面上。第一互连的下表面和第二互连的上表面为了第一基板和第二基板之间的导电性而彼此耦合。导电套环围绕第一和第二互连的侧壁，介电层围绕导电套环。

10. 发明申请

WO2014155099A1 COATED ELECTRICAL ASSEMBLY 审中-公开
标题翻译：涂层电气总成
公开(公告)号：WO2014155099A1
公开(公告)日：2014-10-02
申请号：PCT/GB2014/050945
申请日：2014-03-25
申请人： SEMBLANT LIMITED
发明人： DUNCAN, Elizabeth
IPC分类号： H05K3/28
CPC分类号： H05K3/282 , H01L21/32138 , H01L23/552 , H01L23/562 , H01L23/564 , H01L2224/80007 , H01L2224/81007 , H01L2224/82007 , H01L2224/83007 , H01L2224/84007 , H01L2224/85007 , H01L2224/86007 , H05K1/181 , H05K3/285 , H05K2201/09872 , H05K2203/095 , H05K2203/1322 , H05K2203/1333 , H05K2203/1377
摘要： The present invention relates to an electrical assembly which has a conformal coating, wherein said conformal coating is obtainable by a method which comprises: (a) plasma polymerization of a compound of formula (I) and a fluorohydrocarbon, wherein the molar ratio of the compound of formula (I) to the fluorohydrocarbon is from 5:95 to 50:50, and deposition of the resulting polymer onto at least one surface of the electrical assembly: wherein: R 1 represents C 1 -C 3 alkyl or C 2 -C 3 alkenyl; R 2 represents hydrogen, C 1 -C 3 alkyl or C 2 -C 3 alkenyl; R 3 represents hydrogen, C 1 -C 3 alkyl or C 2 -C 3 alkenyl; R 4 represents hydrogen, C 1 -C 3 alkyl or C 2 -C 3 alkenyl; R 5 represents hydrogen, C 1 -C 3 alkyl or C 2 -C 3 alkenyl; and R 6 represents hydrogen, C 1 -C 3 alkyl or C 2 -C 3 alkenyl, and (b) plasma polymerization of a compound of formula (I) and deposition of the resulting polymer onto the polymer formed in step (a).
摘要翻译：本发明涉及具有保形涂层的电气组件，其中所述保形涂层可通过以下方法获得：一种方法，该方法包括：（a）式（I）化合物和氟代烃的等离子体聚合，其中化合物式（I）的化合物为5:95至50:50，并将所得聚合物沉积在电组件的至少一个表面上：其中：R 1表示C 1 -C 3烷基或C 2 -C 3烯基; R2代表氢，C1-C3烷基或C2-C3烯基; R 3表示氢，C 1 -C 3烷基或C 2 -C 3烯基; R4表示氢，C1-C3烷基或C2-C3烯基; R5表示氢，C1-C3烷基或C2-C3烯基; 并且R 6表示氢，C 1 -C 3烷基或C 2 -C 3烯基，和（b）式（I）化合物的等离子体聚合和所得聚合物沉积在步骤（a）中形成的聚合物上。

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