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1. 发明申请

WO2018084980A1 STACKED ELECTRONICS PACKAGE AND METHOD OF MANUFACTURING THEREOF 审中-公开
标题翻译：堆叠电子封装及其制造方法
公开(公告)号：WO2018084980A1
公开(公告)日：2018-05-11
申请号：PCT/US2017/054695
申请日：2017-10-02
申请人： GENERAL ELECTRIC COMPANY
发明人： TUOMINEN, Risto, Ilkka , GOWDA, Arun, Virupaksha
IPC分类号： H01L25/065 , H01L25/07 , H01L25/16 , H01L25/18 , H01L25/00
CPC分类号： H01L24/24 , H01L23/49816 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L24/19 , H01L24/82 , H01L25/0657 , H01L25/074 , H01L25/16 , H01L25/18 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/16235 , H01L2224/16238 , H01L2224/2402 , H01L2224/24105 , H01L2224/24145 , H01L2224/24147 , H01L2224/24996 , H01L2224/25171 , H01L2224/25174 , H01L2224/2541 , H01L2224/32225 , H01L2224/32245 , H01L2224/73253 , H01L2224/73267 , H01L2224/92144 , H01L2924/15311 , H01L2924/15313
摘要： An electronics package includes an insulating substrate, a first electrical component coupled to a bottom surface of the insulating substrate, and a first conductor layer formed adjacent the bottom surface of the insulating substrate. The electronics package also includes a second conductor layer formed on a top surface of the insulating substrate and extending through a plurality of vias in the insulating substrate to electrically couple with the first electrical component and the first conductor layer. A second electrical component is electrically coupled to the first conductor layer and the first electrical component and the second electrical component are positioned in a stacked arrangement.
摘要翻译：电子组件包括绝缘基板，耦合到绝缘基板的底表面的第一电部件以及邻近绝缘基板的底表面形成的第一导体层。所述电子封装还包括第二导体层，所述第二导体层形成在所述绝缘基板的顶表面上并且延伸穿过所述绝缘基板中的多个通孔以与所述第一电气部件和所述第一导体层电耦合。第二电气元件电耦合至第一导体层，并且第一电气元件和第二电气元件以堆叠布置方式定位。

2. 发明申请

WO2018063154A1 3D STACKED-IN-RECESS SYSTEM IN PACKAGE 审中-公开
标题翻译：包装中的3D堆叠入库系统
公开(公告)号：WO2018063154A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/053935
申请日：2016-09-27
申请人： INTEL CORPORATION , CHEAH, Bok Eng , LIM, Min Suet , KONG, Jackson Chung Peng , LOO, Howe Yin
发明人： CHEAH, Bok Eng , LIM, Min Suet , KONG, Jackson Chung Peng , LOO, Howe Yin
IPC分类号： H01L25/065 , H01L23/538 , H01L23/48 , H01L21/48 , H01L23/00
CPC分类号： H01L21/48 , H01L23/00 , H01L23/48 , H01L23/538 , H01L23/552 , H01L25/0652 , H01L25/0655 , H01L25/18 , H01L25/50 , H01L29/0657 , H01L2224/13025 , H01L2224/16146 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/1432 , H01L2924/1434 , H01L2924/15192 , H01L2924/15311 , H01L2924/3025
摘要： A system in package device includes a landed first die disposed on a package substrate. The landed first die includes a notch that is contoured and that opens the backside surface of the die to a ledge. A stacked die is mounted at the ledge and the two dice are each contacted by a through-silicon via (TSV). The system in package device also includes a landed subsequent die on the package substrate and a contoured notch in the landed subsequent die and the notch in the first die form a composite contoured recess into which the stacked die is seated.
摘要翻译：封装装置中的系统包括设置在封装衬底上的落地第一管芯。落地的第一模具包括具有轮廓的凹口并且将模具的背面表面打开成凸缘。堆叠式芯片安装在壁架上，并且两个芯片分别与硅通孔（TSV）接触。封装装置中的系统还包括位于封装衬底上的落地后续裸片，落地后续裸片中的轮廓凹槽和第一裸片中的凹槽形成组合轮廓凹槽，堆叠裸片位于该凹槽中。

3. 发明申请

WO2018043888A1 필름형 반도체 밀봉 부재, 이를 이용하여 제조된 반도체 패키지 및 그 제조방법 审中-公开
标题翻译：薄膜型半导体密封部件，使用其制造的半导体封装及其制造方法
公开(公告)号：WO2018043888A1
公开(公告)日：2018-03-08
申请号：PCT/KR2017/006526
申请日：2017-06-21
申请人： 삼성에스디아이 주식회사
发明人： 권기혁 , 이윤만
IPC分类号： H01L23/31 , H01L23/29 , H01L21/56 , H01L23/498 , H01L25/065
CPC分类号： H01L21/56 , H01L23/29 , H01L23/31 , H01L23/498 , H01L25/065 , H01L2224/16225 , H01L2224/48091 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00014
摘要： 본 발명은, 유리 직물로 이루어진 제1층; 상기 제1층의 상부에 형성되고, 제1에폭시 수지 및 제1무기 충전제를 포함하는 제2층; 상기 제1층의 하부에 형성되고, 제2에폭시 수지 및 제2무기 충전제를 포함하는 제3층을 포함하며, 상기 제3층의 두께가 상기 제2층의 두께보다 두꺼운 필름형 반도체 밀봉 부재, 이를 이용하여 제조된 반도체 패키지 및 그 제조방법에 관한 것이다.
摘要翻译：＆lt; p num =“0000”＆gt;本发明涉及由玻璃织物制成的第一层; 形成在第一层上的第二层，第二层包含第一环氧树脂和第一无机填料; 在第一层的下部形成的膜状半导体密封部件，第三层包括第二环氧树脂和第二无机填料，第三层比第二层厚，本发明涉及使用其制造的半导体封装及其制造方法。

4. 发明申请

WO2018017222A1 BALL GRID ARRAY (BGA) WITH ANCHORING PINS 审中-公开
标题翻译：球栅阵列（BGA），带锚钉
公开(公告)号：WO2018017222A1
公开(公告)日：2018-01-25
申请号：PCT/US2017/037905
申请日：2017-06-16
申请人： INTEL CORPORATION
发明人： LIANG, Zuyang , GARCIA, Michael , HEPPNER, Joshua, D. , NEKKANTY, Srikant
IPC分类号： H01L23/498 , H01L23/495 , H01L23/00
CPC分类号： H01L23/49816 , H01L23/13 , H01L23/49811 , H01L23/49827 , H01L24/00 , H01L2924/15311 , H01L2924/16152 , H01R13/2485
摘要： Embodiments herein may relate to an electronic device that includes a board. The electronic device may include a device physically coupled with the board by an anchoring pin. The electronic device may further include a plurality of ball grid array (BGA) solder joints coupled with the device. For example, the BGA solder joints may electrically and/or communicatively couple one or more pins of the device with the board. The BGA solder joints may have a shape that is different than the anchoring pin. Other embodiments may be described and/or claimed.
摘要翻译：这里的实施例可以涉及包括板的电子设备。该电子设备可以包括通过锚定销与该板物理耦合的设备。电子器件可以进一步包括与器件耦合的多个球栅阵列（BGA）焊点。例如，BGA焊点可以电气和/或通信地将器件的一个或多个引脚与电路板耦合。 BGA焊点可能具有与锚定销不同的形状。其他实施例可以被描述和/或要求保护。

5. 发明申请

WO2018004869A1 SWITCHED CLOSED LOOP READ-OUT METHODS AND SYSTEMS FOR RESONANT SENSING PLATFORMS 审中-公开
标题翻译：用于谐振感测平台的开关闭环读取方法和系统
公开(公告)号：WO2018004869A1
公开(公告)日：2018-01-04
申请号：PCT/US2017/033385
申请日：2017-05-18
申请人： INTEL CORPORATION
发明人： DOGIAMIS, Georgios C. , OSTER, Sasha N. , EID, Feras , YOUNG, Ian A.
IPC分类号： G01R33/00
CPC分类号： G01R23/02 , G01D5/00 , G01D18/006 , G01P15/097 , H01L24/13 , H01L24/16 , H01L2224/131 , H01L2224/16227 , H01L2924/10253 , H01L2924/1432 , H01L2924/1434 , H01L2924/15159 , H01L2924/15311 , H01L2924/014 , H01L2924/00014
摘要： Embodiments of the invention include a resonant sensing system comprising driving circuitry to generate a drive signal during excitation time periods, a first switch coupled to the driving circuitry, and a sensing device coupled to the driving circuitry via the first switch during the excitation time periods. The sensing device includes beams to receive the drive signal during a first excitation time period that causes the beams to mechanically oscillate and generate a first induced electromotive force (emf) in response to the drive signal. The first switch decouples the sensing device and the driving circuitry during measurement time periods for measurement of the induced emf.
摘要翻译：本发明的实施例包括谐振感测系统，该谐振感测系统包括用于在激励时间段期间产生驱动信号的驱动电路，耦合到驱动电路的第一开关以及经由驱动电路耦合到驱动电路的感测设备在激励时间段内第一次切换。感测装置包括用于在第一激励时间段期间接收驱动信号的波束，该第一激励时间段使波束机械地振荡并响应于驱动信号产生第一感应电动势（emf）。第一个开关在测量时间段内将感测装置和驱动电路分开，以测量感应电动势。

6. 发明申请

WO2017222918A1 CHIP PACKAGE ASSEMBLY HAVING CONFORMAL LID 审中-公开
标题翻译：芯片封装组件具有一致的盖子
公开(公告)号：WO2017222918A1
公开(公告)日：2017-12-28
申请号：PCT/US2017/037784
申请日：2017-06-15
申请人： XILINX, INC.
发明人： GANDHI, Jaspreet Singh
IPC分类号： H01L23/04 , H01L23/00
CPC分类号： H01L23/13 , H01L23/04 , H01L23/367 , H01L23/3675 , H01L23/3737 , H01L23/5384 , H01L23/5385 , H01L23/562 , H01L23/585 , H01L25/0655 , H01L2224/16225 , H01L2224/73204 , H01L2224/73253 , H01L2924/15311 , H01L2924/16153 , H01L2924/16251 , H01L2924/3511
摘要： A chip package assembly and method for fabricating the same are provided which utilize a conformal lid (150, 450) to improve the chip package assembly from deformation. In one example, a chip package assembly is provided that includes integrated circuit (IC) dies, a packaging substrate, and a lid (250, 450). The packaging substrate has a die receiving area (120) that is defined by the laterally outermost extents of the IC dies mounted to the packaging substrate (150). The lid (150, 450) a surface that includes a first region (254) and a second region. The first region (254) is disposed over the first IC die (110) while the second region (258) of the lid (150, 450) extends below the second surface the first IC die (110) and is spaced above the packaging substrate (150). At least a portion of the second region (258) of the lid (150, 450) is overlapped with the die receiving area (120).
摘要翻译：提供了一种芯片封装组件及其制造方法，其利用共形盖（150,450）来改善芯片封装组件的变形。在一个示例中，提供了一种芯片封装组件，其包括集成电路（IC）管芯，封装衬底和盖（250,450）。封装衬底具有由安装到封装衬底（150）的IC裸片的横向最外部范围限定的裸片接收区域（120）。盖（150,450）包括第一区域（254）和第二区域的表面。第一区域（254）设置在第一IC管芯（110）上方，而盖（150,450）的第二区域（258）延伸到第一IC管芯（110）的第二表面下方并且在封装衬底（150）。盖（150,450）的第二区域（258）的至少一部分与管芯容纳区域（120）重叠。

7. 发明申请

WO2017189119A1 MICROELECTRONIC BOND PADS HAVING INTEGRATED SPRING STRUCTURES 审中-公开
标题翻译：具有集成弹簧结构的微电子粘结垫
公开(公告)号：WO2017189119A1
公开(公告)日：2017-11-02
申请号：PCT/US2017/023114
申请日：2017-03-19
申请人： INTEL CORPORATION
发明人： EID, Feras , SANKMAN, Robert L. , SANE, Sandeep B.
IPC分类号： H01L23/488 , H01L23/00
CPC分类号： H01L23/562 , H01L21/485 , H01L21/4853 , H01L23/49811 , H01L23/49816 , H01L23/49838 , H01L2224/16225 , H01L2924/15311 , H01L2924/3511
摘要： A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.
摘要翻译：可以制造微电子封装，其具有至少一个柔性外部接合焊盘，该至少一个柔性外部接合焊盘具有至少一个集成弹簧结构，用于减轻附连到外部基板期间微电子封装的翘曲的影响。用于微电子封装的实施例可以包括具有第一表面和相对的第二表面的微电子封装衬底，其中微电子封装衬底包括限定在其中的空隙，其从第二表面延伸到微电子封装衬底中，并且柔性接合焊盘其中所述柔性接合垫包括接地部分和至少一个弹簧部分，并且其中所述至少一个弹簧部分从所述柔性接合垫接合区部分延伸到所述微电子封装基板第二表面上的锚定结构。 / p>

8. 发明申请

WO2017142637A1 CHIP PACKAGE ASSEMBLY WITH POWER MANAGEMENT INTEGRATED CIRCUIT AND INTEGRATED CIRCUIT DIE 审中-公开
标题翻译：具有电源管理集成电路和集成电路芯片的芯片封装组件
公开(公告)号：WO2017142637A1
公开(公告)日：2017-08-24
申请号：PCT/US2017/012379
申请日：2017-01-05
申请人： XILINX, INC.
发明人： TRIMBERGER, Stephen, M. , MARDI, Mohsen, H. , MAHONEY, David, M.
IPC分类号： H01L25/16 , H01L25/065 , H01L23/00
CPC分类号： H01L25/18 , H01L23/49833 , H01L23/49838 , H01L23/5389 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/16 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/131 , H01L2224/16145 , H01L2224/16148 , H01L2224/16225 , H01L2224/16227 , H01L2224/1703 , H01L2224/17181 , H01L2224/81193 , H01L2225/06513 , H01L2225/06517 , H01L2225/06555 , H01L2225/06568 , H01L2225/06572 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/15153 , H01L2924/15192 , H01L2924/15311 , H01L2924/19107 , H01L2924/014 , H01L2924/00014
摘要： A chip package assembly (100, 200, 400, 600) is provided that includes a substrate (104), at least one integrated circuit (IC) die (102) and a power management integrated circuit (PMIC) (106). In one example, the IC die of the chip package assembly is disposed on a first surface (112) of the substrate. The PMIC die (106) has a first surface (116) having outputs (132) electrically coupled to the second surface of the IC die. The PMIC die (106) also has a second surface (118) facing away from the first surface. The second surface of the PMIC die (106) has inputs (132) that are electrically coupled to the first surface of the substrate.
摘要翻译：提供了一种芯片封装组件（100,200,400,600），其包括衬底（104），至少一个集成电路（IC）管芯（102）和功率管理集成电路（ PMIC）（106）。在一个示例中，芯片封装组件的IC裸片设置在衬底的第一表面（112）上。 PMIC管芯（106）具有第一表面（116），该第一表面（116）具有电耦合到IC管芯的第二表面的输出（132）。 PMIC管芯（106）还具有背离第一表面的第二表面（118）。 PMIC管芯（106）的第二表面具有电耦合到衬底的第一表面的输入（132）。

9. 发明申请

WO2017139410A1 INTEGRATED DEVICE COMPRISING A CAPACITOR THAT INCLUDES MULTIPLE PINS AND AT LEAST ONE PIN THAT TRAVERSES A PLATE OF THE CAPACITOR 审中-公开
标题翻译：包含电容器的集成器件，该电容器包括多个引脚并且至少一个引脚穿过电容器板
公开(公告)号：WO2017139410A1
公开(公告)日：2017-08-17
申请号：PCT/US2017/017059
申请日：2017-02-08
申请人： QUALCOMM INCORPORATED
发明人： GU, Shiqun , PANDEY, Shree Krishna , RADOJCIC, Ratibor
IPC分类号： H01L23/64 , H01L23/498 , H01L23/538 , H01L21/60 , H01L49/02
CPC分类号： H01L23/49838 , H01L21/4846 , H01L21/568 , H01L23/3128 , H01L23/49822 , H01L23/5389 , H01L23/642 , H01L24/17 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/16238 , H01L2224/16268 , H01L2224/18 , H01L2924/05042 , H01L2924/15311 , H01L2924/19011 , H01L2924/19041 , H01L2924/19102
摘要： Some features pertain to an integrated device that includes a die and a first redistribution portion coupled to the die. The first redistribution portion includes at least one dielectric layer and a capacitor. The capacitor includes a first plate, a second plate, and an insulation layer located between the first plate and the second plate. The first redistribution portion further includes several first pins coupled to the first plate of the capacitor. The first redistribution portion further includes several second pins coupled to the second plate of the capacitor. In some implementations, the capacitor includes the first pins and/or the second pins. In some implementations, at least one pin from the several first pins traverses through the second plate to couple to the first plate of the capacitor. In some implementations, the second plate comprises a fin design.
摘要翻译：一些特征涉及包括管芯和耦合到管芯的第一重新分配部分的集成器件。第一重新分配部分包括至少一个介电层和电容器。电容器包括第一板，第二板以及位于第一板和第二板之间的绝缘层。第一重新分配部分还包括耦合到电容器的第一板的多个第一引脚。第一重新分配部分还包括耦合到电容器的第二板的若干第二引脚。在一些实现中，电容器包括第一引脚和/或第二引脚。在一些实施方式中，来自多个第一引脚的至少一个引脚横穿第二板以耦合到电容器的第一板。在一些实现中，第二板包括翅片设计。

10. 发明申请

WO2017135111A1 回路基板および回路基板の製造方法审中-公开
标题翻译：电路板和制造电路板的方法
公开(公告)号：WO2017135111A1
公开(公告)日：2017-08-10
申请号：PCT/JP2017/002396
申请日：2017-01-24
申请人：富士ゼロックス株式会社 , 株式会社野田スクリーン
发明人：井口　大介 , 服部　篤典
IPC分类号： H05K3/46 , H01L23/12 , H05K1/16
CPC分类号： H01L24/17 , H01L21/4875 , H01L23/492 , H01L23/5223 , H01L23/528 , H01L23/53214 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/16 , H01L25/50 , H01L2224/13144 , H01L2224/16225 , H01L2924/15174 , H01L2924/15311 , H01L2924/19041 , H01L2924/19105 , H01L2924/00014
摘要：回路基板は、基材と、前記基材上に設けられた第１の金属層と、当該第１の金属層上に設けられた誘電体層と、当該誘電体層上に設けられた第２の金属層とを有するキャパシタ層と、を備える。前記第１の金属層は、前記基材上に設けられ前記キャパシタ層を介して回路部品に電流を供給するキャパシタ素子の第１の端子が接続される、前記誘電体層から露出した第１の電極領域を有し、前記第２の金属層は、前記キャパシタ素子の第２の端子が接続される、当該第２の金属層が露出した第２の電極領域を有する。
摘要翻译：
所述电路板包括：衬底，设置在衬底上的第一金属层，设置在第一金属层上的介电层，介电并在该层上提供第二金属层。第一金属层，将电流供给到通过形成在基板上的电容器层的电路部件的电容元件的第一端子连接起来，第一从电介质层暴露并且第二金属层具有第二电极区域，电容器元件的第二端子连接到第二电极区域并且第二金属层被暴露在第二电极区域中。

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