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1. 发明申请

WO2017144573A1 EFFICIENTLY MICRO-TRANSFER PRINTING MICRO-SCALE DEVICES ONTO LARGE-FORMAT SUBSTRATES 审中-公开
标题翻译：有效微传输印刷微型设备到大型基板
公开(公告)号：WO2017144573A1
公开(公告)日：2017-08-31
申请号：PCT/EP2017/054140
申请日：2017-02-23
申请人： X-CELEPRINT LIMITED
发明人： BOWER, Christopher , MEITL, Matthew
IPC分类号： H01L21/683
CPC分类号： H01L25/167 , H01L21/67144 , H01L21/6835 , H01L24/97 , H01L25/0753 , H01L33/0095 , H01L33/62 , H01L2221/68354 , H01L2221/68368 , H01L2221/68381 , H01L2224/24227 , H01L2224/82007 , H01L2224/951 , H01L2224/95136 , H01L2924/12041 , H01L2924/12044 , H01L2924/14 , H01L2924/1815 , H01L2924/18162 , H01L2933/0066
摘要： A method of making a micro-transfer printed system includes providing a source wafer (10) having a plurality of micro-transfer printable source devices (12 arranged at a source spatial density; providing an intermediate wafer (20) having a plurality of micro-transfer printable intermediate supports (24) arranged at an intermediate spatial density less than or equal to the source spatial density; providing a destination substrate (30); micro-transfer printing the source devices from the source wafer to the intermediate supports of the intermediate wafer with a source stamp having a plurality of posts at a source transfer density to make an intermediate device (22) on each intermediate support; and micro-transfer printing the intermediate devices from the intermediate wafer to the destination substrate at a destination spatial density less than the source spatial density with an intermediate stamp having a plurality of posts at an intermediate transfer density less than the source transfer density.
摘要翻译：制造微转移印刷系统的方法包括提供具有多个微转移可印刷源装置（12）的源晶片（10），其以源空间密度排列;提供中间晶片（ 20），其具有以小于或等于所述源空间密度的中间空间密度布置的多个可微转印的中间支撑体（24）;提供目标基板（30）;将所述源设备从所述源晶圆利用具有源传输密度的多个柱的源印模在中间晶圆的中间支撑体上形成中间装置（22）;以及将中间装置从中间晶圆微传送到目的地基板以小于源空间密度的目标空间密度与具有中间转印密度小于中间转印密度的多个柱的中间印章相接触源传输密度。

2. 发明申请

WO2017142637A1 CHIP PACKAGE ASSEMBLY WITH POWER MANAGEMENT INTEGRATED CIRCUIT AND INTEGRATED CIRCUIT DIE 审中-公开
标题翻译：具有电源管理集成电路和集成电路芯片的芯片封装组件
公开(公告)号：WO2017142637A1
公开(公告)日：2017-08-24
申请号：PCT/US2017/012379
申请日：2017-01-05
申请人： XILINX, INC.
发明人： TRIMBERGER, Stephen, M. , MARDI, Mohsen, H. , MAHONEY, David, M.
IPC分类号： H01L25/16 , H01L25/065 , H01L23/00
CPC分类号： H01L25/18 , H01L23/49833 , H01L23/49838 , H01L23/5389 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/16 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/131 , H01L2224/16145 , H01L2224/16148 , H01L2224/16225 , H01L2224/16227 , H01L2224/1703 , H01L2224/17181 , H01L2224/81193 , H01L2225/06513 , H01L2225/06517 , H01L2225/06555 , H01L2225/06568 , H01L2225/06572 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/15153 , H01L2924/15192 , H01L2924/15311 , H01L2924/19107 , H01L2924/014 , H01L2924/00014
摘要： A chip package assembly (100, 200, 400, 600) is provided that includes a substrate (104), at least one integrated circuit (IC) die (102) and a power management integrated circuit (PMIC) (106). In one example, the IC die of the chip package assembly is disposed on a first surface (112) of the substrate. The PMIC die (106) has a first surface (116) having outputs (132) electrically coupled to the second surface of the IC die. The PMIC die (106) also has a second surface (118) facing away from the first surface. The second surface of the PMIC die (106) has inputs (132) that are electrically coupled to the first surface of the substrate.
摘要翻译：提供了一种芯片封装组件（100,200,400,600），其包括衬底（104），至少一个集成电路（IC）管芯（102）和功率管理集成电路（ PMIC）（106）。在一个示例中，芯片封装组件的IC裸片设置在衬底的第一表面（112）上。 PMIC管芯（106）具有第一表面（116），该第一表面（116）具有电耦合到IC管芯的第二表面的输出（132）。 PMIC管芯（106）还具有背离第一表面的第二表面（118）。 PMIC管芯（106）的第二表面具有电耦合到衬底的第一表面的输入（132）。

3. 发明申请

WO2017112252A1 SEMICONDUCTOR PACKAGE WITH TRENCHED MOLDING-BASED ELECTROMAGNETIC INTERFERENCE SHIELDING 审中-公开
标题翻译：半导体封装基于模压成型的电磁干扰屏蔽
公开(公告)号：WO2017112252A1
公开(公告)日：2017-06-29
申请号：PCT/US2016/063318
申请日：2016-11-22
申请人： INTEL CORPORATION
发明人： DIAS, Rajendra C. , LI, Eric J. , HEPPNER, Joshua D.
IPC分类号： H01L23/552 , H01L23/29 , H01L23/31 , H01L23/498 , H01L25/075 , H01L25/11
CPC分类号： H01L23/552 , H01L21/3105 , H01L21/31111 , H01L21/31116 , H01L21/4867 , H01L21/561 , H01L21/565 , H01L21/76877 , H01L21/78 , H01L23/3121 , H01L23/3128 , H01L23/3135 , H01L23/5283 , H01L23/5328 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/92 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L2224/131 , H01L2224/13111 , H01L2224/13147 , H01L2224/16227 , H01L2224/2919 , H01L2224/2929 , H01L2224/29388 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2224/81207 , H01L2224/92125 , H01L2224/97 , H01L2225/06506 , H01L2225/0651 , H01L2225/06517 , H01L2225/06541 , H01L2225/06558 , H01L2225/06568 , H01L2924/14 , H01L2924/1461 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/01029 , H01L2924/014 , H01L2924/00014 , H01L2924/00012 , H01L2224/81 , H01L2224/83 , H01L2224/85 , H01L2924/00
摘要： Semiconductor packages with electromagnetic interference (EMI) shielding and a method of manufacture therefor is disclosed. The semiconductor packages may house single electronic component or may be a system in a package (SiP) implementation. The EMI shielding may be provided on top of and along the periphery of the semiconductor package. The EMI shielding on the periphery may be formed of cured conductive ink or cured conductive paste disposed on sidewalls of molding that encapsulates the electronic component(s) provided on the semiconductor package. The vertical portions of the EMI shielding, including EMI shielding on the periphery may be formed by filling conductive ink in trenches formed in-situ with curing the molding. The top portion of the EMI shielding may additionally be cured conductive ink.
摘要翻译：公开了具有电磁干扰（EMI）屏蔽的半导体封装及其制造方法。半导体封装可以容纳单个电子组件或者可以是封装（SiP）实现中的系统。 EMI屏蔽可以设置在半导体封装的顶部并沿着其周边。周边上的EMI屏蔽可以由固化的导电油墨或固化的导电膏形成，固化的导电膏设置在封装设置在半导体封装上的电子组件的模制件的侧壁上。包括外围EMI屏蔽的EMI屏蔽的垂直部分可以通过在原位形成的沟槽中填充导电墨水并固化模制品来形成。 EMI屏蔽的顶部可以另外固化导电油墨。

4. 发明申请

WO2017111855A1 MICROPROCESSOR PACKAGE WITH FIRST LEVEL DIE BUMP GROUND WEBBING STRUCTURE 审中-公开
标题翻译：微处理器封装与第一级模具冲击地面网带结构
公开(公告)号：WO2017111855A1
公开(公告)日：2017-06-29
申请号：PCT/US2015/000431
申请日：2015-12-26
申请人： INTEL CORPORATION
发明人： ZHANG, Yu, Amos , MANUSHAROW, Mathew, J. , AYGUN, Kemal , MAZUMDER, Mohiuddin
IPC分类号： H01L23/48
CPC分类号： H01L23/48 , H01L23/50 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/13101 , H01L2224/1412 , H01L2224/16225 , H01L2224/17515 , H01L2224/81801 , H01L2924/14 , H01L2924/00014 , H01L2924/014
摘要： A ground isolation webbing structure package includes a top level with an upper interconnect layer having upper ground contacts, upper data signal contacts, and a conductive material upper ground webbing structure that is connected to the upper ground contacts and surrounds the upper data signal contacts. The upper contacts may be formed over and connected to via contacts or traces of a lower layer of the same interconnect level. The via contacts of the lower layer may be connected to upper contacts of a second interconnect level which may also have such webbing. There may also be at least a third interconnect level having such webbing. The webbing structure electrically isolates and reduces cross talk between the signal contacts, thus providing higher frequency and more accurate data signal transfer between devices such as integrated circuit (IC) chips attached to a package.
摘要翻译：接地隔离带状结构封装包括具有上互连层的顶层，所述上互连层具有上接地触点，上数据信号触点以及连接到所述上接地触点的导电材料上接地带状结构，以及围绕上部数据信号触点。上触点可以形成在相同互连层的下层的通孔触点或迹线上并连接到该通孔触点或迹线。下层的通孔触点可以连接到也可以具有这种织带的第二互连级的上触点。也可能有至少一个具有这种织带的第三互连层。该带状结构电隔离并减少信号触点之间的串扰，从而在诸如附接到封装的集成电路（IC）芯片之类的器件之间提供更高频率和更精确的数据信号传输。

5. 发明申请

WO2017066079A1 INTERPOSER-LESS STACK DIE INTERCONNECT 审中-公开
标题翻译：无干扰的互连模块互连
公开(公告)号：WO2017066079A1
公开(公告)日：2017-04-20
申请号：PCT/US2016/055819
申请日：2016-10-06
申请人： XILINX, INC.
发明人： CHAWARE, Raghunandan , MAJUMDAR, Amitava , O'ROURKE, Glenn , SINGH, Inderjit
IPC分类号： H01L25/065 , H01L23/48 , H01L21/768 , H01L23/00
CPC分类号： H01L23/5385 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L22/14 , H01L23/3114 , H01L23/538 , H01L23/5381 , H01L23/5384 , H01L23/5386 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/92 , H01L24/94 , H01L24/96 , H01L25/0652 , H01L25/0655 , H01L25/18 , H01L2221/68327 , H01L2221/68331 , H01L2221/68372 , H01L2224/03312 , H01L2224/0332 , H01L2224/0345 , H01L2224/03462 , H01L2224/12105 , H01L2224/131 , H01L2224/16145 , H01L2224/16227 , H01L2224/1703 , H01L2224/17051 , H01L2224/17181 , H01L2224/73204 , H01L2224/81191 , H01L2224/92 , H01L2224/94 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/1461 , H01L2924/1515 , H01L2924/152 , H01L2924/153 , H01L2924/15311 , H01L2224/03 , H01L2924/014 , H01L2924/00014 , H01L21/78 , H01L2221/68304 , H01L2224/81 , H01L21/56 , H01L21/304 , H01L2224/11 , H01L2221/68381 , H01L22/00 , H01L2224/1181
摘要： Techniques for providing a semiconductor assembly having an interconnect die (106) for die-to-die interconnection, an IC package (100), a method for manufacturing, and a method for routing signals in an IC package are described. In one implementation, a semiconductor assembly is provided that includes a first interconnect die (106) coupled to a first integrated circuit (IC) die (102) and a second IC die (102) by inter-die connections (108). The first interconnect die includes solid state circuitry (122) that provides a signal transmission path between the IC dice.
摘要翻译：提供一种半导体组件的技术，该半导体组件具有用于管芯间互连的互连管芯（106），IC封装（100），制造方法以及用于在IC中路由信号的方法包描述。在一个实施方式中，提供了一种半导体组件，其包括通过晶粒间连接（108）耦合到第一集成电路（IC）管芯（102）和第二IC管芯（102）的第一互连管芯（106）。第一互连裸片包括在IC裸片之间提供信号传输路径的固态电路（122）。

6. 发明申请

WO2017053560A1 LOW PROFILE PACKAGE WITH PASSIVE DEVICE 审中-公开
标题翻译：具有被动设备的低配置包
公开(公告)号：WO2017053560A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/053101
申请日：2016-09-22
申请人： QUALCOMM INCORPORATED
发明人： SONG, Young Kyu , LEE, Jong-Hoon , JOW, Uei-Ming
IPC分类号： H01L23/538 , H01L25/16 , H01L21/60 , H01L25/065 , H01L23/552
CPC分类号： H01L23/552 , H01L21/4846 , H01L21/4853 , H01L23/498 , H01L23/49838 , H01L23/50 , H01L23/5383 , H01L23/5389 , H01L24/20 , H01L25/065 , H01L25/16 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/24137 , H01L2224/24246 , H01L2224/32245 , H01L2224/73253 , H01L2224/73267 , H01L2224/81815 , H01L2224/83005 , H01L2224/83192 , H01L2224/92225 , H01L2225/06517 , H01L2225/06537 , H01L2225/06572 , H01L2924/14 , H01L2924/1421 , H01L2924/1434 , H01L2924/15311 , H01L2924/15313 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3025 , H01L2924/37001
摘要： Provided is a low-profile package and related techniques for use and fabrication. In an example, a low-profile package is provided. The low-profile package includes an exemplary integrated circuit (IC) (112) having an active face (114), an integrated passive device (IPD) (102) having a face, and a redistribution layer (RDL) (106,108) disposed between the IPD and the IC. The IC is embedded in a substrate (104). The active face of the IC faces the face of the IPD in a face-to-face (F2F) configuration. At least one contact of the IPD is arranged in an overlapping configuration relative to the IC. The RDL is configured to electrically couple the IPD with the IC. The RDL can be disposed between the IPD and the IC, can be embedded in the substrate, and can be configured as an electromagnetic shield.
摘要翻译：提供了一种低调的包装和相关的使用和制造技术。在一个例子中，提供了一个薄型包装。薄型封装包括具有有源面（114），具有面的集成无源器件（IPD）（102））和再分配层（RDL）（106,108）的示例性集成电路（112） IPD和IC。 IC嵌入基板（104）中。 IC的主动面以面对面（F2F）配置面对IPD的脸部。 IPD的至少一个触点以相对于IC的重叠配置布置。 RDL被配置为将IPD与IC电耦合。 RDL可以设置在IPD和IC之间，可以嵌入在基板中，并且可以配置为电磁屏蔽。

7. 发明申请

WO2017050911A1 DISPOSITIF DE PROTECTION D'UN CIRCUIT ÉLECTRONIQUE AVEC DÉTECTION D'UN CHANGEMENT DE RÉACTANCE ÉLECTRIQUE 审中-公开
标题翻译：用于保护电子电路的装置，用于检测电气变化的变化
公开(公告)号：WO2017050911A1
公开(公告)日：2017-03-30
申请号：PCT/EP2016/072566
申请日：2016-09-22
申请人： THALES
发明人： DUPREZ, Adrien , SALIBA, Eric , THIZON, Christophe , GRISAL, Olivier , MIQUEL, Stéphane
IPC分类号： G06F21/86 , H01L23/00 , G09C1/00 , G06F21/87
CPC分类号： G09C1/00 , G06F21/87 , H01L23/576 , H01L2924/10253 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011
摘要： Dispositif de protection d'un circuit électronique avec détection d'un changement de réactance électrique Dispositif (1) de protection d'un circuit électronique comprenant : - des surface de maillage (2A, 2B) comprenant des cellules (3A, 3B) constituées par une portion continue de circuit électrique (20) et réparties sur les surfaces de maillage (2A, 2B), et - au moins un circuit électrique, comprenant : o une entrée d'injection d'un signal électrique, o une sortie de captage d'un signal électrique de sortie, et o entre ladite entrée et ladite sortie, au moins une desdites cellules (3A, 3B), le circuit électrique présentant une réactance électrique entre son entrée et sa sortie, le dispositif de protection (1) comprenant un module de détection (8) propre à détecter un changement de ladite réactance électrique.
摘要翻译：用于通过检测电抗变化来保护电子电路的装置。一种用于保护电子电路的装置（1），包括： - 网眼表面（2A，2B），包括由电路（20）的连续部分组成并分布在网格表面（2A，2B）上的单元（3A，3B）以及 - 至少一个电路，包括：o用于注入电信号的输入，用于捕获电输出信号的输出，以及所述输入和输出之间的o，所述单元（3A，3B）中的至少一个，所述单元电路在其输入和输出之间呈现电抗，该保护装置（1）包括能够检测所述电抗变化的检测模块（8）。

8. 发明申请

WO2017037206A1 ELECTRONIC DEVICE WITH EMBEDDED ELECTRONIC COMPONENT 审中-公开
标题翻译：具有嵌入式电子元件的电子设备
公开(公告)号：WO2017037206A1
公开(公告)日：2017-03-09
申请号：PCT/EP2016/070670
申请日：2016-09-01
申请人： AT & S AUSTRIA TECHNOLOGIE & SYSTEMTECHNIK AKTIENGESELLSCHAFT
发明人： GALLER, Christian , STUBENBERGER, Gerhard , LEITGEB, Markus , SCHRITTWIESER, Wolfgang
IPC分类号： H05K1/18
CPC分类号： H05K1/188 , H01L21/56 , H01L23/13 , H01L23/3107 , H01L23/5386 , H01L23/5389 , H01L2924/14 , H05K2201/0195 , H05K2201/09509 , H05K2203/1469
摘要： An electronic device (200) comprising a component carrier which comprises a component carrier body, an electrically conductive layer (220), and an adhesive structure (230). The electronic device (200) further comprises an electronic component (250) which is arranged within the component carrier body. The adhesive structure (230) is formed between an surface of the electronic component (250) and the electrically conductive layer (220) and covers only a part of the surface of the electronic component (250). A remaining part of the surface of the electronic component (250) is covered with the component carrier body.
摘要翻译：一种包括分量载体的电子器件（200），其包括部件载体主体，导电层（220）和粘合剂结构（230）。电子设备（200）还包括布置在部件载体主体内的电子部件（250）。粘合剂结构（230）形成在电子部件（250）的表面和导电层（220）之间，并且仅覆盖电子部件（250）的表面的一部分。电子部件（250）的表面的剩余部分被部件载体主体覆盖。

9. 发明申请

WO2016153552A1 SEMICONDUCTOR ASSEMBLY HAVING BRIDGE MODULE FOR DIE-TO-DIE INTERCONNECTION 审中-公开
标题翻译：具有用于DIE到DIE互连的桥式模块的半导体组件
公开(公告)号：WO2016153552A1
公开(公告)日：2016-09-29
申请号：PCT/US2015/054947
申请日：2015-10-09
申请人： XILINX, INC.
发明人： KWON, Woon-Seong , RAMALINGAM, Suresh
IPC分类号： H01L25/065 , H01L25/07 , H01L25/00 , H01L23/488 , H01L23/498 , H01L23/00 , H01L23/538
CPC分类号： H01L25/0655 , H01L21/56 , H01L21/568 , H01L23/3107 , H01L23/488 , H01L23/49816 , H01L23/5383 , H01L24/01 , H01L24/11 , H01L24/81 , H01L25/072 , H01L25/50 , H01L2224/11003 , H01L2224/16145 , H01L2224/1703 , H01L2224/73204 , H01L2224/81005 , H01L2224/81191 , H01L2224/81192 , H01L2224/81203 , H01L2224/81801 , H01L2224/92125 , H01L2224/97 , H01L2924/14 , H01L2924/15311 , H01L2924/18161
摘要： In one example, a semiconductor assembly comprises a first IC die (104A), a second IC die (104B), and a bridge module (110). The first IC die includes, on a top side thereof, first interconnects (108A) of a plurality of interconnects (108) and first inter-die contacts (608A) of a plurality of inter-die contacts (608). The second IC die includes, on a top side thereof, second interconnects (108B) of the plurality of interconnects and second inter-die contacts (608B) of the plurality of inter-die contracts. The bridge module is disposed between the first interconnects and the second interconnects and includes bridge interconnects (112) on a top side thereof, the bridge interconnects mechanically and electrically coupled to the plurality of inter-die contacts, and layer(s) of conductive interconnect (706) disposed on the top side thereof to route signals between the first IC and the second IC. A back side (710) of the bridge module does not extend beyond a height of the plurality of interconnects.
摘要翻译：在一个示例中，半导体组件包括第一IC管芯（104A），第二IC管芯（104B）和桥接模块（110）。第一IC芯片在其顶侧上包括多个互连（108）和多个晶片间接触（608）的第一晶片间触点（608A）的第一互连（108A）。第二IC管芯在其顶侧上包括多个互连件中的第二互连（108B）和多个管芯间合同的第二管芯间接触（608B）。桥模块设置在第一互连和第二互连之间，并且在其顶侧上包括桥互连（112），桥互连机械地和电耦合到多个管芯间接触和导电互连层（706）设置在其顶侧，以在第一IC和第二IC之间路由信号。桥模块的后侧（710）不延伸超出多个互连的高度。

10. 发明申请

WO2016105277A1 PROCESSING SYSTEM AND METHOD FOR LARGE SCALE SUBSTRATES 审中-公开
标题翻译：大规模基板的加工系统和方法
公开(公告)号：WO2016105277A1
公开(公告)日：2016-06-30
申请号：PCT/SG2015/050243
申请日：2015-07-30
申请人： ROKKO SYSTEMS PTE LTD
发明人： SHIN, Yun Suk , JUNG, Jong Jae , BAEK, Seung Ho
IPC分类号： H01L21/68 , H01L21/304 , H01L21/67
CPC分类号： H01L21/67144 , H01L24/97 , H01L2924/14
摘要： An alignment assembly for aligning a plurality of IC units, the assembly comprising: a plate having vacuum apertures for receiving said IC units on an engagement surface; a first alignment member having a plurality of projections and recesses uniformly distributed along a first engagement edge; a second alignment member having a plurality of projections and recesses uniformly distributed along a second engagement edge; said first and second alignment members in sliding contact with the engagement surface; wherein said first and second alignment members arranged to move relative to each other so as to intermesh said respective projections and recesses, said intermeshed projections and recesses arranged to define a linear array of rectangular apertures sized to fit said IC units in an aligned condition.
摘要翻译：一种用于对准多个IC单元的对准组件，所述组件包括：具有用于在所述接合表面上接收所述IC单元的真空孔的板; 第一对准构件，其具有沿着第一接合边缘均匀分布的多个突起和凹部; 第二对准构件，具有沿着第二接合边缘均匀分布的多个突起和凹部; 所述第一和第二对准构件与所述接合表面滑动接触; 其中所述第一和第二对准构件被布置成相对于彼此移动以便互相啮合所述相应的突起和凹部，所述相互啮合的突起和凹陷布置成限定矩形孔的线性阵列，其大小适于将所述IC单元配合成对准状态。

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