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1. 发明申请

WO2016202539A1 METHOD FOR PRODUCING A METALLIC CONTACT FACE BY USING A SHAPED METAL BODY SUPPORTED ON ONE SIDE, A POWER SEMICONDUCTOR WITH THE METALLIC CONTACT FACE AND A BOND SHIELD FOR PRODUCING THE METALLIC CONTACT FACE 审中-公开
标题翻译：通过使用支撑在一侧的成形金属体制造金属接触面的方法，具有金属接触面的功率半导体和用于生产金属接触面的粘结膜
公开(公告)号：WO2016202539A1
公开(公告)日：2016-12-22
申请号：PCT/EP2016/061747
申请日：2016-05-25
申请人： DANFOSS SILICON POWER GMBH
发明人： OSTERWALD, Frank , ULRICH, Holger , RUDZKI, Jacek , PAULSEN, Lars , BECKER, Martin , SCHEFUSS, Frank
IPC分类号： H01L21/60 , H01L23/485
CPC分类号： H01L24/02 , H01L23/3164 , H01L24/03 , H01L24/05 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/84 , H01L24/85 , H01L2224/02319 , H01L2224/02335 , H01L2224/0235 , H01L2224/0239 , H01L2224/03334 , H01L2224/03505 , H01L2224/04034 , H01L2224/04042 , H01L2224/05139 , H01L2224/05548 , H01L2224/05572 , H01L2224/05647 , H01L2224/371 , H01L2224/45014 , H01L2924/00014 , H01L2224/45099 , H01L2924/01029
摘要： A method for producing a metallic contact face, suitable for tying an electric conductor to it, for contacting a power semiconductor (10), having the following steps: applying a carrier film (20) on the power semiconductor (10) while leaving uncovered the power contacts of the power semiconductor (10); arranging a shaped metal body (30') on the carrier film (20) so that a first section arranged on the carrier film (20) forms a contact face for tying a wire or a ribbon and a second section of the shaped metal body projects above a power contact beyond the face of the carrier film (20), the carrier film (20) forming a single-sided support for the section, projecting beyond the face of the carrier film (20), of the shaped metal body (30'); and connecting the section of the shaped metal body (30') projecting beyond the face of the carrier film (20) to the power contact while deforming the shaped metal body (30'). Alternatively, a method for producing a metallic contact face, suitable for tying an electric conductor to it, for contacting a power semiconductor (10), having the following steps: applying a bond shield having a carrier film (20) and a shaped metal body (30') arranged on the carrier film (20), wherein the shaped metal body (30') comprises a first shaped metal body section arranged on the carrier film (20) and a second shaped metal body section projecting beyond the face of the carrier film (20), and the first shaped metal body section is connected to the second shaped metal body section via a deformation region on the power semiconductor (10), so that the shaped metal body section projecting beyond the face of the carrier foil (20) is arranged above a control or power contact of the power semiconductor (10); and connecting the shaped metal body section, projecting beyond the face of the carrier film (20), with the control or power contact while deforming the shaped metal body (30'). Connecting the section of the shaped metal body (30') projecting beyond the face of the carrier film (20) to the power contact takes place in particular via silver sintering.
摘要翻译：一种用于制造金属接触面的方法，适用于将电导体与其接合，用于接触功率半导体（10），具有以下步骤：将载体膜（20）施加到功率半导体（10）上，同时不覆盖功率半导体（10）的电源触点; 在载体膜（20）上布置成形金属体（30'），使得布置在载体膜（20）上的第一部分形成用于捆扎线或带的接触面，并且成形金属体的第二部分突出在载体膜（20）的表面之上的动力接触之上，载体膜（20）形成用于截面的单面支撑件，突出超过载体膜（20）的表面，成形金属体（30） “）; 并且在使所述成形金属体（30'）变形的同时将所述成形金属体（30'）的在所述载体膜（20）的表面上突出的部分连接到所述动力接触部。或者，一种用于制造金属接触面的方法，适用于将电导体与其接合，用于接触功率半导体（10），具有以下步骤：施加具有载体膜（20）和成形金属体（30'），其中所述成形金属体（30'）包括布置在所述载体膜（20）上的第一成形金属体部分和突出超过所述载体膜（20）的表面的第二成形金属体部分载体膜（20），并且第一成形金属体部通过功率半导体（10）上的变形区域连接到第二成形金属体部，使得成形金属体部突出超过载体箔（的表面） 20）布置在功率半导体（10）的控制或电源触点之上; 并且在使所述成形金属体（30'）变形的同时，使所述成形金属体部分突出超过所述载体膜（20）的表面与所述控制或动力接触。将穿过载体膜（20）的表面突出的成形金属体（30'）的部分连接到电源接触件特别是通过银烧结进行。

2. 发明申请

WO2014157520A1 保護膜形成用複合シート、保護膜付きチップ、及び保護膜付きチップの製造方法审中-公开
标题翻译：保护膜形成复合片，保护性膜片，以及制备保护性膜片的方法
公开(公告)号：WO2014157520A1
公开(公告)日：2014-10-02
申请号：PCT/JP2014/058868
申请日：2014-03-27
申请人：リンテック株式会社
发明人：山本　大輔 , 吾妻　祐一郎
IPC分类号： B32B27/20 , B32B27/00 , H01L21/301 , H01L23/00 , H01L23/29
CPC分类号： H01L23/3171 , B32B27/20 , B32B2307/302 , C08K2003/382 , C09J7/405 , C09J133/066 , C09J133/068 , C09J2203/326 , C09J2205/106 , C09J2433/00 , H01L21/6836 , H01L23/293 , H01L23/3164 , H01L23/544 , H01L2221/68327 , H01L2221/68377 , H01L2223/54486 , H01L2924/0002 , H01L2924/00 , C08F220/14 , C08F220/20 , C08F2220/325
摘要：　基材（１１）上に粘着剤層（１２）を有する粘着シート（１０）と、該粘着剤層（１２）上の少なくとも一部に、保護膜形成用組成物から形成されてなる保護膜形成用フィルム（２０）とを備える保護膜形成用複合シート（１ａ）であって、前記保護膜形成用組成物が、チッ化ホウ素粒子（Ｃ１）を含む無機フィラー（Ｃ）を含有し、（Ｃ）成分の含有量が、該保護膜形成用組成物の全量に対して、１０～７０質量％である、保護膜形成用複合シート（１ａ）は、放熱性及びマーキング性に優れた保護膜を形成し得ると共に、信頼性の高い保護膜付きチップを製造し得るという格別の効果を奏する。
摘要翻译：本发明提供一种保护膜形成复合片（1a），其具有在基板（11）的上方具有粘合剂层（12）的粘合片（10）和形成有保护膜形成膜（20）的保护膜形成复合片从粘合剂层（12）的至少一部分上的保护膜形成组合物。保护膜形成用组合物具有含有氮化硼粒子（C1）的非有机填料（C），（C）成分的含量相对于保护膜形成总量为10〜70质量％组成。保护膜形成复合片（1a）具有能够形成具有优异的散热特性和标记性能的保护膜的有利效果，并且还制造配备有高可靠性保护膜的芯片。

3. 发明申请

WO2012102270A1 半導体装置の製造方法审中-公开
标题翻译：生产半导体器件的方法
公开(公告)号：WO2012102270A1
公开(公告)日：2012-08-02
申请号：PCT/JP2012/051444
申请日：2012-01-24
申请人：日東電工株式会社 , 高本尚英 , 浅井文輝 , 志賀豪士
发明人：高本　尚英 , 浅井　文輝 , 志賀　豪士
IPC分类号： H01L21/02 , H01L21/301 , H01L23/00
CPC分类号： H01L23/544 , C09J2203/326 , H01L21/6836 , H01L23/3164 , H01L24/81 , H01L2221/68327 , H01L2221/68377 , H01L2223/54433 , H01L2223/5448 , H01L2224/131 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/81007 , H01L2224/81193 , H01L2224/81815 , H01L2224/83102 , H01L2224/83862 , H01L2224/92125 , H01L2924/01082 , H01L2924/00014 , H01L2924/01047 , H01L2924/01029 , H01L2924/0103 , H01L2924/01083 , H01L2924/014
摘要：フリップチップ型半導体裏面用フィルムに効率よくレーザーマーキングを行うことが可能な半導体装置の製造方法を提供することを目的とする。半導体装置の製造方法であって、フリップチップ型半導体裏面用フィルムと、フリップチップ型半導体裏面用フィルムの外周上に設けられたリング状の粘着剤層とを有する粘着剤層付き半導体裏面用フィルムを用意する工程Ａと、粘着剤層よりも内側の、粘着剤層が積層されていないフリップチップ型半導体裏面用フィルム上に、半導体ウエハを貼り付ける工程Ｂと、粘着剤層にダイシングリングを貼り付ける工程Ｃと、工程Ｂ及び工程Ｃの後に、フリップチップ型半導体裏面用フィルムにレーザーマーキングを行う工程Ｄとを具備する。
摘要翻译：其目的是提供一种用于制造半导体器件的方法，其可以有效地对用于倒装芯片半导体的后表面的膜进行激光标记。一种制造半导体器件的方法具有：制备具有倒装芯片半导体后表面膜和设置在倒装芯片半导体周边周围的环状粘合层的含粘合剂层的半导体背面膜的工序（A）后表面膜; 步骤（B），用于将半导体晶片粘贴到不具有粘合剂层的区域中的倒装芯片半导体后表面膜上，并且比粘合剂层更内侧; 用于将切割环粘贴在粘合剂层上的步骤（C）; 以及在步骤（B）和步骤（C）完成之后对倒装芯片半导体后表面膜进行激光标记的步骤（D）。

4. 发明申请

WO2009079040A1 ADHESIVE APPLICATIONS USING ALKALI SILICATE GLASS FOR ELECTRONICS 审中-公开
标题翻译：使用阿尔卡利硅酸盐玻璃进行电子应用
公开(公告)号：WO2009079040A1
公开(公告)日：2009-06-25
申请号：PCT/US2008/074224
申请日：2008-08-25
申请人： ROCKWELL COLLINS, INC. , LOWER, Nathan, P. , BOONE, Alan, P. , WILCOXON, Ross, K. , BROWER, David, M.
发明人： LOWER, Nathan, P. , BOONE, Alan, P. , WILCOXON, Ross, K. , BROWER, David, M.
IPC分类号： H01L21/70 , H01L21/60
CPC分类号： H01L24/29 , H01L21/50 , H01L21/563 , H01L23/10 , H01L23/291 , H01L23/3164 , H01L23/4334 , H01L24/16 , H01L24/27 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L25/0657 , H01L2224/16225 , H01L2224/29 , H01L2224/29101 , H01L2224/2919 , H01L2224/29288 , H01L2224/29305 , H01L2224/29309 , H01L2224/29311 , H01L2224/29313 , H01L2224/29339 , H01L2224/29344 , H01L2224/29347 , H01L2224/29355 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/4845 , H01L2224/48465 , H01L2224/73203 , H01L2224/73204 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2224/83855 , H01L2224/85205 , H01L2224/8592 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2924/00013 , H01L2924/01006 , H01L2924/01007 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01037 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01055 , H01L2924/01057 , H01L2924/01068 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/01105 , H01L2924/01327 , H01L2924/014 , H01L2924/0665 , H01L2924/09701 , H01L2924/10253 , H01L2924/12041 , H01L2924/14 , H01L2924/1461 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00014 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929
摘要： An integrated circuit assembly (100) comprises a substrate (102) and an integrated circuit (104) configured for being mounted to the substrate (102). At least one of the integrated circuit (104) and substrate (102) are at least partially coated with a low processing temperature, at least near-hermetic, glass-based coating (204). The coating (204) includes thermally conductive particles for promoting reduction of thermal resistance of the integrated circuit assembly (100).
摘要翻译：集成电路组件（100）包括衬底（102）和被配置为安装到衬底（102）的集成电路（104）。集成电路（104）和衬底（102）中的至少一个至少部分地涂覆有低处理温度，至少近乎密封的玻璃基涂层（204）。涂层（204）包括用于促进集成电路组件（100）的热阻降低的导热颗粒。

5. 发明申请

WO2003060985A1 SEMICONDUCTOR PACKAGE DEVICE AND METHOD 审中-公开
标题翻译：半导体封装器件和方法
公开(公告)号：WO2003060985A1
公开(公告)日：2003-07-24
申请号：PCT/US2002/041758
申请日：2002-12-31
申请人： MOTOROLA, INC., A CORPORATION OF THE STATE OF DELAWARE
发明人： CHASON, Marc, , DANVIR, Janice, , QI, Jing, , YALA, Nadia,
IPC分类号： H01L21/56
CPC分类号： H01L21/563 , H01L23/3164 , H01L2224/73203 , H05K3/3436 , H05K2201/10378 , H05K2201/10977 , Y02P70/613
摘要： An interposer-based semiconductor package (40) having at least one semiconductor die (21) attached to one side thereof also has, prior to placement on a printed wiring board (61), an underfill material (31) disposed at least partially thereon. Depending upon the embodiment, the underfill material (31) may initially cover interface electrodes (12) on the interposer (11). Such material (31) can be selectively removed to partially expose the interface electrodes (12). In other embodiments, apertures (101) can be left in the underfill material (31) during deposition, or formed after the underfill material (31) has been deposited, and the interface electrodes (12) subsequently formed in the apertures (101). Deposition of the underfill material (31) can be done with a single interposer-based package (40) or simultaneously with a plurality of such packages. Once deposited, the underfill material can be processed to render it relatively stable an substantially non-tacky. So processed, the package can be easily handled.
摘要翻译：在其一侧附近具有至少一个半导体管芯（21）的插入件半导体封装（40）在放置在印刷电路板（61）上之前还具有至少部分设置在其上的底部填充材料（31）。根据实施例，底部填充材料（31）可以初始地覆盖插入件（11）上的界面电极（12）。可以选择性地去除这种材料（31）以部分地暴露界面电极（12）。在其他实施例中，孔（101）可以在沉积期间留在底部填充材料（31）中，或者在已经沉积底部填充材料（31）之后形成，并且接口电极（12）随后形成在孔（101）中。底部填充材料（31）的沉积可以用单个基于插入件的包装（40）或与多个这样的包装同时进行。一旦沉积，可以处理底部填充材料使其相对稳定，基本上不粘。这样处理，包装很容易处理。

6. 发明申请

WO02019783A1 CIRCUIT BOARD UNIT AND METHOD OF MANUFACTURE THEREOF 审中-公开
标题翻译：电路板单元及其制造方法
公开(公告)号：WO02019783A1
公开(公告)日：2002-03-07
申请号：PCT/JP2000/005843
申请日：2000-08-29
IPC分类号： H01L21/60 , H01L23/04 , H01L23/31 , H05K3/28
CPC分类号： H01L24/81 , H01L23/04 , H01L23/3164 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/75 , H01L2224/81801 , H05K3/284
摘要： A circuit board unit (10) includes a circuit board (11) with conductive pads and an electronic device (13) with conductive terminals, which are electrically interconnected through the pads and the corresponding terminals. The electronic device (13) has a sheet (20) for covering itself on the circuit board (11) to seal the gap between the electronic device (13) and the circuit board (11).
摘要翻译：电路板单元（10）包括具有导电焊盘的电路板（11）和具有导电端子的电子设备（13），其通过焊盘和相应的端子电互连。电子设备（13）具有用于在电路板（11）上自身覆盖以密封电子设备（13）和电路板（11）之间的间隙的薄片（20）。

7. 发明申请

WO2013102146A1 DIE UP FULLY MOLDED FAN-OUT WAFER LEVEL PACKAGING 审中-公开
标题翻译： DIY UP全成型FAN-OUT WAFER LEVEL PACKAGING
公开(公告)号：WO2013102146A1
公开(公告)日：2013-07-04
申请号：PCT/US2012/072184
申请日：2012-12-28
申请人： DECA TECHNOLOGIES, INC. , SCANLAN, Christopher
发明人： SCANLAN, Christopher
IPC分类号： H01L21/50 , H01L23/48
CPC分类号： H01L21/76838 , H01L21/56 , H01L21/561 , H01L21/563 , H01L21/568 , H01L21/78 , H01L23/28 , H01L23/3114 , H01L23/3128 , H01L23/48 , H01L23/562 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/20 , H01L24/92 , H01L24/94 , H01L24/96 , H01L24/97 , H01L2224/12105 , H01L2224/131 , H01L2224/2101 , H01L2224/214 , H01L2224/215 , H01L2224/32225 , H01L2224/73267 , H01L2224/92 , H01L2224/94 , H01L2224/96 , H01L2224/97 , H01L2924/181 , H01L2924/3511 , H01L2224/20 , H01L2224/11 , H01L2924/01029 , H01L2924/014 , H01L2924/01028 , H01L2924/0105 , H01L2224/83 , H01L2924/00 , H01L2224/19 , H01L23/3164 , H01L2224/03
摘要： A method of manufacturing a semiconductor chip comprising placing a plurality of die units each having an active front surface and a back surface facing front surface up on an encapsulant layer, encapsulating the plurality of die units on the active surface of the encapsulant layer with an encapsulant covering a front surface and four side surfaces of each of the plurality of die units, and exposing, through the encapsulation on the front surface, conductive interconnects electrically connecting a die bond pad to redistribution layer.
摘要翻译：一种制造半导体芯片的方法，包括将具有活性前表面和背面的前表面的多个模具单元放置在密封剂层上，用密封剂将多个模具单元封装在密封剂层的活性表面上覆盖多个模具单元中的每一个的前表面和四个侧表面，并且通过前表面上的封装暴露导电互连件，以将管芯接合焊盘电连接到再分配层。

8. 发明申请

WO2013102137A2 FULLY MOLDED FAN-OUT 审中-公开
标题翻译：完全模制风扇
公开(公告)号：WO2013102137A2
公开(公告)日：2013-07-04
申请号：PCT/US2012/072164
申请日：2012-12-28
申请人： DECA TECHNOLOGIES, INC. , SCANLAN, Christopher
发明人： SCANLAN, Christopher
IPC分类号： H01L23/498 , H01L21/56 , H01L21/60
CPC分类号： H01L21/56 , H01L21/561 , H01L21/568 , H01L21/78 , H01L23/31 , H01L23/3114 , H01L23/3128 , H01L23/48 , H01L23/562 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/20 , H01L24/92 , H01L24/94 , H01L24/96 , H01L2224/12105 , H01L2224/131 , H01L2224/2101 , H01L2224/214 , H01L2224/215 , H01L2224/92 , H01L2224/94 , H01L2224/96 , H01L2924/181 , H01L2924/3511 , H01L2224/20 , H01L2924/01029 , H01L2924/014 , H01L2224/11 , H01L2924/01028 , H01L2924/0105 , H01L23/3164 , H01L2924/00
摘要： A method for manufacturing a device package may include constructing a spacer element coupled with a surface of a semiconductor die unit, where the spacer element is configured to create a gap between the semiconductor die unit and a surface of a carrier, and encapsulating the semiconductor die unit within a mold compound, where the encapsulating includes introducing the mold compound into the gap.
摘要翻译：用于制造器件封装的方法可以包括构造与半导体管芯单元的表面耦合的间隔元件，其中间隔元件构造成在半导体管芯单元和载体的表面之间产生间隙，并且封装半导体管芯单元在模具化合物中，其中包封包括将模具化合物引入到间隙中。

9. 发明申请

WO2009082516A3 ADHESIVE APPLICATIONS USING ALKALI SILICATE GLASS FOR ELECTRONICS 审中-公开
标题翻译：使用阿尔卡利硅酸盐玻璃进行电子应用
公开(公告)号：WO2009082516A3
公开(公告)日：2010-07-29
申请号：PCT/US2008075591
申请日：2008-09-08
申请人： ROCKWELL COLLINS INC , LOWER NATHAN P , BOONE ALAN P , WILCOXON ROSS K , BROWER DAVID M
发明人： LOWER NATHAN P , BOONE ALAN P , WILCOXON ROSS K , BROWER DAVID M
IPC分类号： H01L23/10 , H01L21/77
CPC分类号： H01L24/29 , H01L21/50 , H01L21/563 , H01L23/10 , H01L23/291 , H01L23/3164 , H01L23/4334 , H01L24/16 , H01L24/27 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L25/0657 , H01L2224/16225 , H01L2224/29 , H01L2224/29101 , H01L2224/2919 , H01L2224/29288 , H01L2224/29305 , H01L2224/29309 , H01L2224/29311 , H01L2224/29313 , H01L2224/29339 , H01L2224/29344 , H01L2224/29347 , H01L2224/29355 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/4845 , H01L2224/48465 , H01L2224/73203 , H01L2224/73204 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2224/83855 , H01L2224/85205 , H01L2224/8592 , H01L2225/0651 , H01L2225/06513 , H01L2225/06541 , H01L2924/00013 , H01L2924/01006 , H01L2924/01007 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/0102 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01037 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01055 , H01L2924/01057 , H01L2924/01068 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/01105 , H01L2924/01327 , H01L2924/014 , H01L2924/0665 , H01L2924/09701 , H01L2924/10253 , H01L2924/12041 , H01L2924/14 , H01L2924/1461 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00014 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929
摘要： A circuit assembly (2210) includes a substrate (2214) and an electrical component (2212) configured for being mounted to the substrate (2214). The electrical component (2212) and the substrate (2214) are at least partially coated with a glass-based coating (2218). The coating (2218) is configured to couple or attach the electrical component (2212) to the substrate (2214).
摘要翻译：电路组件（2210）包括衬底（2214）和被配置为安装到衬底（2214）上的电气部件（2212）。电气部件（2212）和基板（2214）至少部分地涂覆有玻璃基涂层（2218）。涂层（2218）被配置为将电气部件（2212）耦合或附接到基板（2214）。

10. 发明申请

WO2007050422A3 PLASTIC PACKAGED DEVICE WITH DIE INTERFACE LAYER 审中-公开
标题翻译：具有DIE接口层的塑料包装设备
公开(公告)号：WO2007050422A3
公开(公告)日：2009-05-14
申请号：PCT/US2006040871
申请日：2006-10-18
申请人： FREESCALE SEMICONDUCTOR INC , CONDIE BRIAN W , SHAH MAHESH K
发明人： CONDIE BRIAN W , SHAH MAHESH K
IPC分类号： H01L21/48 , H01L21/50 , H01L23/28 , H01L23/29
CPC分类号： H01L23/3192 , H01L23/3164 , H01L23/3171 , H01L23/4334 , H01L24/97 , H01L2224/48091 , H01L2924/01004 , H01L2924/01005 , H01L2924/01021 , H01L2924/01033 , H01L2924/01057 , H01L2924/01074 , H01L2924/01082 , H01L2924/09701 , H01L2924/14 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： Structure and method are provided for plastic encapsulated semiconductor devices having a buffer layer of low dielectric constant and/or low loss tangent material separating the die surface from the plastic encapsulation. Semiconductor wafers with substantially completed SC die (42) are coated with the buffer layer (52). The buffer layer is patterned to expose the die bonding pads (44) but leave the buffer layer over some or all of the other die metallization. The die are then separated, mounted on a lead-frame or other support, wire bonded or otherwise coupled to external leads, and encapsulated. The plastic encapsulation (47) surrounds the die and the buffer layer, providing a solid structure. The buffer layer reduces the parasitic capacitance, cross-talk and loss between metallization regions on the die. An optional sealing layer may also be provided at the wafer stage between the buffer layer and the plastic encapsulation to mitigate any buffer layer porosity.
摘要翻译：提供了具有低介电常数和/或低损耗正切材料的缓冲层的塑料封装的半导体器件的结构和方法，其将管芯表面与塑料封装分开。具有基本上完成的SC管芯（42）的半导体晶片被缓冲层（52）涂覆。对缓冲层进行图案化以使裸片接合焊盘（44）露出，但是将缓冲层留在其它管芯金属化部分或全部上。然后将管芯分离，安装在引线框架或其他支撑件上，引线键合或以其他方式耦合到外部引线，并封装。塑料封装（47）围绕裸片和缓冲层，提供坚实的结构。缓冲层减少了裸片上的金属化区域之间的寄生电容，串扰和损耗。也可以在缓冲层和塑料封装之间的晶片台处提供可选的密封层，以减轻任何缓冲层孔隙率。

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