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1. 发明申请

WO2011014434A3 BOND AND PROBE PAD DISTRIBUTION AND PACKAGE ARCHITECTURE 审中-公开
标题翻译：粘结和探针垫分布和包装结构
公开(公告)号：WO2011014434A3
公开(公告)日：2011-04-28
申请号：PCT/US2010043137
申请日：2010-07-23
申请人： ALTERA CORP , HATA WILLIAM Y
发明人： HATA WILLIAM Y
IPC分类号： H01L21/60 , H01L23/48
CPC分类号： H01L24/06 , H01L22/32 , H01L23/3171 , H01L2224/02166 , H01L2224/0392 , H01L2224/0401 , H01L2224/05553 , H01L2224/16 , H01L2224/48091 , H01L2224/49171 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01033 , H01L2924/01075 , H01L2924/01076 , H01L2924/014 , H01L2924/14 , H01L2924/15192 , H01L2924/00014
摘要： An integrated circuit (IC) that includes a plurality of bond pads disposed on a surface of the IC and a plurality of probe pads disposed on the surface of the IC is provided. Each of the plurality of probe pads is in electrical communication with corresponding bond pads. The plurality of probe pads are linearly configured across the surface. In one embodiment, the probe pads are disposed along a diagonal of the surface of the die defined between opposing vertices of the die surface. In another embodiment, multiple rows of linearly disposed probe pads are provided on the surface. In addition a packaging architecture for an integrated circuit is provided. The architecture includes a printed circuit board and a package substrate disposed on the printed circuit board. A first integrated circuit is disposed on a first surface of the package substrate. The package substrate is capable of supporting a second integrated circuit. The second integrated circuit is in electrical communication with a plurality of pads disposed on the first surface of the package substrate. Each of the plurality of pads is in electrical communication with the printed circuit board without communicating with the first integrated circuit.
摘要翻译：提供了一种集成电路（IC），其包括设置在IC表面上的多个接合焊盘和设置在IC表面上的多个探针焊盘。多个探针垫中的每一个都与对应的接合垫电连通。多个探测垫在表面上线性构造。在一个实施例中，探针垫沿着在芯片表面的相对顶点之间限定的芯片表面的对角线设置。在另一个实施例中，在表面上提供多行线性设置的探针垫。此外还提供了用于集成电路的封装体系结构。该架构包括印刷电路板和设置在印刷电路板上的封装衬底。第一集成电路设置在封装衬底的第一表面上。封装衬底能够支撑第二集成电路。第二集成电路与设置在封装衬底的第一表面上的多个焊盘电连通。多个垫中的每一个都与印刷电路板电通信，而不与第一集成电路通信。

2. 发明申请

WO2009141402A1 METHOD FOR MANUFACTURING AND TESTING AN INTEGRATED ELECTRONIC CIRCUIT 审中-公开
标题翻译：一体化电子电路的制造和测试方法
公开(公告)号：WO2009141402A1
公开(公告)日：2009-11-26
申请号：PCT/EP2009/056183
申请日：2009-05-20
申请人： STMICROELECTRONICS (GRENOBLE) SAS , COFFY, Romain
发明人： COFFY, Romain
IPC分类号： G01R31/28 , G01R1/20 , H01L21/66 , H01L23/485
CPC分类号： G01R31/2884 , G01R1/0408 , G01R31/2822 , H01L22/32 , H01L24/03 , H01L24/05 , H01L24/10 , H01L24/11 , H01L24/12 , H01L24/13 , H01L2224/03 , H01L2224/0392 , H01L2224/0401 , H01L2224/05553 , H01L2224/0558 , H01L2224/05639 , H01L2224/05644 , H01L2224/13 , H01L2224/13099 , H01L2224/13111 , H01L2224/16 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01058 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/15311 , H01L2924/30105 , H01L2924/30107 , H01L2224/11 , H01L2924/00
摘要： A method for manufacturing and for testing an integrated circuit, including the steps of forming, on the upper portion of the integrated circuit (1), a passivation layer (19) comprising openings at the level of metal tracks (17) of the last interconnect stack of the integrated circuit; forming, in the openings, first pads (11) connected to second pads (13) formed on the passivation layer by conductive track sections, the first pads being intended for the connection of the integrated circuit; testing the integrated circuit by bringing test tips in contact with the second pads; and eliminating at least a portion of at least one of the conductive track sections.
摘要翻译：一种用于制造和测试集成电路的方法，包括以下步骤：在集成电路（1）的上部形成钝化层（19），该钝化层包括位于最后互连的金属轨道（17）的开口处的开口堆叠的集成电路; 在所述开口中形成通过导电轨道部分连接到形成在所述钝化层上的第二焊盘（13）的第一焊盘（11），所述第一焊盘用于连接所述集成电路; 通过将测试头与第二个焊盘接触来测试集成电路; 以及消除所述导电轨道部分中的至少一个的至少一部分。

3. 发明申请

WO2009084700A1 SEMICONDUCTOR PACKAGE INCLUDING THROUGH-HOLE ELECTRODE AND LIGHT-TRANSMITTING SUBSTRATE 审中-公开
标题翻译：半导体封装，包括通孔电极和发光基板
公开(公告)号：WO2009084700A1
公开(公告)日：2009-07-09
申请号：PCT/JP2008/073882
申请日：2008-12-19
申请人： KABUSHIKI KAISHA TOSHIBA , KAWASAKI, Atsuko , MATSUO, Mie , INOUE, Ikuko , AYABE, Masayuki , SEKIGUCHI, Masahiro , TANIDA, Kazumasa
发明人： KAWASAKI, Atsuko , MATSUO, Mie , INOUE, Ikuko , AYABE, Masayuki , SEKIGUCHI, Masahiro , TANIDA, Kazumasa
IPC分类号： H01L27/14 , H01L21/3205 , H01L23/52 , H04N5/335
CPC分类号： H01L27/14618 , H01L21/76898 , H01L23/481 , H01L27/14636 , H01L2224/02372 , H01L2224/0392 , H01L2224/0401 , H01L2224/05548 , H01L2224/13022 , H01L2224/13024 , H04N5/2257
摘要： An imaging element is formed on the first main surface of a semiconductor substrate. An external terminal is formed on the second main surface of the semiconductor substrate. A through hole electrode is formed in a through hole formed in the semiconductor substrate. A first electrode pad is formed on the through hole electrode in the first main surface. An interlayer insulating film is formed on the first electrode pad and on the first main surface. A second electrode pad is formed on the interlayer insulating film. A passivation film is formed on the second electrode pad and the interlayer insulating film, and has an opening which exposes a portion of the second electrode pad. A contact plug is formed between the first and second electrode pads in a region which does not overlap the opening when viewed in a direction perpendicular to the surface of the semiconductor substrate.
摘要翻译：成像元件形成在半导体衬底的第一主表面上。外部端子形成在半导体衬底的第二主表面上。在形成在半导体衬底中的通孔中形成通孔电极。第一电极焊盘形成在第一主表面中的通孔电极上。在第一电极焊盘和第一主表面上形成层间绝缘膜。在层间绝缘膜上形成第二电极焊盘。在第二电极焊盘和层间绝缘膜上形成钝化膜，并且具有露出第二电极焊盘的一部分的开口。当在垂直于半导体衬底的表面的方向观察时，在不与开口重叠的区域中，在第一和第二电极焊盘之间形成接触插塞。

4. 发明申请

WO2004049436A1 SEMICONDUCTOR DEVICE HAVING A BOND PAD AND METHOD FOR ITS FABRICATION 审中-公开
标题翻译：具有BOND PAD的半导体器件及其制造方法
公开(公告)号：WO2004049436A1
公开(公告)日：2004-06-10
申请号：PCT/US2003/035964
申请日：2003-11-12
申请人： MOTOROLA, INC., A CORPORATION OF THE STATE OF DELAWARE
发明人： DOWNEY, Susan H. , HARPER, Peter R. , HESS, Kevin , LEONI, Michael, V. , TRAN, Tu-Anh
IPC分类号： H01L23/485
CPC分类号： H01L24/05 , H01L22/32 , H01L24/03 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/0657 , H01L2224/02166 , H01L2224/0392 , H01L2224/04042 , H01L2224/05001 , H01L2224/05082 , H01L2224/05155 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05553 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/32145 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/4813 , H01L2224/48145 , H01L2224/48227 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48724 , H01L2224/48744 , H01L2224/48747 , H01L2224/48824 , H01L2224/48844 , H01L2224/48847 , H01L2224/4911 , H01L2224/49112 , H01L2224/49113 , H01L2224/49431 , H01L2225/06506 , H01L2225/0651 , H01L2225/06596 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2924/01007 , H01L2924/00 , H01L2924/00012
摘要： A bond pad (200) has a first wire bond region (202) and a second wire bond region (204). In one embodiment, the first wire bond region (202) extends over a passivation layer (18). In an alternate embodiment, a bond pad has a probe region , a first wire bond region , and a second wire bond region . In one embodiment, the probe region and the wire bond region extend over a passivation layer (18). The bond pads may have any number of wire bond and probe regions and in any configuration. The ability for the bond pads to have multiple wire bond regions allows for multiple wire connections to a single bond pad, such as in multi-chip packages. The ability for the bond pads to extend over the passivation layer also allows for reduced integrated circuit die area.
摘要翻译：接合焊盘（200）具有第一引线接合区域（202）和第二引线接合区域（204）。在一个实施例中，第一引线接合区域（202）在钝化层（18）上延伸。在替代实施例中，接合焊盘具有探针区域，第一引线接合区域和第二引线接合区域。在一个实施例中，探针区域和引线接合区域在钝化层（18）上延伸。接合焊盘可以具有任何数量的引线键合和探针区域并且具有任何构造。接合焊盘具有多个引线接合区域的能力允许多个电线连接到单个接合焊盘，例如在多芯片封装中。接合焊盘在钝化层上延伸的能力也允许减小集成电路管芯面积。

5. 发明申请

WO00044041A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURE THEREOF 审中-公开
标题翻译：半导体集成电路及其制造
公开(公告)号：WO00044041A1
公开(公告)日：2000-07-27
申请号：PCT/JP1999/000232
申请日：1999-01-22
IPC分类号： G01R31/28 , H01L23/58 , H01L21/66 , G01R31/26
CPC分类号： H01L22/32 , G01R31/2884 , G01R31/31713 , H01L2224/02379 , H01L2224/0392 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit includes test pads (209b) of a conducting layer, such as a secondary interconnection layer (205), on or near terminals such as bonding pads (202b) that are used only for probing and are not provided with bump electrodes (208). Other terminals such as bonding pads provided with bump electrodes may include similar test pads. Probing is carried out on such test pads, or both on such test pads and an underlying metal layer on which bump electrodes are to be formed. The use of test pads eliminates the need for bump electrodes for dedicated probing pads. Since the test pads are formed near terminals such as bonding pads and smaller than metal parts under bump electrodes, probing can be carried out after a secondary interconnection process.
摘要翻译：半导体集成电路包括诸如二次互连层（205）之类的导电层（例如二次互连层）的测试焊盘（209b），例如仅用于探测的接合焊盘（202b）的端子上或附近，并且没有设置凸块电极 208）。诸如具有凸起电极的接合焊盘的其它端子可以包括类似的测试焊盘。在这些测试焊盘上进行探测，或者在这些测试焊盘上进行探测，并在其上形成凸起电极的底层金属层。使用测试焊盘消除了对专用探测焊盘的凸起电极的需要。由于测试焊盘形成在诸如焊盘之类的端子附近并且小于凸块电极下方的金属部件，所以可以在二次互连工艺之后进行探测。

7. 发明申请

WO2010106600A1 半導体装置及びその製造方法审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2010106600A1
公开(公告)日：2010-09-23
申请号：PCT/JP2009/006547
申请日：2009-12-02
申请人：パナソニック株式会社 , 竹村康司
发明人：竹村康司
IPC分类号： H01L21/60 , H01L21/3205 , H01L21/66 , H01L23/52
CPC分类号： H01L23/3171 , H01L22/32 , H01L23/3114 , H01L24/05 , H01L24/13 , H01L24/48 , H01L2224/02166 , H01L2224/02233 , H01L2224/02377 , H01L2224/02381 , H01L2224/0392 , H01L2224/0401 , H01L2224/05024 , H01L2224/05554 , H01L2224/05568 , H01L2224/0603 , H01L2224/131 , H01L2224/48091 , H01L2224/48227 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/10162 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要：　半導体装置は、半導体集積回路素子(1)を備えている。半導体集積回路素子(1)では、半導体基板(3)の上面の中央に半導体集積回路(5)が形成されており、半導体基板(3)の上面に複数の電極端子(7,7,…)が設けられている。半導体基板(3)の上面上には各電極端子(7)の上面を露出する保護膜(9)を備えている。そして、複数の電極端子(7,7,…)には、肉薄部(74)を有する電極端子(73)が存在している。肉薄部(74)の上面は、複数の電極端子(7,7,…)のうち肉薄部(74)を有する電極端子(73)以外の電極端子の上面よりも下に位置している。
摘要翻译：公开了一种具有半导体集成电路元件（1）的半导体器件。在半导体集成电路元件（1）中，半导体集成电路（5）形成在半导体衬底（3）的上表面的中心，并且半导体衬底（3）的上表面设置有多个的电极端子（7）。半导体衬底（3）的上表面还设置有保护膜（9），使得每个电极端子（7）的上表面从保护膜露出。一些电极端子（7）是电极端子（73），每个电极端子具有薄的部分（74）。每个薄部分（74）的上表面位于比具有薄部分（74）的电极端子（73）之外的电极端子的上表面的下表面。

8. 发明申请

WO2009084701A1 SEMICONDUCTOR PACKAGE AND CAMERA MODULE 审中-公开
标题翻译：半导体封装和相机模块
公开(公告)号：WO2009084701A1
公开(公告)日：2009-07-09
申请号：PCT/JP2008/073883
申请日：2008-12-19
申请人： KABUSHIKI KAISHA TOSHIBA , MATSUO, Mie , KAWASAKI, Atsuko , TAKAHASHI, Kenji , SEKIGUCHI, Masahiro , TANIDA, Kazumasa
发明人： MATSUO, Mie , KAWASAKI, Atsuko , TAKAHASHI, Kenji , SEKIGUCHI, Masahiro , TANIDA, Kazumasa
IPC分类号： H01L27/14 , H01L21/3205 , H01L23/52 , H04N5/335
CPC分类号： H04N5/2257 , H01L23/481 , H01L27/14618 , H01L27/14625 , H01L2224/02372 , H01L2224/0392 , H01L2224/0401 , H01L2224/05 , H01L2224/05548 , H01L2224/06181 , H01L2224/13022 , H01L2224/13024 , H01L2224/131 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor package includes a solid-state imaging element, electrode pad, through-hole electrode, and light-transmitting substrate. The solid-state imaging element is formed on the first main surface of a semiconductor substrate. The electrode pad is formed on the first main surface of the semiconductor substrate. The through-hole electrode is formed to extend through the semiconductor substrate between the first main surface and a second main surface opposite to the electrode pad formed on the first main surface. The light-transmitting substrate is placed on a patterned adhesive to form a hollow on the solid-state imaging element. The thickness of the semiconductor substrate below the hollow when viewed from the light-transmitting substrate is larger than that of the semiconductor substrate below the adhesive.
摘要翻译：半导体封装包括固态成像元件，电极焊盘，通孔电极和透光衬底。固态成像元件形成在半导体衬底的第一主表面上。电极焊盘形成在半导体衬底的第一主表面上。通孔电极形成为在第一主表面和与形成在第一主表面上的电极焊盘相对的第二主表面之间延伸穿过半导体衬底。将透光基板放置在图案化的粘合剂上以在固态成像元件上形成中空。从透光性基板观察时，半导体衬底在中空部下方的厚度大于粘合剂下方的半导体衬底的厚度。

9. 发明申请

WO2005122238A1 半導体集積回路装置の製造方法审中-公开
标题翻译：制造半导体集成电路器件的工艺
公开(公告)号：WO2005122238A1
公开(公告)日：2005-12-22
申请号：PCT/JP2004/008414
申请日：2004-06-09
申请人：株式会社ルネサステクノロジ , 神田信 , 渡辺孝司 , 廣田大介
发明人：神田信 , 渡辺孝司 , 廣田大介
IPC分类号： H01L21/66
CPC分类号： G01R31/2894 , H01L22/20 , H01L24/05 , H01L24/06 , H01L24/13 , H01L2224/0231 , H01L2224/0392 , H01L2224/0401 , H01L2224/05085 , H01L2224/05553 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01057 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/12036 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15788 , H01L2924/00
摘要：　薄膜プローブを備えたプローブカードを用いて行うプローブ検査時において、薄膜プローブの破損を防ぐために、外観検査装置５１により検査対象であるウエハの主面の外観を検査し、ウエハの主面への異物の付着およびウエハの主面のバンプ電極の形状の異常などの外観不良の結果をウエハの面内における各チップの配列通りにウエハマップデータとしてまとめた後に、このウエハマップデータをサーバー５２を介してプローブ検査装置５３に送信し、プローブ検査装置５３はウエハマップデータをもとに外観不良が検出されたチップに対してのプローブ検査を省略しつつ、外観不良が検出されなかった他のチップに対してプローブ検査を実施する。
摘要翻译：当使用配备有薄膜探针的探针卡进行探针标记检查时，目视检查系统（51）目视检查检查对象（即，晶片）的主表面的外观，收集检查结果，例如粘附在晶片的主表面上的晶片的主表面上的尘埃颗粒或凸起电极的异常形状，作为晶片平面中各芯片的排列顺序的晶片映射数据。晶片地图数据通过服务器（52）发送到探针检查系统（53），对于没有根据晶片图数据进行目视检查的芯片，省略了检测标记检查，并且进行探针标记检查通过目视检查的其他芯片。

10. 发明申请

WO2003079437A2 SEMICONDUCTOR DEVICE HAVING A BOND PAD AND METHOD THEREFOR 审中-公开
标题翻译：具有BOND PAD的半导体器件及其方法
公开(公告)号：WO2003079437A2
公开(公告)日：2003-09-25
申请号：PCT/US2003/007782
申请日：2003-03-12
申请人： MOTOROLA, INC.
发明人： YONG, Lois, E. , HARPER, Peter, R. , TRAN, Tu Anh, , METZ, Jeffrey, W. , LEAL, George, R. , DINH, Dieu, Van
IPC分类号： H01L23/485
CPC分类号： H01L24/05 , H01L22/32 , H01L24/03 , H01L2224/02166 , H01L2224/0392 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05187 , H01L2224/05553 , H01L2224/05624 , H01L2224/48145 , H01L2225/06506 , H01L2225/0651 , H01L2225/06596 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A bond pad (10) has a probe region (14) and a wire bond region (12) that are substantially non-overlapping. In one embodiment, the bond pad (10) is connected to a final metal layer pad (16) and extends over an interconnect region (24). The bond pad (10) is formed from aluminum and the final metal layer pad (16) is formed from copper. Separating the probe region (14) from the wire bond region (12) prevents the final metal layer pad (16) from being damaged by probe testing, allowing for more reliable wire bonds. In another embodiment, the probe region (14) extends over a passivation layer (18). In an application requiring very fine pitch between bond pads, the probe regions (14) and wire bond regions (12) of a plurality of bond pads formed in a line may be staggered to increase the distance between the probe regions (14). In addition, forming the bond pads (10) over the interconnect region (24) reduces the size of the integrated circuit.
摘要翻译：接合焊盘（10）具有基本上不重叠的探针区域（14）和引线接合区域（12）。在一个实施例中，接合焊盘（10）连接到最终金属层焊盘（16）并在互连区域（24）上延伸。接合焊盘（10）由铝形成，并且最终的金属层焊盘（16）由铜形成。将探针区域（14）与引线接合区域（12）分开可防止最终金属层焊盘（16）被探针测试损坏，从而允许更可靠的引线接合。在另一个实施例中，探针区域（14）在钝化层（18）上延伸。在需要接合焊盘之间非常细间距的应用中，形成在一条线上的多个接合焊盘的探针区域（14）和引线键合区域（12）可以交错以增加探针区域（14）之间的距离。此外，在互连区域（24）上形成接合焊盘（10）减小了集成电路的尺寸。

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