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1. 发明申请

WO2015015982A1 封止用シート、及び、当該封止用シートを用いた半導体装置の製造方法审中-公开
标题翻译：用于密封的表格和使用用于密封的表格制造半导体器件的方法
公开(公告)号：WO2015015982A1
公开(公告)日：2015-02-05
申请号：PCT/JP2014/067396
申请日：2014-06-30
申请人：日東電工株式会社
发明人：飯野　智絵 , 松村　健 , 志賀　豪士 , 盛田　浩介
IPC分类号： H01L23/29 , H01L21/56 , H01L23/00 , H01L23/31
CPC分类号： H01L23/544 , H01L21/561 , H01L23/295 , H01L23/3128 , H01L24/02 , H01L24/11 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2223/54426 , H01L2223/54433 , H01L2223/54486 , H01L2224/02311 , H01L2224/02313 , H01L2224/0401 , H01L2224/16146 , H01L2224/17181 , H01L2224/2919 , H01L2224/32145 , H01L2224/73104 , H01L2224/73204 , H01L2224/81191 , H01L2224/83191 , H01L2224/92 , H01L2224/9202 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2225/06568 , H01L2225/06582 , H01L2225/06593 , H01L2924/181 , H01L2924/18161 , H01L2224/81 , H01L2924/00 , H01L2224/0231 , H01L2224/11 , H01L2224/83 , H01L21/56 , H01L2223/544 , H01L21/304 , H01L21/78 , H01L2924/00014
摘要：　電子デバイスの封止に使用する熱硬化性の封止用シートであって、一方の面の表面粗さ（Ｒａ）が、硬化前において、３μｍ以下である封止用シート。
摘要翻译：一种密封用热固性片材，用于密封电子设备。用于密封的该片的一个表面在固化前的表面粗糙度（Ra）为3μm以下。

2. 发明申请

WO2010145712A1 CRACK REDUCTION AT METAL/ORGANIC DIELECTRIC INTERFACE 审中-公开
标题翻译：金属/有机电介质界面减少裂纹
公开(公告)号：WO2010145712A1
公开(公告)日：2010-12-23
申请号：PCT/EP2009/057678
申请日：2009-06-19
申请人： IMEC , NEC CORPORATION , GONZALEZ, Mario , IKER, François , FUNAYA, Takuo
发明人： GONZALEZ, Mario , IKER, François , FUNAYA, Takuo
IPC分类号： H01L23/532 , H01L21/60 , H01L21/768
CPC分类号： H01L23/5329 , H01L21/76829 , H01L21/76885 , H01L23/3171 , H01L23/3192 , H01L23/53295 , H01L24/03 , H01L24/05 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/02319 , H01L2224/02321 , H01L2224/02331 , H01L2224/02333 , H01L2224/02381 , H01L2224/0239 , H01L2224/024 , H01L2224/03462 , H01L2224/03616 , H01L2224/05024 , H01L2224/05073 , H01L2224/05548 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01049 , H01L2924/01075 , H01L2924/01082 , H01L2924/10253 , H01L2924/10329 , H01L2924/30105 , Y10T29/49117 , Y10T428/24942 , H01L2924/01022 , H01L2924/00
摘要： A method for providing a metal interconnect (181) to second structures (91) embedded in organic dielectric material (110) comprises: obtaining a first structure with second structures, e.g. metal pillars (91), embedded in organic dielectric material (110), and at least at some locations of the first structure providing a stiffening layer (130) on top of the organic dielectric material (110), the stiffening layer (130) having a stiffness higher than the stiffness of the organic dielectric material (110). The method provides an interconnect structure free from cracks at the interface between the second structures (91) and the organic dielectric material (110).
摘要翻译：用于向嵌入在有机介电材料（110）中的第二结构（91）提供金属互连（181）的方法包括：获得具有第二结构的第一结构，金属柱（91），嵌入有机电介质材料（110）中，并且至少在第一结构的某些位置处，在有机电介质材料（110）的顶部上提供加强层（130），加强层（130）具有刚度高于有机介电材料（110）的刚度。该方法提供了在第二结构（91）和有机介电材料（110）之间的界面处没有裂纹的互连结构。

4. 发明申请

WO98052224A1 LITHOGRAPHICALLY DEFINED MICROELECTRONIC CONTACT STRUCTURES 审中-公开
标题翻译：光刻定位微电触点结构
公开(公告)号：WO98052224A1
公开(公告)日：1998-11-19
申请号：PCT/US1998/009999
申请日：1998-05-14
IPC分类号： H01L23/12 , H01L21/20 , H01L21/3205 , H01L21/48 , H01L21/60 , H01L23/48 , H01L23/498 , H01L23/52 , H01L23/522 , H01R4/48 , H01R12/16 , H01R13/24 , H05K3/40
CPC分类号： H01L21/4853 , H01L23/49811 , H01L23/522 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/72 , H01L24/81 , H01L24/94 , H01L2224/02311 , H01L2224/02313 , H01L2224/0239 , H01L2224/036 , H01L2224/03912 , H01L2224/0401 , H01L2224/05166 , H01L2224/05644 , H01L2224/05666 , H01L2224/11003 , H01L2224/11005 , H01L2224/11334 , H01L2224/11426 , H01L2224/1143 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/11472 , H01L2224/11474 , H01L2224/11823 , H01L2224/119 , H01L2224/13012 , H01L2224/13015 , H01L2224/13016 , H01L2224/13017 , H01L2224/13018 , H01L2224/13019 , H01L2224/13024 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/1316 , H01L2224/13163 , H01L2224/13164 , H01L2224/13166 , H01L2224/13169 , H01L2224/13173 , H01L2224/13176 , H01L2224/13178 , H01L2224/1318 , H01L2224/13184 , H01L2224/13562 , H01L2224/13644 , H01L2224/145 , H01L2224/16145 , H01L2224/16227 , H01L2224/81801 , H01L2224/94 , H01L2924/381 , H05K3/4092 , H01L2924/00012 , H01L2224/11 , H01L2924/014 , H01L2924/00014 , H01L2924/01074 , H01L2924/01027 , H01L2924/01028 , H01L2924/01082 , H01L2924/01108 , H01L2924/01104 , H01L2924/01022 , H01L2924/01079 , H01L2224/034 , H01L2224/1147 , H01L2224/0231 , H01L2224/114
摘要： Microelectronic contact structures (260, 360, 460) are lithographically defined and fabricated by applying a masking layer (220, 320, 420) on a surface of a substrate (202, 302, 402) such as an electronic component, creating an opening (222, 322, 422) in the masking layer, depositing a conductive trace of a seed layer (250, 350, 450) onto the masking layer and into the openings, and building up a mass of conductive material on the conductive trace. The sidewalls of the opening can be sloped (tapered). The conductive trace can be patterned by depositing material through a stencil or shadow mask (240, 340, 440). A protruding feature (230, 430) may be disposed on the masking layer so that a tip end (264, 364, 464) of the contact structure acquires a topography. All of these elements can be constructed as a group to form a plurality of precisely positioned resilient contact structures.
摘要翻译：微电子接触结构（260,360,460）通过在诸如电子部件的基板（202,302,402）的表面上施加掩模层（220,320,420）而光刻地限定和制造，从而产生开口 222,322,422），在所述掩蔽层上沉积种子层（250,350,450）的导电迹线并且进入所述开口中，以及在所述导电迹线上建立大量导电材料。开口的侧壁可以是倾斜的（渐缩的）。导电迹线可以通过沉积材料通过模板或荫罩（240,340,440）进行图案化。可以在掩蔽层上设置突出特征（230,430），使得接触结构的末端（264,364,464）获取形貌。所有这些元件可以被构造成一组以形成多个精确定位的弹性接触结构。

5. 发明申请

WO2011155638A1 METHOD OF REDISTRIBUTING FUNCTIONAL ELEMENT 审中-公开
标题翻译：重新配置功能元件的方法
公开(公告)号：WO2011155638A1
公开(公告)日：2011-12-15
申请号：PCT/JP2011/063856
申请日：2011-06-10
申请人： NEC Corporation , IMEC , FUNAYA, Takuo , IKER, Francois , BEYNE, Eric
发明人： FUNAYA, Takuo , IKER, Francois , BEYNE, Eric
IPC分类号： H01L23/12 , H01L21/3205 , H01L23/52
CPC分类号： H01L21/486 , H01L21/76802 , H01L21/76819 , H01L23/522 , H01L23/525 , H01L23/5389 , H01L24/02 , H01L24/05 , H01L24/13 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/82 , H01L24/83 , H01L24/92 , H01L2224/02311 , H01L2224/02313 , H01L2224/02317 , H01L2224/02321 , H01L2224/02331 , H01L2224/0239 , H01L2224/024 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/12105 , H01L2224/21 , H01L2224/211 , H01L2224/215 , H01L2224/24011 , H01L2224/24105 , H01L2224/24226 , H01L2224/24227 , H01L2224/24246 , H01L2224/245 , H01L2224/27318 , H01L2224/2732 , H01L2224/27416 , H01L2224/27436 , H01L2224/291 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/29339 , H01L2224/32147 , H01L2224/32227 , H01L2224/73253 , H01L2224/73267 , H01L2224/821 , H01L2224/82101 , H01L2224/82104 , H01L2224/82106 , H01L2224/8385 , H01L2224/83851 , H01L2224/92244 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/014 , H01L2924/09701 , H01L2924/10329 , H01L2924/12042 , H01L2924/1461 , H01L2924/00014 , H01L2224/81 , H01L2924/3512 , H01L2924/00
摘要： According to a method of redistributing a functional element of the present invention, an insulating resin layer is supplied onto a functional element wafer such as an LSI. A portion to be a via hole on an electrode pad of the functional element is filled with a sacrificial layer. The top of the sacrificial layer filled in the via hole is exposed from the insulating layer by grinding or polishing. Therefore, it is possible to prevent breakage of a brittle material such as a low-k material in the functional element, which would be caused by transmission of shearing stress when a conventional pillar or a conventional gold projecting electrode is used. The reliability, the yield, and the level of flatness can be improved by forming an interconnection conductive layer after the flattening process of grinding or polishing. Accordingly, a fine conductive interconnection can be formed.
摘要翻译：根据本发明的功能元件的再分配方法，绝缘树脂层被供给到诸如LSI的功能元件晶片上。在功能元件的电极焊盘上作为通孔的部分填充有牺牲层。填充在通孔中的牺牲层的顶部通过研磨或抛光从绝缘层暴露出来。因此，可以防止当使用传统的支柱或常规的金突出电极时由于剪切应力的传递而引起的功能元件中诸如低k材料的脆性材料的破损。通过在研磨或抛光的平坦化处理之后形成互连导电层，可以提高可靠性，产量和平坦度。因此，可以形成精细的导电互连。

6. 发明申请

WO2011074589A1 エッチング液及びこれを用いた半導体装置の製造方法审中-公开
标题翻译：用于制造使用其的半导体器件的蚀刻和方法
公开(公告)号：WO2011074589A1
公开(公告)日：2011-06-23
申请号：PCT/JP2010/072506
申请日：2010-12-14
申请人：三菱瓦斯化学株式会社 , 細見彰良 , 大前健祐
发明人：細見　彰良 , 大前　健祐
IPC分类号： H01L21/308 , C23F1/18 , H01L21/306 , H01L21/3205 , H01L21/3213 , H01L23/52
CPC分类号： H01L21/32134 , C23F1/02 , C23F1/18 , C23F1/44 , H01L23/3114 , H01L23/525 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02311 , H01L2224/02313 , H01L2224/02331 , H01L2224/0239 , H01L2224/03462 , H01L2224/0347 , H01L2224/0361 , H01L2224/03614 , H01L2224/03912 , H01L2224/03914 , H01L2224/03916 , H01L2224/0401 , H01L2224/05008 , H01L2224/05027 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05548 , H01L2224/05572 , H01L2224/05647 , H01L2224/11334 , H01L2224/11462 , H01L2224/1147 , H01L2224/1191 , H01L2224/11912 , H01L2224/13007 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/01022 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552
摘要：　電極を有する半導体基板の再配線に用いられ、ニッケルをエッチングせずに銅を選択的にエッチングできるエッチング液及びこれを用いた半導体装置の製造方法を提供する。　過酸化水素とクエン酸とを含み、過酸化水素の含有量が０．７５～１２質量％、クエン酸の含有量が１～２０質量％、かつ過酸化水素とクエン酸とのモル比が０．３～５の範囲内である半導体基板の再配線に用いられるエッチング液、過酸化水素とリンゴ酸とを含み、過酸化水素の含有量が０．７５～１２質量％、リンゴ酸の含有量が１．５～２５質量％、かつ過酸化水素とリンゴ酸とのモル比が０．２～６の範囲内である半導体基板の再配線に用いられる、銅の選択的エッチング用エッチング液、及びこれらのエッチング液を用いた半導体装置の製造方法である。
摘要翻译：公开了：用于重新布线具有电极的半导体衬底的蚀刻剂，并且能够在不蚀刻镍的情况下选择性地蚀刻铜; 以及使用蚀刻剂制造半导体器件的方法。具体公开的是：用于重新布线半导体衬底并含有过氧化氢和柠檬酸的蚀刻剂，其中过氧化氢含量为0.75-12质量％，柠檬酸含量为1-20质量％，过氧化氢与柠檬酸的摩尔比在0.3-5的范围内; 用于铜的选择性蚀刻的蚀刻剂，其用于半导体衬底的重新布线并含有过氧化氢和苹果酸，并且其中过氧化氢含量为0.75-12质量％，苹果酸含量为1.5〜25质量％过氧化氢与苹果酸的摩尔比在0.2-6的范围内; 以及使用该蚀刻剂制造半导体器件的方法。

7. 发明申请

WO2010069077A1 FACE-TO-FACE (F2F) HYBRID STRUCTURE FOR AN INTEGRATED CIRCUIT 审中-公开
标题翻译：用于集成电路的面对面（F2F）混合结构
公开(公告)号：WO2010069077A1
公开(公告)日：2010-06-24
申请号：PCT/CA2009/001861
申请日：2009-12-18
申请人： ATI TECHNOLOGIES ULC , MARTINEZ, Liane , TOPACIO, Roden, R. , LOW, Yip, Seng
发明人： MARTINEZ, Liane , TOPACIO, Roden, R. , LOW, Yip, Seng
IPC分类号： H01L21/77 , H01L21/60 , H01L21/98 , H01L23/485 , H01L23/488 , H01L23/50
CPC分类号： G06F17/5068 , H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L23/525 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L2224/02313 , H01L2224/02331 , H01L2224/0239 , H01L2224/0333 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05644 , H01L2224/05647 , H01L2224/1134 , H01L2224/11462 , H01L2224/13024 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/14135 , H01L2224/14136 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48599 , H01L2224/48624 , H01L2224/48639 , H01L2224/48644 , H01L2224/48647 , H01L2224/73207 , H01L2224/81121 , H01L2224/81191 , H01L2224/81193 , H01L2224/81815 , H01L2224/85181 , H01L2224/85424 , H01L2224/85439 , H01L2224/92127 , H01L2224/92163 , H01L2224/94 , H01L2225/0651 , H01L2225/06513 , H01L2225/06527 , H01L2225/06568 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/00014 , H01L2924/01024 , H01L2224/11 , H01L2224/131 , H01L2924/00013 , H01L2924/00 , H01L2924/00012
摘要： An integrated circuit (IC) product includes a redistribution layer (RDL) having at least one conductive layer configured to distribute electrical information from one location to another location in the IC. The RDL also includes a plurality of wire bond pads and a plurality of solder pads. The plurality of solder pads each includes a solder wettable material that is in direct electrical communication with the RDL.
摘要翻译：集成电路（IC）产品包括具有至少一个导电层的再分配层（RDL），该导电层被配置为将电信息从一个位置分配到IC中的另一个位置。 RDL还包括多个引线接合焊盘和多个焊盘。多个焊盘各自包括与RDL直接电连通的焊料可润湿材料。

8. 发明申请

WO2010059118A1 FUNCTIONAL CAPPING 审中-公开
标题翻译：功能开机
公开(公告)号：WO2010059118A1
公开(公告)日：2010-05-27
申请号：PCT/SE2009/051311
申请日：2009-11-19
申请人： SILEX MICROSYSTEMS AB , EBEFORS, Thorbjörn , KÄLVESTEN, Edvard , BAUER, Thomas
发明人： EBEFORS, Thorbjörn , KÄLVESTEN, Edvard , BAUER, Thomas
IPC分类号： B81C1/00 , B81B7/00 , H01L21/50 , H01L23/48
CPC分类号： H01L21/50 , B81B7/007 , B81B2207/095 , B81C1/00301 , H01L21/6835 , H01L21/76898 , H01L21/78 , H01L23/04 , H01L23/10 , H01L23/481 , H01L23/49827 , H01L23/49838 , H01L23/552 , H01L23/585 , H01L23/642 , H01L23/645 , H01L23/66 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/33 , H01L24/81 , H01L24/83 , H01L2221/68363 , H01L2221/68372 , H01L2223/6616 , H01L2223/6622 , H01L2223/6655 , H01L2223/6677 , H01L2224/02311 , H01L2224/02313 , H01L2224/02371 , H01L2224/02372 , H01L2224/0239 , H01L2224/03462 , H01L2224/0401 , H01L2224/05073 , H01L2224/05155 , H01L2224/05548 , H01L2224/05573 , H01L2224/05644 , H01L2224/1146 , H01L2224/13009 , H01L2224/13024 , H01L2224/13083 , H01L2224/131 , H01L2224/13111 , H01L2224/13144 , H01L2224/13155 , H01L2224/29009 , H01L2224/29011 , H01L2224/29012 , H01L2224/29018 , H01L2224/29101 , H01L2224/29111 , H01L2224/29144 , H01L2224/30051 , H01L2224/3012 , H01L2224/81005 , H01L2224/81203 , H01L2224/81801 , H01L2224/83005 , H01L2224/83203 , H01L2224/83801 , H01L2224/83805 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01051 , H01L2924/01072 , H01L2924/01079 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/1461 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/01027 , H01L2924/01028 , H01L2924/3512
摘要： A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer. Finally the wafer is singulated to individual devices.
摘要翻译：一种制造微电子和/或微机械装置的晶片级方法，其具有通过连接（通孔）的电晶片的封盖，包括以下步骤：提供具有第一和第二侧的半导体材料的第一晶片，以及第一侧中的多个孔和/或凹部，以及在第二侧上延伸到晶片上方的阻挡结构，所述屏障包括绝缘材料（例如氧化物）和另一材料的外层的内层。然后，将金属施加在所述孔中，以覆盖孔中的壁和孔的底部。去除阻挡结构，并且通过晶片背面上的连接将接触提供给晶片。粘合结构设置在晶片的所述第一侧或第二侧中的任一个上。晶片接合到承载电子和微电子/机械部件的另一个晶片，使得第一晶片形成覆盖第二晶片的封盖结构。最后，将晶片单个化为单个器件。

9. 发明申请

WO2009122912A1 はんだ構造体、はんだ構造体の形成方法、はんだ構造体を含む半導体モジュール、および携帯機器审中-公开
标题翻译：焊接结构，形成焊接结构的方法，包括焊接结构的半导体模块和便携式设备
公开(公告)号：WO2009122912A1
公开(公告)日：2009-10-08
申请号：PCT/JP2009/055318
申请日：2009-03-18
申请人：三洋電機株式会社 , 水原秀樹 , 小林初 , 清水敏哉
发明人：水原秀樹 , 小林初 , 清水敏哉
IPC分类号： H01L21/60 , B23K1/00 , B23K31/02 , B23K35/26 , C22C13/00 , C22C13/02 , C22C28/00 , B23K101/40
CPC分类号： B23K1/0016 , B23K31/02 , B23K35/262 , B23K35/3013 , B23K2201/42 , B32B15/018 , C22C13/00 , C22C13/02 , H01L23/544 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2224/02313 , H01L2224/02319 , H01L2224/0233 , H01L2224/0239 , H01L2224/0401 , H01L2224/1132 , H01L2224/13099 , H01L2224/131 , H01L2224/16 , H01L2924/0001 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01051 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H05K3/3463 , H05K2203/0435 , H01L2924/00
摘要：本発明は、Ｓｎ合金はんだにおいてＳｎのウイスカーの発生を抑制するはんだ構造体及びその形成方法に関する。はんだ構造体（２）は、固液共存状態になりうるＳｎ合金（４）とＳｎ合金（４）の表面の少なくとも一部を覆うＡｕ（またはＡｕ合金）被膜（６）とで構成されている。Ａｕ被膜（６）がＳｎ合金（４）の表面の少なくとも一部を覆う被膜となっている。望ましい形態として、Ａｕ被膜（６）はＳｎ合金（４）の表面に網目構造を形成している。Ａｕ被膜（６）の厚さは、たとえば、１～５μｍである。
摘要翻译：公开了抑制Sn合金焊料中Sn晶须的形成的焊料结构。还公开了一种形成焊料结构的方法。焊料结构（2）由可以处于固液共存状态的Sn合金（4）和覆盖Sn的表面的至少一部分的Au（或Au合金）涂膜（6）构成，合金（4）。也就是说，Au涂膜（6）是覆盖Sn合金（4）表面的至少一部分的膜。优选地，Au涂膜（6）在Sn合金（4）的表面上形成网状结构。 Au涂膜（6）具有例如1-5μm的厚度。

10. 发明申请

WO2014020479A3 POST-CMOS PROCESSING AND 3D INTEGRATION BASED ON DRY-FILM LITHOGRAPHY 审中-公开
标题翻译：基于干膜光刻的后CMOS处理和3D集成
公开(公告)号：WO2014020479A3
公开(公告)日：2014-04-10
申请号：PCT/IB2013055946
申请日：2013-07-19
申请人： ECOLE POLYTECH
发明人： GUIDUCCI CARLOTTA , LEBLEBICI YUSUF , TEMIZ YÜKSEL
IPC分类号： H01L21/60 , H01L21/683 , H01L21/768 , H01L21/98 , H01L23/31 , H01L23/48 , H01L25/065
CPC分类号： H01L25/50 , G03F7/2022 , G03F7/32 , H01L21/568 , H01L21/6835 , H01L21/76898 , H01L23/3185 , H01L24/02 , H01L24/05 , H01L24/24 , H01L24/27 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L2221/68381 , H01L2224/02313 , H01L2224/0239 , H01L2224/05166 , H01L2224/05624 , H01L2224/24011 , H01L2224/24051 , H01L2224/24146 , H01L2224/27002 , H01L2224/32145 , H01L2224/73267 , H01L2224/82002 , H01L2224/82005 , H01L2224/8201 , H01L2224/82101 , H01L2224/82106 , H01L2224/82143 , H01L2224/83143 , H01L2224/83203 , H01L2224/8385 , H01L2224/9202 , H01L2224/92244 , H01L2224/94 , H01L2225/06541 , H01L2225/06544 , H01L2225/06565 , H01L2924/01322 , H01L2924/10253 , H01L2924/1461 , H01L2924/00014 , H01L2924/01013 , H01L2924/00013 , H01L2224/83 , H01L2224/82 , H01L2924/00
摘要： A method for performing a post processing patterning on a diced chip having a footprint, comprises the steps of: - providing a support wafer; - applying a first dry film photoresist to the support wafer; - positioning a mask corresponding to the footprint of the diced chip on the first dry film photoresist; - exposing the mask and the first dry film photoresist to UV radiation; - removing the mask; - developing the exposed first dry film photoresist to obtain a cavity corresponding to the diced chip; - positioning the diced chip inside the cavity; - applying a second dry film photoresist to the first film photoresist and the diced chip; - exposing and developing the second dry film photoresist applied to the diced chip in accordance with the post processing pattern; and - performing an anisotropic dry etching of the chip to form a via therein. Furthermore, a method for obtaining a stack of two semiconductor chips or wafers in a back to face configuration, whereby at least one of the semiconductor chips or wafers comprises a through silicon via (TSV), comprises the steps of: - providing a first semiconductor chip or wafer; - providing a second semiconductor chip or wafer; - making a hole through the second semiconductor chip or wafer from a face side to a back side; - applying the face side of second semiconductor chip or wafer on a release tape; - depositing parylene on the assembly of the second semiconductor chip or wafer and the release tape, thereby obtaining a sidewall passivation in the hole and a bonding layer on the back side of the second semiconductor chip or wafer; - releasing the release tape, thereby obtaining a membrane of parylene covering an opening of the hole on the front side; - positioning the back side of the second semiconductor chip or wafer relative to a face side of the first semiconductor chip or wafer; - bonding the second semiconductor chip or wafer to the first semiconductor chip or wafer by applying pressure and heat; - removing the membrane of parylene by directional etching; and - electrically connecting the face side of the second semiconductor chip or wafer to the face side of the first semiconductor chip or wafer by depositing a conductor inside the hole, thereby obtaining the TSV.
摘要翻译：一种用于在具有占地面积的切割芯片上执行后处理图案化的方法包括以下步骤： - 提供支撑晶片; - 将第一干膜光致抗蚀剂施加到所述支撑晶片; - 将对应于切割芯片的覆盖区的掩模定位在第一干膜光致抗蚀剂上; - 将所述掩模和所述第一干膜光致抗蚀剂暴露于UV辐射; - 去除面膜; - 将暴露的第一干膜光致抗蚀剂显影以获得对应于切割芯片的腔; - 将切割的芯片定位在腔内; - 将第二干膜光致抗蚀剂施加到第一膜光致抗蚀剂和切割的芯片上; - 根据后处理图案曝光和显影施加到切割的芯片上的第二干膜光致抗蚀剂; 以及 - 对所述芯片进行各向异性干蚀刻以在其中形成通孔。此外，一种用于以背对面配置获得两个半导体芯片或晶片的堆叠的方法，由此半导体芯片或晶片中的至少一个包括贯穿硅通孔（TSV），包括以下步骤： - 提供第一半导体芯片或晶片; - 提供第二半导体芯片或晶片; - 从第二半导体芯片或晶片从正面到背面形成一个孔; - 将第二半导体芯片或晶片的表面施加在释放带上; - 将聚对二甲苯沉积在第二半导体芯片或晶片和释放带的组件上，从而在孔中获得侧壁钝化和在第二半导体芯片或晶片的背面上的结合层; - 释放释放带，从而获得覆盖前侧的孔的开口的聚对二甲苯膜; - 相对于所述第一半导体芯片或晶片的正面侧定位所述第二半导体芯片或晶片的背面; - 通过施加压力和热量将所述第二半导体芯片或晶片接合到所述第一半导体芯片或晶片; - 通过定向蚀刻去除聚对二甲苯膜; 以及 - 通过在孔内沉积导体，将第二半导体芯片或晶片的表面侧电连接到第一半导体芯片或晶片的正面，从而获得TSV。

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