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1. 发明申请

WO2012122388A2 CHIP-LAST EMBEDDED INTERCONNECT STRUCTURES AND METHODS OF MAKING THE SAME 审中-公开
标题翻译：嵌入式嵌入式互连结构及其制备方法
公开(公告)号：WO2012122388A2
公开(公告)日：2012-09-13
申请号：PCT/US2012028300
申请日：2012-03-08
申请人： GEORGIA TECH RES INST , LIU FUHAN , KUMBHAT NITESH , SUNDARAM VENKATESH , TUMMALA RAO
发明人： LIU FUHAN , KUMBHAT NITESH , SUNDARAM VENKATESH , TUMMALA RAO
IPC分类号： A61K31/5377 , A61P3/00 , A61P5/00 , A61P9/00 , A61P11/06 , A61P19/00 , A61P25/00 , A61P25/28 , A61P29/00 , A61P35/00 , A61P37/00 , A61P37/08 , C07D413/14 , C12N9/96 , C12N9/99 , C12Q1/48
CPC分类号： H01L23/49827 , H01L23/13 , H01L23/49833 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16227 , H01L2224/73253 , H01L2225/06517 , H01L2225/06572 , H01L2225/1029 , H01L2225/1052 , H01L2225/1058 , H01L2924/00014 , H01L2924/15153 , H01L2924/15311 , H01L2224/05599
摘要： CHIP-LAST EMBEDDED INTERCONNECT STRUCTURES AND METHODS OF MAKING THE SAME ABSTRACT The various embodiments of the present invention provide a novel chip-last embedded structure, wherein an IC is embedded within a one to two metal layer substrate. The various embodiments of the present invention are comparable to other two-dimensional and three-dimensional WLFO packages of the prior art as the embodiments have similar package thicknesses and X-Y form factors, short interconnect lengths, fine-pitch interconnects to chip I/Os, a reduced layer count for re-distribution of chip I/O pads to ball grid arrays (BGA) or land grid arrays (LGA), and improved thermal management options.
摘要翻译：嵌入式嵌入式互连结构及其制造方法摘要本发明的各种实施例提供了一种新颖的芯片最后嵌入式结构，其中将IC嵌入在一至两个金属层基板内。本发明的各种实施例与现有技术的其它二维和三维WLFO封装相当，因为实施例具有类似的封装厚度和XY形状因子，短互连长度，到芯片I / O的精细间距互连，用于将芯片I / O焊盘重新分配到球栅阵列（BGA）或焊盘网格阵列（LGA）的减少的层数，以及改进的热管理选项。

2. 发明申请

WO2010033322A2 STACKING QUAD PRE-MOLDED COMPONENT PACKAGES, SYSTEMS USING THE SAME, AND METHODS OF MAKING THE SAME 审中-公开
标题翻译：堆叠的四层预成型组件包，使用该组件的系统及其制造方法
公开(公告)号：WO2010033322A2
公开(公告)日：2010-03-25
申请号：PCT/US2009053597
申请日：2009-08-12
申请人： FAIRCHILD SEMICONDUCTOR , LIU YONG , ALLEN HOWARD , QIAN QIUXIAO
发明人： LIU YONG , ALLEN HOWARD , QIAN QIUXIAO
IPC分类号： H01L23/12 , H01L23/495
CPC分类号： H01L23/4951 , H01L23/3107 , H01L23/49572 , H01L23/49861 , H01L25/105 , H01L2224/05573 , H01L2224/13025 , H01L2224/16 , H01L2225/1029 , H01L2225/1041 , H01L2924/00014 , H01L2924/13091 , H01L2924/19105 , H01L2224/05599
摘要： Pre-molded component packages that may be as thin as a leadframe for a semiconductor die, systems using the same, and methods of making the same are disclosed. The leads of an exemplary package are exposed at both surfaces at the leadframe. The packages may be stacked upon one another and electrically coupled at the exposed portions of their leads.
摘要翻译：公开了可以与半导体管芯的引线框一样薄的预成型部件封装，使用其的系统及其制造方法。示例性包装的引线在引线框架的两个表面处露出。封装可以彼此堆叠并且在引线的暴露部分处电耦合。

3. 发明申请

WO2006052616A1 STACKED PACKAGING IMPROVEMENTS 审中-公开
标题翻译：堆叠包装改进
公开(公告)号：WO2006052616A1
公开(公告)日：2006-05-18
申请号：PCT/US2005/039716
申请日：2005-11-03
申请人： TESSERA, INC. , HABA, Belgacem , MITCHELL, Craig, S. , BEROZ, Masud
发明人： HABA, Belgacem , MITCHELL, Craig, S. , BEROZ, Masud
IPC分类号： H01L23/498
CPC分类号： H01L24/81 , H01L21/56 , H01L21/78 , H01L23/49575 , H01L23/49833 , H01L24/48 , H01L24/97 , H01L25/105 , H01L25/18 , H01L25/50 , H01L2224/48091 , H01L2224/48227 , H01L2224/97 , H01L2225/1023 , H01L2225/1029 , H01L2225/1041 , H01L2225/1052 , H01L2225/1058 , H01L2924/00014 , H01L2924/01002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/07811 , H01L2924/15311 , H01L2924/19107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A plurality of microelectronic assemblies (60) are made by severing an in-process unit including an upper substrate (40) and lower substrate (20) with microelectronic elements (36) disposed between the substrates. In a further embodiment, a lead frame (452) is joined to a substrate (440) so that the leads project from this substrate. Lead frame (452) is joined to a further substrate (470) with one or more microelectronic elements (436, 404, 406) disposed between the substrates.
摘要翻译：多个微电子组件（60）通过用设置在基板之间的微电子元件（36）切断包括上基板（40）和下基板（20）的在线单元来制造。在另一个实施例中，引线框架（452）连接到基板（440），使得引线从该基板突出。引线框架（452）与设置在基板之间的一个或多个微电子元件（436,404,406）连接到另一基板（470）。

4. 发明申请

WO2005022591A3 REVERSIBLE LEADLESS PACKAGE AND METHODS OF MAKING AND USING SAME 审中-公开
标题翻译：可逆无铅封装及其制造和使用方法
公开(公告)号：WO2005022591A3
公开(公告)日：2005-10-20
申请号：PCT/US2004026790
申请日：2004-08-18
申请人： ADVANCED INTERCONNECT TECH LTD , ISLAM SHAFIDUL , SAN ANTONIO ROMARICO SANTOS
发明人： ISLAM SHAFIDUL , SAN ANTONIO ROMARICO SANTOS
IPC分类号： H01L20060101 , H01L21/44 , H01L21/48 , H01L23/31 , H01L23/495 , H01L25/10
CPC分类号： H01L21/4832 , H01L21/561 , H01L21/568 , H01L23/3107 , H01L23/3128 , H01L23/49548 , H01L24/45 , H01L24/48 , H01L24/97 , H01L25/105 , H01L2221/68377 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16245 , H01L2224/2919 , H01L2224/32257 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/84439 , H01L2224/92247 , H01L2224/97 , H01L2225/1029 , H01L2225/1058 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2224/85 , H01L2924/0665 , H01L2224/83 , H01L2224/81 , H01L2924/00012 , H01L2224/05599 , H01L2224/45015 , H01L2924/207 , H01L2224/37099
摘要： A semiconductor device package includes an electrically conductive lead frame having a plurality of posts disposed at a perimeter of the package. Each of the posts has a first contact surface disposed at the first package face and a second contact surface disposed at the second package face. The lead frame also includes a plurality of post extensions disposed at the second package face. Each of the post extensions includes a bond site formed on a surface of the post extension opposite the second package face. At least one I/O pads on the semiconductor device is electrically connected to the post extension at the bond site using wirebonding, tape automated bonding, or flip-chip methods. The package can be assembled use a lead frame having pre-formed leads, with or without taping, or it can employ the use of partially etched lead frames. A stack of the semiconductor device packages may be formed.
摘要翻译：一种半导体器件封装包括导电引线框架，该导电引线框架具有设置在封装周边的多个柱。每个柱具有设置在第一包装面处的第一接触表面和设置在第二包装面处的第二接触表面。引线框架还包括设置在第二包装面处的多个支柱延伸部。每个柱延伸部包括形成在柱延伸部的与第二包装面相对的表面上的结合部位。半导体器件上的至少一个I / O焊盘使用引线键合，带式自动键合或倒装芯片方法在键合位置处电连接到柱延伸部分。封装可以使用具有预成型引线的引线框架进行组装，有或没有胶带，或者可以使用部分蚀刻的引线框架。可以形成半导体器件封装的堆叠。

5. 发明申请

WO2005001927A2 STACKABLE INTEGRATED CIRCUIT PACKAGE AND METHOD THEREFOR 审中-公开
标题翻译：可堆叠集成电路封装及其方法
公开(公告)号：WO2005001927A2
公开(公告)日：2005-01-06
申请号：PCT/US2004018019
申请日：2004-06-03
申请人： SANDISK CORP , TAKIAR HEM P
发明人： TAKIAR HEM P
IPC分类号： H01L23/31 , H01L25/065 , H01L25/10 , H05K3/34 , H01L23/00
CPC分类号： H05K3/3426 , H01L23/3128 , H01L23/49575 , H01L24/48 , H01L25/105 , H01L2224/05599 , H01L2224/32145 , H01L2224/32188 , H01L2224/45099 , H01L2224/48091 , H01L2224/48247 , H01L2224/85399 , H01L2225/1029 , H01L2225/1058 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/18165 , H05K2201/10515 , H05K2201/10689 , H05K2201/10931 , H05K2201/2081 , Y02P70/613 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： Improved apparatus and methods for stacking integrated circuit packages having leads are disclosed. According to one embodiment, the leads of an integrated circuit package are exposed and provided with solder balls so that corresponding leads of another integrated circuit package being stacked thereon can be electrically connected. The stacking results in increased integrated circuit density with respect to a substrate, yet the stacked integrated circuit packages are able to still enjoy having an overall thin or low profile.
摘要翻译：公开了用于堆叠具有引线的集成电路封装的改进的装置和方法。根据一个实施例，集成电路封装的引线被暴露并设置有焊球，使得堆叠在其上的另一个集成电路封装的相应引线可以电连接。堆叠导致相对于衬底的集成电路密度增加，但是堆叠的集成电路封装仍然可以享受整体薄或薄的轮廓。

6. 发明申请

WO03058719B1 MONOLITHIC INTERCONNECTION INTERFACE FOR THE STACKING OF ELECTRONIC COMPONENTS AND THE PRODUCTION METHOD THEREOF 审中-公开
标题翻译：用于堆叠电子元件的单片互连接口及其生产方法
公开(公告)号：WO03058719B1
公开(公告)日：2004-05-27
申请号：PCT/FR0204009
申请日：2002-11-22
申请人： NOVATEC SOC , BOURRIERES FRANCIS , KAISER CLEMENT
发明人： BOURRIERES FRANCIS , KAISER CLEMENT
IPC分类号： H01L25/10 , H05K1/00 , H05K1/14 , H05K1/18 , H05K3/34
CPC分类号： H05K1/141 , H01L25/105 , H01L2225/1029 , H01L2225/107 , H01L2924/0002 , H01L2924/1627 , H05K1/0284 , H05K1/144 , H05K1/182 , H05K3/3442 , H05K2201/049 , H05K2201/09036 , H05K2201/10515 , H05K2201/10666 , H05K2201/10689 , H01L2924/00
摘要： The invention relates to an interconnection interface (1) which can be used to create at least one additional interconnection surface level for the production of three-dimensional electronic assemblies. According to the invention, the base boxes (3), which provide the electric interconnection with said interface, are surface assembly components of the type which have gullwing connections that extend out from the boxes called SO, TSOP, QFP, etc. Said interface consists of a one-piece printed circuit comprising at least two faces and having non-through openings and metallised through holes, thereby fulfilling the mechanical separator and electric connection functions simultaneously. The upper face (4) of the interface (1) is flat and forms a receiving and interconnecting circuit and the surface thereof, which is totally free, can be adapted to the size of additional components. The lower face of said interface comprises at least two levels, namely: a first level (5) forming a circuit which is used simultaneously for the electric interconnection and the mechanical bearing on the supports (2) of the base box(es) (3) and the link via metallised holes (6) with the upper face (4); and a second level (7) forming the apex of an opening that is used for the passage of the body/bodies of the base box(es) to be avoided.
摘要翻译：本发明涉及一种互连接口（1），其可用于产生用于生产三维电子组件的至少一个额外的互连表面水平。根据本发明，提供与所述接口的电互连的底盒（3）是具有从称为SO，TSOP，QFP等的盒延伸出的鸥翼连接类型的表面组装部件。所述接口包括包括至少两个面并且具有不通孔和金属化通孔的单件印刷电路，从而同时实现机械分离器和电连接功能。接口（1）的上表面（4）是平坦的，并且形成接收和互连电路，并且其完全没有的表面可以适应于附加部件的尺寸。所述接口的下表面包括至少两个层次，即形成电路的第一层（5），其与电互连同时使用，并且基座盒（3）的支撑件（2）上的机械轴承）和通过金属化孔（6）与上表面（4）的连接; 以及形成用于待避免的底盒的主体/主体的通道的开口的顶点的第二水平面（7）。

7. 发明申请

WO2004008531A1 LEAD FRAME FOR STACKED SEMICONDUCTOR PACKAGES, STACKED SEMICONDUCTOR PACKAGES USING IT, AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：用于堆叠半导体封装的引线框架，使用其的堆叠半导体封装及其制造方法
公开(公告)号：WO2004008531A1
公开(公告)日：2004-01-22
申请号：PCT/KR2002/002439
申请日：2002-12-26
申请人： SUNDUS CO., LTD. , RYOO, Rak-Hyun , KWON, Jung-Hoon
发明人： RYOO, Rak-Hyun , KWON, Jung-Hoon
IPC分类号： H01L23/48
CPC分类号： H01L23/49541 , H01L25/105 , H01L2225/1029 , H01L2225/1064 , H01L2225/107 , H01L2924/0002 , H01L2924/00
摘要： A lead frame for stacked semiconductor package is provided, which comprises a plurality of lead pins having same length, thickness, pitch and arranged to correspond to exterior leads of a semiconductor package, and a frame holding the lead pins, wherein at least one lead pin is integrally formed with an adjacent lead pin to be electrically connected and a part of the end of the lead pin is cut to be shorter that other lead pins. Additionally and/or alternatively, at least one lead pin is electrically connected with a remote lead pin through an additional lead or a lead line.
摘要翻译：提供了一种用于层叠半导体封装的引线框架，其包括具有相同长度，厚度，间距的多个引脚，并且被布置为对应于半导体封装的外部引线和保持引脚的框架，其中至少一个引脚与相邻的引脚一体地形成为电连接，并且引脚的端部的一部分被切割成与其它引脚相比更短。附加地和/或替代地，至少一个引脚与远程引脚通过附加引线或引线电连接。

8. 发明申请

WO2002080309A1 HIGH DENSITY PACKAGING OF ELECTRONIC COMPONENTS 审中-公开
标题翻译：电子元件的高密度包装
公开(公告)号：WO2002080309A1
公开(公告)日：2002-10-10
申请号：PCT/US2002/005594
申请日：2002-02-25
申请人： L-3 COMMUNICATIONS CORPORATION , WATSON, Edwin, George
发明人： WATSON, Edwin, George
IPC分类号： H01R12/28
CPC分类号： H05K7/023 , H01L23/5387 , H01L25/105 , H01L2225/1005 , H01L2225/1029 , H01L2225/107 , H01L2924/0002 , H05K1/14 , H01L2924/00
摘要： Disclosed is an electronics packaging systems, which provides for a high density assembly of groups (2a, 2b, 2c, 2d) of similar solid state part packages. The system provides a novel method which includes the use of interconnect members (5) and crossover members (8) for interconnecting the signal paths, structurally assembling and supporting the parts (2a, 2b, 2c, 2d), and removing heat generated within the components (1). The system approach disclosed typically starts at the level of assembling pre-packaged parts (2a, 2b, 2c, 2d) into modules, and permeates through to the printed circuit board (6, 9) and box levels of assembly. The system is applicable, but not limited to, solid state memory device packaging, which typically consists of many similar parts interconnected in a matrix bus type configuration. The assembly of a building block of numerous memory components allows for the modular construction of large amounts of solid state memory.
摘要翻译：公开了一种电子封装系统，其提供类似固态部件封装的组（2a，2b，2c，2d）的高密度组装。该系统提供了一种新颖的方法，其包括使用互连构件（5）和用于互连信号路径的交叉构件（8），结构地组装和支撑部件（2a，2b，2c，2d），以及去除在组件（1）。所公开的系统方法通常从将预包装部件（2a，2b，2c，2d）组装成模块的级别开始，并且渗透到印刷电路板（6,9）和箱体组装。该系统适用于但不限于固态存储器件封装，其通常由以矩阵总线类型配置互连的许多类似部件组成。许多存储器组件的构建块的组装允许大量固态存储器的模块化构造。

9. 发明申请

WO02033752A2 ELECTRONIC MODULE HAVING CANOPY-TYPE CARRIERS 审中-公开
标题翻译：具有CANOPY型载体的电子模块
公开(公告)号：WO02033752A2
公开(公告)日：2002-04-25
申请号：PCT/US2001/032330
申请日：2001-10-16
IPC分类号： H01L25/18 , H01L25/10 , H01L25/11 , H05K1/02 , H05K1/14 , H05K3/34 , H05K3/36
CPC分类号： H05K1/141 , H01L25/105 , H01L2225/1005 , H01L2225/1029 , H01L2225/107 , H01L2225/1094 , H01L2924/0002 , H05K1/0231 , H05K3/0061 , H05K3/3405 , H05K3/3421 , H05K3/368 , H05K2201/049 , H05K2201/1034 , H05K2201/10515 , H05K2201/10659 , H05K2201/10689 , H05K2201/10734 , H05K2201/10924 , H01L2924/00
摘要： An improved multi-chip module includes a main circuit board having and array of electrical interconnection pads to which are mounted a plurality of IC package units. Each IC package unit includes a pair of IC packages, both of which are mounted on opposite sides of the package carrier. The package units may be mounted on one or both sides of the main circuit board. A first primary embodiment of the invention employs a laminar package carrier having a pair of major planar surfaces. Each surface incorporates electrical contact pads. One IC package is surface mounted on each major planar surface, by interconnecting the leads of the package with the contact pads on the planar surface, to form the IC package unit. A number of other vriations exist that provide various other embodiments of the invention including one in which the carrier leads are laminated directly to the leads of an IC package.
摘要翻译：改进的多芯片模块包括主电路板，其具有安装有多个IC封装单元的电互连焊盘阵列。每个IC封装单元包括一对IC封装，两者都安装在封装载体的相对侧上。封装单元可以安装在主电路板的一侧或两侧。本发明的第一个主要实施例采用具有一对主平面的层状包装载体。每个表面都包含电接触垫。通过将封装的引线与平坦表面上的接触焊盘相互连接，将一个IC封装表面安装在每个主平面上，形成IC封装单元。存在提供本发明的各种其它实施例的许多其他的变化，包括其中载体引线直接层压到IC封装的引线的其他实施例。

10. 发明申请

WO01091173A1 STACKABLE FLEX CIRCUIT CHIP PACKAGE AND METHOD OF MAKING SAME 审中-公开
标题翻译：可堆叠电路芯片封装及其制造方法
公开(公告)号：WO01091173A1
公开(公告)日：2001-11-29
申请号：PCT/US2001/010064
申请日：2001-03-29
IPC分类号： H01L23/12 , H01L23/31 , H01L23/498 , H01L25/10 , H01L25/11 , H01L25/18 , H01L21/50 , H01L23/50
CPC分类号： H01L23/3121 , H01L23/3128 , H01L23/498 , H01L23/49805 , H01L23/4985 , H01L25/10 , H01L25/105 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2225/1029 , H01L2225/1041 , H01L2225/1094 , H01L2924/00012
摘要： A stackable integrated circuit chip package (10) comprising a flex circuit (14). The flex circuit itself comprises a flexible substrate having opposed, generally planar top and bottom surfaces, and a conductive pattern (20) which is disposed on the bottom surface. The chip package further comprises a frame (12) which is attached to the substrate of the flex circuit, and an integrated circuit chip which is at least partially circumvented by the frame and electrically connected to the conductive pattern. The substrate is wrapped about and attached to at least a portion of the frame such that the conductive pattern defines first and second portions which are each electrically connectable to another stackable integrated circuit chip package.
摘要翻译：一种包括柔性电路（14）的可堆叠集成电路芯片封装（10）。柔性电路本身包括具有相对的，大致平坦的顶表面和底表面的柔性基底和设置在底表面上的导电图案（20）。芯片封装进一步包括附接到柔性电路的基板的框架（12）以及至少部分地被框架围绕并电连接到导电图案的集成电路芯片。衬底缠绕并附接到框架的至少一部分，使得导电图案限定第一和第二部分，每个部分可电连接到另一个可堆叠集成电路芯片封装。

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