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1. 发明申请

WO2019048137A1 METHOD FOR DETERMINING A CONTROL PARAMETER FOR AN APPARATUS UTILIZED IN A SEMICONDUCTOR MANUFACTURING PROCESS 审中-公开
公开(公告)号：WO2019048137A1
公开(公告)日：2019-03-14
申请号：PCT/EP2018/070605
申请日：2018-07-30
申请人： ASML NETHERLANDS B.V.
发明人： TABERY, Cyrus, Emil , CEKLI, Hakki, Ergun , VAN GORP, Simon, Hendrik, Celine , LIN, Chenxi
IPC分类号： G03F7/20 , H01L21/66
CPC分类号： G03F7/70525 , G03F7/70616 , H01L22/12 , H01L22/20
摘要： Disclosed herein is a method for determining a control parameter for an apparatus utilised in a semiconductor manufacturing process, the method comprising: obtaining performance data associated with a substrate subject to the semiconductor manufacturing process; obtaining die specification data comprising values of an expected yield of one or more dies on the substrate based on the performance data and/or a specification for the performance data; and determining the control parameter in dependence on the performance data and the die specification data. Advantageously, the efficiency and accuracy of processes are improved by only determining how to perform the processes in dependence on dies within specification.

2. 发明申请

WO2018226749A1 METHOD AND SYSTEM FOR DATA COLLECTION AND ANALYSIS FOR SEMICONDUCTOR MANUFACTURING 审中-公开
公开(公告)号：WO2018226749A1
公开(公告)日：2018-12-13
申请号：PCT/US2018/036138
申请日：2018-06-05
申请人： OPTIMAL PLUS LTD. , TEPLINSKY, Shaul
发明人： TEPLINSKY, Shaul , SCHULDENFREI, Michael , SEBBAN, Dan
IPC分类号： G01R31/28 , G01R31/26 , G06F17/18
CPC分类号： G01R31/2601 , G01R31/2837 , G01R31/2894 , G06Q10/06395 , G06Q50/04 , H01L22/00 , H01L22/14 , H01L22/20
摘要： A method includes receiving, from a system manufacturer, system test data for a plurality of electronic systems. Each of the plurality of electronic systems includes a plurality of electronic components. The method also includes determining a relationship between a set of electronic components from the plurality of electronic components and the electronic systems upon which the electronic components of the set of electronic components are assembled and receiving, from a component manufacturer, manufacturing attributes for the set of electronic components. The method further includes selecting a data subset from the system test data corresponding to a subgroup of the set of electronic components. The subgroup includes components from a same fabrication cluster. Additionally, the method includes identifying an outlier relative to the data subset and communicating information about the outlier to at least one of the system manufacturer or the component manufacturer.

3. 发明申请

WO2018075248A1 CONTROL OF A SPECTRAL FEATURE OF A PULSED LIGHT BEAM 审中-公开
标题翻译：脉冲光束的光谱特性控制
公开(公告)号：WO2018075248A1
公开(公告)日：2018-04-26
申请号：PCT/US2017/055182
申请日：2017-10-04
申请人： CYMER, LLC
发明人： CONLEY, Willard Earl , MASON, Eric Anders , THORNES, Joshua Jon
IPC分类号： H01S3/136 , H01S3/11 , H01S3/00 , H01S3/08 , H01S3/106 , H01L21/3065 , H01L21/66 , G03F7/20
CPC分类号： H01S3/136 , G03F7/70041 , G03F7/70141 , G03F7/70191 , G03F7/70575 , G03F7/7085 , H01L21/3065 , H01L22/20 , H01S3/0071 , H01S3/08004 , H01S3/08009 , H01S3/10046 , H01S3/106 , H01S3/11 , H01S3/137 , H01S3/225 , H01S3/2366
摘要： A spectral feature of a pulsed light beam produced by an optical source is controlled by a method. The method includes producing a pulsed light beam at a pulse repetition rate; directing the pulsed light beam toward a substrate received in a lithography exposure apparatus to expose the substrate to the pulsed light beam; modifying a pulse repetition rate of the pulsed light beam as it is exposing the substrate. The method includes determining an amount of adjustment to a spectral feature of the pulsed light beam, the adjustment amount compensating for a variation in the spectral feature of the pulsed light beam that correlates to the modification of the pulse repetition rate of the pulsed light beam. The method includes changing the spectral feature of the poised light beam by the determined adjustment amount as the substrate is exposed to thereby compensate for the variation in the spectral feature.
摘要翻译：由光源产生的脉冲光束的光谱特征由方法控制。该方法包括以脉冲重复率产生脉冲光束; 朝向在光刻曝光设备中接收的衬底引导脉冲光束以将衬底暴露于脉冲光束; 修改脉冲光束在曝光衬底时的脉冲重复率。该方法包括确定对脉冲光束的光谱特征的调整量，该调整量补偿与脉冲光束的脉冲重复率的修改相关的脉冲光束的光谱特征的变化。该方法包括在曝光衬底时将稳定光束的光谱特征改变确定的调整量，从而补偿光谱特征的变化。

4. 发明申请

WO2018046246A1 METHOD AND APPARATUS TO MONITOR A PROCESS APPARATUS 审中-公开
标题翻译：监视过程设备的方法和设备
公开(公告)号：WO2018046246A1
公开(公告)日：2018-03-15
申请号：PCT/EP2017/070586
申请日：2017-08-14
申请人： ASML NETHERLANDS B.V.
发明人： MASLOW, Mark, John , MULKENS, Johannes, Catharinus, Hubertus , TEN BERGE, Peter , VAN DE MAST, Franciscus , GEMMINK, Jan-Willem , REIJNEN, Liesbeth
IPC分类号： G03F7/20
CPC分类号： H01L22/20 , G03F7/36 , G03F7/70616 , G03F7/70683 , H01L21/31105 , H01L21/31144 , H01L21/67253
摘要： A substrate, including a substrate layer; and an etchable layer on the substrate layer, the etchable layer including a patterned region thereon or therein and including a blank region of sufficient size to enable a bulk etch rate of an etch tool for etching the blank region to be determined.
摘要翻译：包括衬底层的衬底; 以及在衬底层上的可蚀刻层，可蚀刻层包括其上或其中的图案化区域，并且包括空白区域，该空白区域具有足够尺寸以使蚀刻工具的体蚀刻速率能够蚀刻待确定的空白区域。

5. 发明申请

WO2017185315A1 METHOD AND TEST SYSTEM FOR PROVIDING ACCURATE ANALOG SIGNALS 审中-公开
标题翻译：提供准确模拟信号的方法和测试系统
公开(公告)号：WO2017185315A1
公开(公告)日：2017-11-02
申请号：PCT/CN2016/080584
申请日：2016-04-29
申请人： TERADYNE (SHANGHAI) CO., LTD.
发明人： CHEN, Zai-man , ZHANG, Pei-Lai
IPC分类号： G01R31/00
CPC分类号： G01R31/2879 , G01R31/00 , G01R31/2601 , G01R31/2834 , G01R35/005 , H01L22/20
摘要： Automatic test equipment with multiple components to generate highly accurate and stable analog test signals and method for operating the test system in semiconductor manufacturing process are disclosed. Output analog signals from existing test systems often fail the stability and accuracy requirement with less than 10 mV variations for testing certain electronic devices, due in part to environmental condition variations such as temperature fluctuations. Traditional compensation mechanisms for temperature variations involve time consuming and disruptive calibration procedures. Disclosed here is a system and method that provides near real-time monitoring and compensation for temperature-induced variations via a digital control mechanism that compensates for environmental variations in a time scale of less than 10 milliseconds and maintains the AC output analog signal with 10 milliVolt accuracy.
摘要翻译：公开了具有多个组件的自动测试设备以生成高精度和稳定的模拟测试信号，以及用于在半导体制造过程中操作测试系统的方法。来自现有测试系统的输出模拟信号经常不能满足稳定性和精度要求，对于测试某些电子设备的变化小于10mV，这部分归因于诸如温度波动的环境条件变化。传统的温度变化补偿机制涉及耗时且破坏性的校准程序。这里公开了一种系统和方法，其通过数字控制机构提供对温度引起的变化的近实时监测和补偿，所述数字控制机构补偿在小于10毫秒的时间尺度内的环境变化并且保持AC输出模拟信号为10毫伏精度。

6. 发明申请

WO2017120370A1 FEATURE SELECTION AND AUTOMATED PROCESS WINDOW MONITORING THROUGH OUTLIER DETECTION 审中-公开
标题翻译：特征选择和自动化过程窗口监视通过OUTLIER DETECTION
公开(公告)号：WO2017120370A1
公开(公告)日：2017-07-13
申请号：PCT/US2017/012382
申请日：2017-01-05
申请人： KLA-TENCOR CORPORATION
发明人： GHADAR, Shabnam , JAHANBIN, Sina , VAJARIA, Himanshu , RIES, Bradley
IPC分类号： H01L21/66 , H01L21/67
CPC分类号： G05B19/41875 , G05B2219/37224 , G06N99/005 , H01L22/12 , H01L22/20 , Y02P90/22
摘要： Feature extraction and classification is used for process window monitoring. A classifier, based on combinations of metrics of masked die images and including a set of significant combinations of one or more segment masks, metrics, and wafer images, is capable of detecting a process non-compliance. A process status can be determined using a classifier based on calculated metrics. The classifier may learn from nominal data.
摘要翻译：
特征提取和分类用于过程窗口监视。基于掩蔽裸片图像的度量的组合并且包括一个或多个分段掩码，度量和晶片图像的一组重要组合的分类器能够检测过程不符合。可以使用基于计算量度的分类器来确定过程状态。分类器可以从名义数据中学习。

7. 发明申请

WO2017117051A1 WAFER SINGULATION PROCESS CONTROL 审中-公开
标题翻译：晶片过程控制
公开(公告)号：WO2017117051A1
公开(公告)日：2017-07-06
申请号：PCT/US2016/068519
申请日：2016-12-23
申请人： RUDOLPH TECHNOLOGIES, INC.
发明人： FITZGERALD, Wayne
IPC分类号： H01L21/78 , H01L21/76 , H01L21/02 , H01L21/764
CPC分类号： H01L21/78 , H01L22/12 , H01L22/20
摘要： A method for monitoring and controlling a substrate singulation process is described. Device edges are imaged and identified for analysis. Discrepancies in device edges are noted and used to modify a singulation process and to monitor the operation of singulation processes for anomalous behavior.
摘要翻译：描述了用于监视和控制衬底分割过程的方法。设备边缘被成像并被识别用于分析。记录器件边缘的差异，并用于修改单个化过程并监控单个化过程对异常行为的操作。

8. 发明申请

WO2017106788A1 METHODS FOR IMPROVING WAFER PLANARITY AND BONDED WAFER ASSEMBLIES MADE FROM THE METHODS 审中-公开
标题翻译：用这些方法改进晶片平坦度和结合晶片组件的方法
公开(公告)号：WO2017106788A1
公开(公告)日：2017-06-22
申请号：PCT/US2016/067379
申请日：2016-12-16
申请人： OSTENDO TECHNOLOGIES, INC.
发明人： BATINICA, Gregory , YADAVALLI, Kameshwar , FAN, Qian , HASKELL, Benjamin A. , EL-GHOROURY, Hussein S.
IPC分类号： H01L21/822 , H01L21/02 , H01L21/06 , H01L21/20 , H01L21/38 , H01L21/67
CPC分类号： H01L21/02035 , H01L21/02002 , H01L21/02164 , H01L21/0217 , H01L21/02172 , H01L21/02274 , H01L22/12 , H01L22/20 , H01L23/3171 , H01L23/562 , H01L24/94 , H01L29/2003 , H01L29/30 , H01L2224/94 , H01L2924/3511
摘要： A method to improve the planarity of a semiconductor wafer and an assembly made from the method. In a preferred embodiment of the method, a compressive PECVD oxide layer such as SiO2 having a predetermined thickness or pattern is deposited on the second surface of a semiconductor wafer having an undesirable warp or bow. The thickness or pattern of the deposited oxide layer is determined by the measured warp or bow of the semiconductor wafer. The compressive oxide layer induces an offsetting compressive force on the second surface of the semiconductor wafer to reduce the warp and bow across the major surface of the semiconductor wafer.
摘要翻译：一种改善半导体晶片平面度的方法和由该方法制成的组件。在该方法的优选实施例中，具有预定厚度或图案的诸如SiO 2的压缩PECVD氧化物层被沉积在具有不希望的弯曲或弯曲的半导体晶片的第二表面上。沉积的氧化物层的厚度或图案由测量的半导体晶片的翘曲或弯曲确定。压缩氧化物层在半导体晶片的第二表面上引起偏移压缩力，以减少跨过半导体晶片的主表面的翘曲和弯曲。

9. 发明申请

WO2017078933A1 TECHNIQUES FOR COMBINING CMP PROCESS TRACKING DATA WITH 3D PRINTED CMP CONSUMABLES 审中-公开
标题翻译： CMP过程跟踪数据与3D打印CMP耗材的组合CMP技术
公开(公告)号：WO2017078933A1
公开(公告)日：2017-05-11
申请号：PCT/US2016/057669
申请日：2016-10-19
申请人： APPLIED MATERIALS, INC.
发明人： FUNG, Jason G. , BAJAJ, Rajeev , REDFIELD, Daniel , KHANNA, Aniruddh , CORNEJO, Mario , MENK, Gregory E. , WATKINS, John
IPC分类号： H01L21/304 , H01L21/306 , H01L21/67
CPC分类号： H01L21/67253 , B24B37/26 , B24B49/003 , B24B49/10 , B24B49/14 , B24B49/16 , B29C64/106 , B29K2995/0003 , B29K2995/0005 , B29L2031/736 , B33Y10/00 , B33Y80/00 , H01L21/30625 , H01L21/67075 , H01L21/67294 , H01L22/12 , H01L22/20 , H01L22/26
摘要： Chemical mechanical polishing (CMP) apparatus and methods for manufacturing CMP apparatus are provided herein. CMP apparatus may include polishing pads, polishing head retaining rings, and polishing head membranes, among others, and the CMP apparatus may be manufactured via additive manufacturing processes, such as three dimensional (3D) printing processes. The CMP apparatus may include wireless communication apparatus components integrated therein. Methods of manufacturing CMP apparatus include 3D printing wireless communication apparatus into a polishing pad and printing a polishing pad with a recess configured to receive a preformed wireless communication apparatus.
摘要翻译：本文提供化学机械抛光（CMP）设备和用于制造CMP设备的方法。 CMP设备可以包括抛光垫，抛光头保持环和抛光头膜等等，并且CMP设备可以通过增材制造工艺例如三维（3D）印刷工艺制造。 CMP设备可以包括集成在其中的无线通信设备组件。制造CMP设备的方法包括将3D无线通信设备3D打印到抛光垫中并且打印带有凹槽的抛光垫，所述凹槽被配置为容纳预先形成的无线通信设备。

10. 发明申请

WO2017066341A1 MULTI-DIE PACKAGE COMPRISING UNIT SPECIFIC ALIGNMENT AND UNIT SPECIFIC ROUTING 审中-公开
标题翻译：多模包装，包含单元特定的对齐和单元特定的布线
公开(公告)号：WO2017066341A1
公开(公告)日：2017-04-20
申请号：PCT/US2016/056670
申请日：2016-10-12
申请人： DECA TECHNOLOGIES INC.
发明人： BISHOP, Craig
IPC分类号： H01L21/768
CPC分类号： H01L22/26 , H01L21/568 , H01L22/12 , H01L22/20 , H01L23/5386 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/96 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/24137 , H01L2224/94 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2224/214
摘要： A method of making a semiconductor device can include forming an embedded die panel by encapsulating a first semiconductor die and a second semiconductor die with conductive interconnects in a single step. An actual position of the first semiconductor die and second semiconductor die can be measured within the embedded die panel. The first semiconductor die and the second semiconductor die can be interconnected by a build-up interconnect structure comprising a first unit specific alignment portion aligned with the first semiconductor die, a second unit specific alignment portion aligned with the second semiconductor die, unit specific routing connecting the first unit specific alignment portion and the second unit specific alignment portion, and a fixed portion aligned with outline of embedded die panel and coupled to the unit specific routing.
摘要翻译：制造半导体器件的方法可以包括通过在单个步骤中用导电互连封装第一半导体管芯和第二半导体管芯形成嵌入式管芯面板。可以在嵌入式模具面板内测量第一半导体管芯和第二半导体管芯的实际位置。第一半导体管芯和第二半导体管芯可通过构建互连结构互连，所述构建互连结构包括与第一半导体管芯对准的第一单元特定对准部分，与第二半导体管芯对准的第二单元特定对准部分，单元特定路由连接第一单元特定对准部分和第二单元特定对准部分，以及固定部分，其与嵌入式模具面板的轮廓对齐并且耦合到单元特定布线。

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