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1. 发明申请

WO2014129351A1 半導体装置とその製造方法审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2014129351A1
公开(公告)日：2014-08-28
申请号：PCT/JP2014/053157
申请日：2014-02-12
申请人：ピーエスフォールクスコエスエイアールエル , 友廣任志
发明人：友廣　任志
IPC分类号： H01L23/00 , H01L23/12
CPC分类号： H01L23/552 , H01L21/56 , H01L21/561 , H01L23/16 , H01L23/3107 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/544 , H01L24/16 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2223/54406 , H01L2223/5442 , H01L2223/54433 , H01L2223/54486 , H01L2224/0401 , H01L2224/04042 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2224/92247 , H01L2224/97 , H01L2225/0651 , H01L2225/06517 , H01L2225/06558 , H01L2225/06568 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/00 , H01L2924/00012 , H01L2224/83 , H01L2224/85 , H01L2224/45015 , H01L2924/207
摘要：　半導体装置１が、配線基板３と、配線基板３の一方の面に積層され、配線基板３に向いた第１の面４ａと第１の面４ａの反対側に位置する第２の面４ｂとを有し、少なくとも第２の面４ｂに回路が形成されている、半導体チップ４と、半導体チップ４の第２の面４ｂに積層されている、回路が形成されていない回路非内蔵チップ１１と、少なくとも配線基板３と回路非内蔵チップ１１との間に配置されている封止樹脂２と、を含む。それにより、半導体チップを内蔵した半導体装置にマーキングを形成するためのレーザ照射を行う際などに与えられたエネルギーが、半導体チップに形成された回路を損傷することを抑える。
摘要翻译：半导体器件（1）包括：布线基板（3）; 层叠在所述布线基板（3）的一个面上且具有面对所述布线基板（3）的第一面（4a）的半导体芯片（4）和位于与所述第一面（4a）相反侧的第二面），至少形成在所述第二面（4b）上的电路; 其中不形成电路的非电路结合芯片（11），非电路结合芯片（11）层叠在半导体芯片（4）的第二面（4b）上; 以及设置在至少布线基板（3）和非电路结合芯片（11）之间的密封树脂（2）。该结构通过在半导体芯片的结合的半导体器件上形成标记的激光照射等处理中的能量来抑制对半导体芯片中形成的电路的损坏。

2. 发明申请

WO2011133743A3 INTERLEAF FOR LEADFRAME IDENTIFICATION 审中-公开
标题翻译： LEADFRAME识别语言
公开(公告)号：WO2011133743A3
公开(公告)日：2012-01-26
申请号：PCT/US2011033378
申请日：2011-04-21
申请人： TEXAS INSTRUMENTS INC , TEXAS INSTRUMENTS JAPAN , TELLKAMP JOHN P
发明人： TELLKAMP JOHN P
IPC分类号： H01L23/495
CPC分类号： H01L22/14 , H01L23/49565 , H01L23/544 , H01L2223/54406 , H01L2223/54433 , H01L2223/54473 , H01L2223/54486 , H01L2924/0002 , H01L2924/00
摘要： A method of making an integrated circuit (IC) device includes providing a stack of leadframe sheets each including a plurality of leadframes and an interleaf member interposed between adjacent ones of the leadframe sheets (101). The interleaf members include indicia that identifies the leadframes sheets (101). The stack of leadframe sheets is loaded onto an assembly machine (102). A first interleaf member is removed from the first leadframe sheet (103). The first leadframe sheet is transferred onto a mounting surface of the assembly machine (104). Semiconductor die are attached to leadframes on the first leadframe sheet (105). The method can include reading the indicia from the first interleaf member to determine a part number and lead surface texture finish for the first leadframe sheet, verifying the part number for the first leadframe sheet by comparing to a build list, and transferring the first leadframe sheet onto a mounting surface of the assembly machine only if the part number is verified.
摘要翻译：一种制造集成电路（IC）装置的方法包括提供一堆引线框片，每个引线框片片包括多个引线框架和插入在相邻的引线框架片材之间的插入件。插页成员包括标识引线框片（101）的标记。引线框架的堆叠被装载到组装机器（102）上。从第一引线框片（103）移除第一夹层构件。第一引线框片转移到组装机（104）的安装表面上。半导体管芯附接到第一引线框片（105）上的引线框架。该方法可以包括从第一夹层构件读取标记以确定第一引线框片的部件号和引线表面纹理完成，通过与构建列表进行比较来验证第一引线框片的部件号，以及将第一引线框片只有在部件编号被验证的情况下，才能到装配机的安装表面上。

3. 发明申请

WO2011139606A1 METHOD FOR TRACING INDIVIDUAL DIES 审中-公开
标题翻译：跟踪个体化方法
公开(公告)号：WO2011139606A1
公开(公告)日：2011-11-10
申请号：PCT/US2011/033611
申请日：2011-04-22
申请人： MEDTRONIC, INC. , MEYERSON, Charles, M. , DICKES, Eric, J. , GORTON, William, V. , GRAHAM, Stephen, W. , HEAMES, Kenneth , JOHNSON, Dennis, B. , OHME, Christopher, D. , WARREN, Steven, C.
发明人： MEYERSON, Charles, M. , DICKES, Eric, J. , GORTON, William, V. , GRAHAM, Stephen, W. , HEAMES, Kenneth , JOHNSON, Dennis, B. , WARREN, Steven, C.
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L2223/54406 , H01L2223/54413 , H01L2223/54433 , H01L2223/54473 , H01L2223/5448 , H01L2223/54486 , H01L2924/0002 , H01L2924/00
摘要： A method for tracing individual dies (12) within stacked chip scale packages includes the steps of recording unique die identifiers (14) from layers of marked dies and associating the unique identifiers with a die bonding substrate and the resulting die or stacked chip scale packages. The unique die identifiers are also associated with wafer numbers, x-y positions on a wafer, wafer lot numbers or any combination thereof.
摘要翻译：用于跟踪堆叠的芯片级封装内的单个管芯（12）的方法包括以下步骤：从标记管芯的层记录唯一的管芯标识符（14），并将唯一标识符与管芯接合衬底以及所得到的管芯或堆叠的芯片级封装相关联。唯一的裸片标识符也与晶片号，晶片上的x-y位置，晶片批号或其任何组合相关联。

4. 发明申请

WO2010044783A1 SEMICONDUCTOR PACKAGE HAVING MARKING LAYER 审中-公开
标题翻译：具有标记层的半导体封装
公开(公告)号：WO2010044783A1
公开(公告)日：2010-04-22
申请号：PCT/US2008/079912
申请日：2008-10-15
申请人： TEXAS INSTRUMENTS INCORPORATED , ANO, Kazuaki , LEE, Wen, Yu
发明人： ANO, Kazuaki , LEE, Wen, Yu
IPC分类号： H01L23/544 , H01L23/00
CPC分类号： H01L21/565 , B41M5/24 , B41M5/26 , H01L23/3128 , H01L23/544 , H01L24/16 , H01L24/31 , H01L24/48 , H01L24/85 , H01L24/97 , H01L2223/54406 , H01L2223/54433 , H01L2223/5448 , H01L2223/54486 , H01L2224/04042 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/2919 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/85 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/10329 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/83 , H01L2924/0665 , H01L2924/07025 , H01L2924/00 , H01L2224/05599 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/0555 , H01L2224/0556
摘要： The symbolization of a semiconductor device (100) is incorporated in a thin sheet (130) attached to the top of the device, facing outwardly with its bare surface. The material of the sheet (about 1 to 10 μm thick) includes regions of a first optical reflectivity and a first color, and regions (133) of a second optical reflectivity and a second color, which differ from, and contrast with, the first reflectivity and color. Preferred choices for the sheet material include the compound o-cresol novolac epoxy and the compound bisphenol-A, more preferably with the chemical imidazole added to the film material. A preferred embodiment of the invention is a packaged device with a semiconductor chip a (101) connected to a substrate (102); the connection is achieved by bonding wires (111) forming an arch with a top 111a. The chip, the wire arches, and the substrate are embedded in an encapsulation material (120), which borders on the attached top sheet so that the arch tops touch the border (131).
摘要翻译：半导体器件（100）的符号化被结合在附接到器件的顶部的薄片（130）中，薄片（130）面向外并具有裸露的表面。片材的材料（约1至10μm厚）包括第一光学反射率和第一颜色的区域，以及第二光学反射率和第二颜色的区域（133），其与第一光学反射率和第二颜色的区别反射率和颜色。片材的优选选择包括化合物邻甲酚酚醛清漆环氧树脂和化合物双酚A，更优选加入薄膜材料中的化学咪唑。本发明的优选实施例是具有连接到衬底（102）的半导体芯片a（101）的封装器件; 通过将形成拱的线（111）与顶部111a接合来实现连接。芯片，线拱和衬底嵌入在封装材料（120）中，封装材料（120）与附接的顶片接合，使得拱顶接触边界（131）。

5. 发明申请

WO2010036579A2 LOW COST DIE-TO-WAFER ALIGNMENT/BOND FOR 3D IC STACKING 审中-公开
标题翻译：低成本三维IC堆叠的对角线对准/绑定
公开(公告)号：WO2010036579A2
公开(公告)日：2010-04-01
申请号：PCT/US2009057515
申请日：2009-09-18
申请人： QUALCOMM INC , GU SHIQUN , TOMS THOMAS R
发明人： GU SHIQUN , TOMS THOMAS R
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L2223/54406 , H01L2223/54426 , H01L2223/5446 , H01L2223/5448 , H01L2225/06513 , H01L2225/06593 , H01L2924/0002 , H01L2924/10253 , H01L2924/14 , H01L2924/00
摘要： The cost associated with alignment in a stacked IC device can be reduced by aligning multiple die instead of a single die during the alignment step. In one embodiment, the alignment structures are placed in the scribe line instead of within the die itself. Aligning four die instead of one eliminates the need for as many alignment indicators and thus more silicon on the wafer can be used for active areas. In addition, this method allows for yield improvement through binning of dies having the same yield configuration.
摘要翻译：在对准步骤期间，可以通过对准多个管芯而不是单个管芯来降低与叠置的IC器件中的对准相关的成本。在一个实施例中，对准结构被放置在划线中，而不是在模具本身内。对准四个模具而不是一个消除了对于多个对准指示器的需要，因此在晶片上更多的硅可用于有源区域。此外，该方法允许通过对具有相同产量构型的模具进行分级来提高产量。

6. 发明申请

WO2010005394A1 LASER PROCESSING SYSTEM AND METHOD 审中-公开
标题翻译：激光加工系统和方法
公开(公告)号：WO2010005394A1
公开(公告)日：2010-01-14
申请号：PCT/SG2008/000249
申请日：2008-07-11
申请人： AEM SINGAPORE PTE LTD , CHENG, Chee Yuen , LAW, Chi Kin Denis , MA, Bo , MUTHUVEL, Parthasarathy , WAN, Qiu , WEI, Jian Dong
发明人： CHENG, Chee Yuen , LAW, Chi Kin Denis , MA, Bo , MUTHUVEL, Parthasarathy , WAN, Qiu , WEI, Jian Dong
IPC分类号： B23K26/02 , B23K26/04
CPC分类号： B23K26/043 , B23K26/04 , B23K26/082 , H01L23/544 , H01L2223/54406 , H01L2223/5448 , H01L2924/0002 , H01L2924/00
摘要： A laser processing system and method. The system comprises a laser source; an imaging device for capturing positional information of a workpiece under processing for controlling a scanning mechanism for directing a laser beam from the laser source onto the workpiece; and the scanning mechanism for directing the laser beam from the laser source to the workpiece along a laser path based on the positional information feedbacked from the imaging device; wherein an optical path of light captured by the imaging device comprises the laser path.
摘要翻译：一种激光加工系统及方法。该系统包括一个激光源; 用于捕获在处理中的工件的位置信息的成像装置，用于控制用于将来自激光源的激光束引导到工件上的扫描机构; 以及基于从成像装置反馈的位置信息，沿着激光路径将激光束从激光源引导到工件的扫描机构; 其中由所述成像装置捕获的光的光路包括所述激光路径。

7. 发明申请

WO2007080375A1 VERIFICATION OF PERFORMANCE ATTRIBUTES OF PACKAGED INTEGRATED CIRCUITS 审中-公开
标题翻译：包装集成电路性能特性的验证
公开(公告)号：WO2007080375A1
公开(公告)日：2007-07-19
申请号：PCT/GB2007/000015
申请日：2007-01-03
申请人： INGENIA HOLDINGS (UK) LIMITED , COWBURN, Russell, Paul , BUCHANAN, James, David, Ralph
发明人： COWBURN, Russell, Paul , BUCHANAN, James, David, Ralph
IPC分类号： H01L23/544
CPC分类号： G01R31/31719 , G01R31/2896 , G01R31/31718 , H01L23/544 , H01L23/573 , H01L2223/54406 , H01L2223/54413 , H01L2223/54473 , H01L2223/54486 , H01L2924/0002 , H01L2924/00
摘要： Packaged integrated circuits (ICs) of some types, such as processors, are graded and sold according to a performance scale, such as maximum specified clock speed, set by the manufacturer as a result of testing. As a record of this grading some part of the package, usually the upper surface, is marked with the specified performance attribute. However, criminal activity has developed where the packaging is relabelled to show a higher specification so the ICs can be fraudulently resold at a higher price. To address this problem, the invention envisages that manufacturers maintaining a product database for each packaged IC which logs not only the performance specification, but also a digital signature derived from a speckle pattern obtained from the packaging. Subsequently, any packaged IC can be rescanned to interrogate its speckle pattern and recompute the signature. The signature is then used to find the product in the database, whereby the originally specified performance attribute is retrieved. The fraud is then detectable. This method can be used to test products returned under a warranty claim, for example.
摘要翻译：某些类型的封装集成电路（如处理器）根据测试结果由制造商设定的性能规模进行分级和出售，例如最大规定的时钟速度。作为此分级的记录，包的某些部分（通常为上表面）标有指定的性能属性。然而，犯罪活动已经发展到包装被重新标榜以显示更高的规格，所以IC可以以更高的价格欺诈地转售。为了解决这个问题，本发明设想制造商为每个封装的IC维护产品数据库，其不仅记录性能规范，而且还记录从包装获得的散斑图案中得到的数字签名。随后，可以重新扫描任何封装的IC以询问其斑点图案并重新计算签名。然后使用签名在数据库中查找产品，从而检索最初指定的性能属性。然后可以检测到欺诈。例如，该方法可用于测试以保修索赔退回的产品。

8. 发明申请

WO2003073504A1 SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING HIGH CONTRAST IDENTIFICATION MARK 审中-公开
标题翻译：半导体器件和生产高对比度识别标记的方法
公开(公告)号：WO2003073504A1
公开(公告)日：2003-09-04
申请号：PCT/US2002/003768
申请日：2002-02-07
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, L.L.C. , SEDDON, Michael , CARNEY, Francis
发明人： SEDDON, Michael , CARNEY, Francis
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L2223/54406 , H01L2223/54473 , H01L2224/16 , H01L2924/01004 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044
摘要： A seconductor device (50) includes a semiconductor die (20) having a first surface (14) for forming electronic circuitry. A coating layer (16) formed on a second surface (15) of the semiconductor die has a color that contrasts with the color of the semiconductor die. The coating layer is patterned to expose a portion of the second surface to reveal information pertaining to the semiconductor device. The coating layer is patterned by directing a radiation beam (30) such as a laser to selectively remove material from the coating layer.
摘要翻译：断电装置（50）包括具有用于形成电子电路的第一表面（14）的半导体管芯（20）。形成在半导体管芯的第二表面（15）上的涂层（16）具有与半导体管芯的颜色对比的颜色。图案化涂层以暴露第二表面的一部分以揭示关于半导体器件的信息。通过引导诸如激光器的辐射束（30）来选择性地从涂层去除材料来对涂层进行图案化。

9. 发明申请

WO03038896A3 BALL GRID ARRAY WITH X-RAY ALIGNMENT MARK 审中-公开
标题翻译：球形阵列与X射线对准标记
公开(公告)号：WO03038896A3
公开(公告)日：2003-07-31
申请号：PCT/US0234809
申请日：2002-10-29
申请人： QUALCOMM INC
发明人： PRIMROSE PAUL W
IPC分类号： H01L21/60 , H01L23/498 , H01L23/544 , H05K1/02 , H05K3/30
CPC分类号： H01L24/81 , H01L23/49816 , H01L23/544 , H01L2223/54406 , H01L2223/5442 , H01L2223/54473 , H01L2223/5448 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/81801 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H05K1/0269 , H05K3/303 , H05K2201/09918 , H05K2201/10734 , H05K2203/168
摘要： An apparatus and method for inspecting electronic component orientation along with x-ray verification of connection integrity is presented. An exemplary method comprises providing an electronic component 100 for surface mount integration and providing an x-ray visible orientation indicator 300, 402, 500, 600 for the electronic component 100 such that proper orientation of the electronic component 100 is verifiable by x-ray inspection after performing surface mount integration of the electronic component. The x-ray inspection also makes connection integrity of the electronic component 100 verifiable.
摘要翻译：提出了一种用于检查电子元件定向以及连接完整性的x射线验证的设备和方法。示例性方法包括提供用于表面安装集成的电子部件100，并为电子部件100提供x射线可见取向指示器300,402,500,600，使得电子部件100的正确取向可通过x射线检查来验证在执行电子元件的表面贴装集成之后。 x射线检查还使电子部件100的连接完整性可验证。

10. 发明申请

WO01061754A1 SEMICONDUCTOR DEVICE FABRICATION METHOD AND SEMICONDUCTOR DEVICE FABRICATION DEVICE 审中-公开
标题翻译：半导体器件制造方法和半导体器件制造装置
公开(公告)号：WO01061754A1
公开(公告)日：2001-08-23
申请号：PCT/JP2001/001091
申请日：2001-02-15
IPC分类号： G01R31/26 , H01L21/50 , H01L21/58 , H01L21/66 , H01L21/98 , H01L23/04 , H01L23/10 , H01L23/13 , H01L23/498 , H01L23/50 , H01L23/544 , H01L25/16 , H01L25/00 , H01L23/00
CPC分类号： H01L22/20 , H01L21/50 , H01L23/04 , H01L23/10 , H01L23/13 , H01L23/49805 , H01L23/50 , H01L23/544 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L25/16 , H01L25/165 , H01L25/50 , H01L2223/54406 , H01L2223/54473 , H01L2223/54486 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83192 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/1306 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15313 , H01L2924/15787 , H01L2924/16152 , H01L2924/16315 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/05599 , H01L2224/32245 , H01L2224/48247
摘要： A semiconductor device fabrication method which reduces the number of production steps and streamlines a production line, and which completes each of high frequency modules by mounting and assembling chip parts (22) and semiconductor pellets (21) onto a wiring board (2) included in an inspected multiple-block substrate (27), wherein a wiring board (2), that is, a block found to be defective during the inspection of the multiple-block substrate (27) is fixed with a rejection mark (2e), and a rejection mark is identified in each of a series of assembly steps that follow to omit any work otherwise required on the wiring board (2) formed with the rejection mark (2e), thereby streamlining a production line.
摘要翻译：一种半导体器件制造方法，其减少生产步骤的数量并简化生产线，并且通过将芯片部件（22）和半导体芯片（21）安装和组装到包括在其中的线路板（2）上来完成每个高频模块。检查多块基板（27），其中在多块基板（27）的检查期间发现有缺陷的布线板（2）被固定有排斥标记（2e），并且在随后的一系列组装步骤中的每一个中识别出拒绝标记，以省略形成有拒收标记（2e）的布线板（2）上另外需要的任何工作，从而简化生产线。

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