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1. 发明申请

WO2012135832A2 VOLTAGE SWITCHABLE DIELECTRIC FOR DIE-LEVEL ELECTROSTATIC DISCHARGE (ESD) PROTECTION 审中-公开
标题翻译：用于模块级静电放电（ESD）保护的电压可切换介质
公开(公告)号：WO2012135832A2
公开(公告)日：2012-10-04
申请号：PCT/US2012031861
申请日：2012-04-02
申请人： QUALCOMM INC , GU SHIQUN , RADOJCIC RATIBOR , LI YIMING
发明人： GU SHIQUN , RADOJCIC RATIBOR , LI YIMING
IPC分类号： H01L23/60
CPC分类号： H01L23/62 , H01L23/29 , H01L23/60 , H01L24/05 , H01L24/06 , H01L24/16 , H01L25/0657 , H01L2224/0401 , H01L2224/05567 , H01L2224/0557 , H01L2224/06181 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/12042 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC.
摘要翻译：可以在用于静电放电（ESD）保护的管芯上采用电压可切换介电层。在模具的正常操作期间，电压可切换介电层用作裸片的端子之间的介电层。当ESD事件发生在管芯的端子处时，端子之间的高电压将电压可切换介电层切换为导电层，以允许电流放电至管芯的接地端子，而电流不通过管芯的电路。因此，在具有电压可切换电介质层的管芯上的ESD事件期间，减小或防止了管芯电路的损坏。可以在用第二管芯堆叠期间将电压可切换介电层沉积在管芯的背侧以用于保护以形成堆叠式IC。

2. 发明申请

WO2011163213A1 DYNAMIC INTERLEAVING OF MULTI-CHANNEL MEMORY 审中-公开
标题翻译：多通道存储器的动态切换
公开(公告)号：WO2011163213A1
公开(公告)日：2011-12-29
申请号：PCT/US2011/041229
申请日：2011-06-21
申请人： QUALCOMM INCORPORATED , WANG, Feng , GU, Shiqun , NOWAK, Matthew Michael
发明人： WANG, Feng , GU, Shiqun , NOWAK, Matthew Michael
IPC分类号： G06F13/16
CPC分类号： G06F13/1652 , G06F13/1684 , Y02D10/14
摘要： In a particular embodiment, a dynamic interleaving system changes the number of interleaving channels of a multi-channel memory based on a detected level of bandwidth requests from a plurality of master ports to a plurality of slave ports. At a low level of bandwidth requests, the number of interleaving channels is reduced.
摘要翻译：在特定实施例中，动态交织系统基于从多个主端口到多个从端口的检测到的带宽请求的级别来改变多信道存储器的交织通道的数量。在低等级的带宽请求下，减少了交织信道的数量。

3. 发明申请

WO2011116326A1 THROUGH-SILICON VIA FABRICATION WITH ETCH STOP FILM 审中-公开
标题翻译：通过硅胶制成的薄膜
公开(公告)号：WO2011116326A1
公开(公告)日：2011-09-22
申请号：PCT/US2011/029058
申请日：2011-03-18
申请人： QUALCOMM Incorporated , GU, Shiqun , LI, Yiming , RAY, Urmi
发明人： GU, Shiqun , LI, Yiming , RAY, Urmi
IPC分类号： H01L21/768
CPC分类号： H01L21/76898
摘要： For a semiconductor wafer substrate (102) having an inter layer dielectric (110), a through - silicon via may be formed in the substrate by first depositing an etch stop film (202) on top of the inter layer dielectric, followed by etching an opening (204) through the etch stop film, the interlayer dielectric, and into the substrate. A dielectric liner (206) is then deposited over the etch stop film and into the opening. For some embodiments, the dielectric liner may be etched away except for those portions adhering to the sidewall of the opening. Then a conductive material (208) may be deposited into the opening and on the etch stop film. The excess conductive material may then be removed, and for some embodiments the etch stop film may also be removed.
摘要翻译：对于具有层间电介质（110）的半导体晶片基板（102），可以通过首先在层间电介质的顶部上沉积蚀刻停止膜（202），然后蚀刻通过蚀刻停止膜，层间电介质，并进入衬底的开口（204）。然后将电介质衬垫（206）沉积在蚀刻停止膜上并进入开口中。对于一些实施例，除了粘附到开口的侧壁上的那些部分之外，电介质衬垫可被蚀刻掉。然后可以将导电材料（208）沉积到开口中和蚀刻停止膜上。然后可以除去过量的导电材料，并且对于一些实施例，也可以去除蚀刻停止膜。

4. 发明申请

WO2011097464A1 SURFACE PREPARATION OF DIE FOR IMPROVED BONDING STRENGTH 审中-公开
标题翻译：用于改进粘结强度的表面制备
公开(公告)号：WO2011097464A1
公开(公告)日：2011-08-11
申请号：PCT/US2011/023726
申请日：2011-02-04
申请人： QUALCOMM INCORPORATED , CHANDRASEKARAN, Arvind , GU, Shiqun , RAY, Urmi
发明人： CHANDRASEKARAN, Arvind , GU, Shiqun , RAY, Urmi
IPC分类号： H01L21/56 , H01L23/31 , H01L25/065
CPC分类号： H01L23/3142 , H01L21/563 , H01L23/293 , H01L23/3128 , H01L23/3135 , H01L23/3192 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L2224/0401 , H01L2224/05022 , H01L2224/05147 , H01L2224/0557 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/73203 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2924/00014 , H01L2924/0002 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2224/05552 , H01L2924/00
摘要： A surface preparation method for improved adhesion in an electronic package system. The method of improving adhesion in the electronic package system includes depositing a passivation layer on a bonding surface and roughening at least a portion of the passivation layer. A coating material is deposited on the passivation layer. The bonding surface can be part of a semiconductor or package substrate. The roughening process can be performed by a chemical or mechanical process. In another embodiment, an electronic package system includes a bonding surface of a semiconductor or package substrate. A passivation layer is deposited on the bonding surface and a portion of the passivation layer is roughened for improved adhesion. A coating material is deposited on the roughened portion of the passivation layer.
摘要翻译：一种用于改善电子封装系统中的附着力的表面处理方法。提高电子封装系统中的附着力的方法包括在接合表面上沉积钝化层并使钝化层的至少一部分变粗糙。在钝化层上沉积涂层材料。接合表面可以是半导体或封装衬底的一部分。粗化工艺可以通过化学或机械工艺进行。在另一个实施例中，电子封装系统包括半导体或封装衬底的接合表面。钝化层沉积在接合表面上，钝化层的一部分被粗糙化以提高粘附力。在钝化层的粗糙化部分上沉积涂层材料。

5. 发明申请

WO2011075491A1 VIA STRUCTURE INTEGRATED IN ELECTRONIC SUBSTRATE 审中-公开
标题翻译：通过集成在电子基板中的结构
公开(公告)号：WO2011075491A1
公开(公告)日：2011-06-23
申请号：PCT/US2010/060362
申请日：2010-12-14
申请人： QUALCOMM Incorporated , LI, Xia , ZHAO, Wei , CAO, Yu , GU, Shiqun , KANG, Seung H. , KING, Ming-Chu
发明人： LI, Xia , ZHAO, Wei , CAO, Yu , GU, Shiqun , KANG, Seung H. , KING, Ming-Chu
IPC分类号： H01L23/552 , H01L23/66 , H01L23/498 , H01L23/48 , H01L23/64 , H05K1/02
CPC分类号： H01L23/552 , H01L23/14 , H01L23/49827 , H01L23/645 , H01L23/66 , H01L2223/6616 , H01L2223/6622 , H01L2223/6638 , H01L2924/0002 , H01L2924/3011 , H05K1/0222 , H05K1/0245 , H05K3/4602 , H05K3/4644 , H05K2201/09809 , Y10T29/49117 , H01L2924/00
摘要： A system of via structures disposed in a substrate. The system includes a first via structure that comprises an outer conductive layer, an inner insulating layer, and an inner conductive layer disposed in the substrate. The outer conductive layer separates the inner insulating layer and the substrate and the inner insulating layer separates the inner conductive layer and the outer conductive layer. A first signal of a first complementary pair passes through the inner conductive layer and a second signal of the first complementary pair passes through the outer conductive layer. In different embodiments, a method of forming a via structure in an electronic substrate is provided.
摘要翻译：设置在基板中的通孔结构的系统。该系统包括第一通孔结构，其包括外导电层，内绝缘层和设置在基板中的内导电层。外部导电层分离内部绝缘层和基板，内部绝缘层分离内部导电层和外部导电层。第一互补对的第一信号通过内导电层，第一互补对的第二信号通过外导电层。在不同的实施例中，提供了一种在电子衬底中形成通孔结构的方法。

6. 发明申请

WO2010096577A1 NOVEL METHOD OF AIR GAP PATTERN FOR ADVANCED BACK END OF LINE (BEOL) INTERCONNECT 审中-公开
标题翻译：用于高级后端（BEOL）互连的空气隙图案的新方法
公开(公告)号：WO2010096577A1
公开(公告)日：2010-08-26
申请号：PCT/US2010/024612
申请日：2010-02-18
申请人： QUALCOMM INCORPORATED , GU, Shiqun
发明人： GU, Shiqun
IPC分类号： H01L21/768 , H01L21/311
CPC分类号： H01L21/7682 , H01L21/31144
摘要： An air gap pattern is created for backend of line (BEOL) interconnects. The method includes designing a nano-island pattern, and etching through the designed nano-island pattern to create at least one air gap between wire connects.
摘要翻译：为后端线（BEOL）互连创建气隙图案。该方法包括设计纳米岛图案，并且通过设计的纳米岛图案进行蚀刻以在线连接之间产生至少一个气隙。

7. 发明申请

WO2010021981A1 CAPACITIVE MEMS-BASED DISPLAY WITH TOUCH POSITION SENSING 审中-公开
标题翻译：具有触摸位置感测功能的基于MEMS的电容显示器
公开(公告)号：WO2010021981A1
公开(公告)日：2010-02-25
申请号：PCT/US2009/054031
申请日：2009-08-17
申请人： QUALCOMM INCORPORATED , GU, Shiqun , NOWAK, Matthew
发明人： GU, Shiqun , NOWAK, Matthew
IPC分类号： G06F3/041
CPC分类号： G06F3/0412 , G06F3/044
摘要： A micro-electro-mechanical systems (MEMS) pixel for display and touch position sensing includes a substrate and a capacitive element. The capacitive element includes one or more pixels having a first conductive platelet above the substrate, and a second conductive platelet above and spaced apart from the first conductive platelet, the two platelets forming the capacitive element. A connection to each platelet provides for applying a voltage, wherein the platelet separation changes according to the applied voltage. A transparent dielectric plate, spaced apart from and positioned opposite the substrate, covers the at least one pixel. A capacitance sensing circuit attached to the connection to each platelet of the pixel senses changes in capacitance not resulting from the applied voltage.
摘要翻译：用于显示和触摸位置感测的微电子机械系统（MEMS）像素包括基板和电容元件。电容元件包括一个或多个像素，其具有在衬底上方的第一导电片，以及在第一导电片上方并与第一导电片形成间隔开的第二导电片，所述两片片形成电容元件。与每个血小板的连接提供施加电压，其中血小板分离根据所施加的电压而改变。与衬底间隔开并与衬底相对设置的透明电介质板覆盖至少一个像素。连接到与像素的每个血小板的连接的电容感测电路感测不是由施加电压引起的电容变化。

8. 发明申请

WO2009129283A1 MANUFACTURING METHOD OF A MAGNETIC TUNNEL JUNCTION ELEMENT USING TWO MASKS 审中-公开
标题翻译：使用两个掩模的磁性隧道结构元件的制造方法
公开(公告)号：WO2009129283A1
公开(公告)日：2009-10-22
申请号：PCT/US2009/040612
申请日：2009-04-15
申请人： QUALCOMM INCORPORATED , KANG, Seung, H. , LI, Xia , GU, Shiqun , NOWAK, Matthew, M.
发明人： KANG, Seung, H. , LI, Xia , GU, Shiqun , NOWAK, Matthew, M.
IPC分类号： H01L43/08 , H01L43/12
CPC分类号： H01L43/08 , G11C11/161 , H01L43/12
摘要： A method for forming a magnetic tunnel junction (MTJ) for magnetic random access memory (MRAM) using two masks includes depositing over an interlevel dielectric layer (36) containing an exposed first interconnect metallization, (37) a first electrode, (30) a fixed magnetization layer, (32) a tunneling barrier layer, (12) a free magnetization layer (11) and a second electrode (6). An MTJ structure including the tunnel barrier layer, free layer and second electrode is defined above the first interconnect metallization by a first mask. A first passivation layer (40) encapsulates the MTJ structure, leaving the second electrode exposed. A third electrode (15) is deposited in contact with the second electrode. A second mask is used to pattern a larger structure including the third electrode, the first passivation layer, the fixed magnetization layer and the first electrode. A second dielectric passivation layer (8) covers the etched plurality of layers, the first interlevel dielectric layer and the first interconnect metallization.
摘要翻译：用于使用两个掩模形成用于磁性随机存取存储器（MRAM）的磁性隧道结（MTJ）的方法包括在包含暴露的第一互连金属化的层间介质层（36）上沉积（37）第一电极，（30）固定磁化层，（32）隧道势垒层，（12）自由磁化层（11）和第二电极（6）。包括隧道势垒层，自由层和第二电极的MTJ结构通过第一掩模限定在第一互连金属化之上。第一钝化层（40）封装MTJ结构，留下第二电极。沉积与第二电极接触的第三电极（15）。使用第二掩模来图案化包括第三电极，第一钝化层，固定磁化层和第一电极的较大结构。第二介电钝化层（8）覆盖被蚀刻的多个层，第一层间介质层和第一互连金属化层。

9. 发明申请

WO2009079662A1 MAGNETIC TUNNEL JUNCTION DEVICE WITH SEPARATE READ AND WRITE PATHS 审中-公开
标题翻译：具有单独读取和写入功能的磁性隧道连接装置
公开(公告)号：WO2009079662A1
公开(公告)日：2009-06-25
申请号：PCT/US2008/087748
申请日：2008-12-19
申请人： QUALCOMM Incorporated , ZHU, Xiaochun , GU, Shiqun , LI, Xia , KANG, Seung H.
发明人： ZHU, Xiaochun , GU, Shiqun , LI, Xia , KANG, Seung H.
IPC分类号： G11C11/16
CPC分类号： G11C11/1675 , G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1673 , Y10S977/933 , Y10S977/935
摘要： In an embodiment, a device is disclosed that includes a magnetic tunnel junction (MTJ) structure. The device also includes a read path (102) coupled to the MTJ structure and a write path (104) coupled to the MTJ structure. The write path (104) is separate from the read path (102). The device in substance comprises a pair of serially coupled MTJ structures (106, 108), whereby the read path (102) comprises only one of the MTJ structure (108). This provides for combined improved read margin and improved write margin.
摘要翻译：在一个实施例中，公开了一种包括磁隧道结（MTJ）结构的装置。该设备还包括耦合到MTJ结构的读取路径（102）和耦合到MTJ结构的写入路径（104）。写入路径（104）与读取路径（102）分离。实质的装置包括一对串联耦合的MTJ结构（106,108），由此读路径（102）仅包括MTJ结构（108）中的一个。这提供了组合改进的读取余量和改进的写入余量。

10. 发明申请

WO2012061664A1 INTEGRATED CIRCUIT CHIP CUSTOMIZATION USING BACKSIDE ACCESS 审中-公开
标题翻译：集成电路芯片定制使用背面访问
公开(公告)号：WO2012061664A1
公开(公告)日：2012-05-10
申请号：PCT/US2011/059245
申请日：2011-11-04
申请人： QUALCOMM INCORPORATED , PERRY, Daniel, W. , GU, Shiqun, Sam
发明人： PERRY, Daniel, W. , GU, Shiqun, Sam
IPC分类号： H01L21/768 , H01L23/48 , H01L23/525 , G11C17/16 , G11C13/00 , G11C11/16
CPC分类号： H01L21/76898 , G11C11/16 , G11C13/0002 , G11C17/16 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit, a method for making an integrated circuit product, and methods for customizing an integrated circuit are disclosed. Integrated circuit elements including programmable elements, such as fuses, PROMs, RRAMs, MRAMs, or the like, are formed on the frontside of a substrate. Vias are formed through the substrate from its frontside to its backside to establish conduction paths to at least some of the programmable elements from the backside. A programming stimulus is applied to at least some of the vias from the backside to program at least some of the frontside programmable elements.
摘要翻译：公开了集成电路，制造集成电路产品的方法以及用于定制集成电路的方法。包括诸如保险丝，PROM，RRAM，MRAM等可编程元件的集成电路元件形成在衬底的前侧。通过从其前侧到其背面的衬底形成通孔，从背面建立至少一些可编程元件的传导路径。编程刺激被应用于来自背面的至少一些通孔以编程前端可编程元件中的至少一些。

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