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    • 5. 发明申请
    • FPGA ARCHITECTURE AT CONVENTIONAL AND SUBMICRON SCALES
    • 常规和亚微米尺寸的FPGA架构
    • WO2007089914A2
    • 2007-08-09
    • PCT/US2007002805
    • 2007-01-30
    • HEWLETT PACKARD DEVELOPMENT COSNIDER GREGORY SKUEKES PHILIP J
    • SNIDER GREGORY SKUEKES PHILIP J
    • H03K19/177G11C13/02
    • H03K19/17748B82Y10/00B82Y30/00G11C8/10G11C13/0007G11C13/0014G11C2213/15G11C2213/34G11C2213/51G11C2213/77G11C2213/81H03K19/17728H03K19/1778
    • Reconfigurable logic devices (500) and methods of programming the devices are disclosed. The logic device includes a look-up table (600, 600') (LUT) and at least one storage element (570) configured for sampling LUT output signals (520). The LUT (600, 600') comprises a plurality of input signals (510), an array of programmable impedance devices (110) operably coupled to the input signals (510), and the LUT output signals (520). Each programmable impedance devices (110) in the array includes a first electrode (120) operably coupled to one of the input signals (520), a second electrode (130) disposed to form a junction (150) wherein the second electrode (130) at least partially overlaps the first electrode (120), and a programmable material (140) disposed between the first electrode (120) and the second electrode (130). The programmable material (140) operably couples the first electrode (120) and second electrode (130) such that each programmable impedance device (110) exhibits a non-volatile programmable impedance. The array may be configured as a one-dimensional array (700, 700') or two-dimensional array (610, 610').
    • 公开了可重新配置的逻辑设备(500)和对设备进行编程的方法。 逻辑器件包括被配置为对LUT输出信号(520)进行采样的查找表(600,600')(LUT)和至少一个存储元件(570)。 LUT(600,600')包括多个输入信号(510),可操作地耦合到输入信号(510)的可编程阻抗设备(110)阵列以及LUT输出信号(520)。 阵列中的每个可编程阻抗器件(110)包括可操作地耦合到输入信号(520)中的一个的第一电极(120),布置为形成结(150)的第二电极(130),其中第二电极 至少部分地与第一电极(120)重叠,以及设置在第一电极(120)和第二电极(130)之间的可编程材料(140)。 可编程材料(140)可操作地耦合第一电极(120)和第二电极(130),使得每个可编程阻抗设备(110)呈现非易失性可编程阻抗。 该阵列可以被配置为一维阵列(700,700')或二维阵列(610,610')。