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1. 发明申请

WO2018164745A1 METHODS FOR THREE-DIMENSIONAL NONVOLATILE MEMORY 审中-公开
公开(公告)号：WO2018164745A1
公开(公告)日：2018-09-13
申请号：PCT/US2017/063724
申请日：2017-11-29
申请人： SANDISK TECHNOLOGIES LLC
发明人： WU, Ming-Che , KAMALANATHAN, Deepak , SAENZ, Juan , KUMAR, Tanmay
IPC分类号： H01L27/24 , G11C13/00 , H01L45/00 , H01L27/115
CPC分类号： H01L45/1608 , G11C7/18 , G11C8/14 , G11C13/0007 , G11C2213/35 , G11C2213/71 , H01L27/1052 , H01L27/115 , H01L27/2436 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/1206 , H01L45/1226 , H01L45/124 , H01L45/1253 , H01L45/146 , H01L45/16
摘要： A method is provided that includes forming a word line above a substrate, the word line disposed in a first direction, forming a bit line above the substrate, the bit line disposed in a second direction perpendicular to the first direction, forming a nonvolatile memory material between the word line and the bit line, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The word line includes a first portion and a second portion including an electrically conductive carbon-containing material. The nonvolatile memory material includes a semiconductor material layer and a conductive oxide material layer, with the semiconductor material layer disposed adjacent the second portion of the word line.

2. 发明申请

WO2017189088A1 MULTI-LAYER RESISTIVE MEMORY DEVICES 审中-公开
标题翻译：多层电阻存储器件
公开(公告)号：WO2017189088A1
公开(公告)日：2017-11-02
申请号：PCT/US2017/020076
申请日：2017-03-01
申请人： WESTERN DIGITAL TECHNOLOGIES INC.
发明人： BEDAU, Daniel
IPC分类号： G11C13/00
CPC分类号： H01L27/249 , G11C13/0007 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C2213/53 , G11C2213/71 , G11C2213/75 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/1206 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1608
摘要： To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a multi-layer resistive random access memory (ReRAM) array is provided. Active layers of the array each comprise a plurality of ReRAM elements that each include a gate portion having a gate terminal and a memory cell portion with a source terminal and drain terminal. Insulating layers of the array alternate with the active layers and each comprise an insulating material between adjacent active layers. Wordlines span through more than one layer of the array, with each of the wordlines comprising a column of memory cell portions coupled via source terminals and drain terminals of column-associated ReRAM elements. Bitlines each span through an associated active layer of the array, with each of the bitlines comprising a row of gate portions coupled via at least gate terminals of row-associated ReRAM elements.
摘要翻译：为了提供增强的数据存储设备和系统，本文提供了各种系统，体系结构，设备和方法。在第一个例子中，提供了一种多层电阻随机存取存储器（ReRAM）阵列。阵列的有源层各自包括多个ReRAM元件，每个ReRAM元件包括具有栅极端子的栅极部分和具有源极端子和漏极端子的存储器单元部分。阵列的绝缘层与有源层交替并且各自包括相邻有源层之间的绝缘材料。字线跨越阵列的多于一层，每个字线包括经由列关联的ReRAM元件的源极端子和漏极端子耦接的一列存储器单元部分。位线各自跨越阵列的相关有源层，每个位线包括至少经由行相关ReRAM元件的栅极端子耦合的一行栅极部分。

3. 发明申请

WO2017189083A1 NONVOLATILE SCHOTTKY BARRIER MEMORY TRANSISTOR 审中-公开
标题翻译：非易失性肖特基存储器晶体管
公开(公告)号：WO2017189083A1
公开(公告)日：2017-11-02
申请号：PCT/US2017/019168
申请日：2017-02-23
申请人： WESTERN DIGITAL TECHNOLOGIES, INC.
发明人： BEDAU, Daniel
IPC分类号： H01L27/24
CPC分类号： H01L27/2463 , G11C13/0007 , G11C2213/31 , G11C2213/32 , G11C2213/53 , H01L27/2454 , H01L45/04 , H01L45/1206 , H01L45/1226 , H01L45/1253 , H01L45/146 , H01L45/147
摘要： An apparatus for high density memory with integrated logic. Specifically, a three terminal resistive random access memory (ReRAM) device having Schottky barriers that can switch from a low resistive state to a high resistive state is provided. The Schottky transistor memory device includes an insulating layer, a source region disposed on the insulating layer, a drain region disposed on the insulating layer, a binary or complex oxide memory material, a gate dielectric layer, and a gate electrode. As voltage is applied the Schottky barrier breaks down leading to the formation of a conductive anodic filament (CAF). The CAF is non-volatile and short-circuits the reverse-biased barrier thus keeping the device in a low resistance state. Removing the CAF switches the device back to a high resistance state. Thus, a new type of semiconductor device advantageously combines computation and memory further providing for very high density NAND chains.
摘要翻译：
一种集成逻辑的高密度存储器。具体地，提供了具有可以从低电阻状态切换到高电阻状态的肖特基势垒的三端子电阻随机存取存储器（ReRAM）器件。肖特基晶体管存储器件包括绝缘层，设置在绝缘层上的源极区，设置在绝缘层上的漏极区，二元或复合氧化物存储材料，栅极电介质层和栅电极。施加电压时，肖特基势垒击穿导致形成导电阳极丝（CAF）。 CAF是非易失性的，并使反向偏置的屏障短路，从而使器件保持在低电阻状态。移除CAF会将设备切换回高电阻状态。因此，新型半导体器件有利地结合了进一步提供非常高密度NAND链的计算和存储器。

4. 发明申请

WO2017172071A1 CONTROLLING MEMORY CELL SIZE IN THREE DIMENSIONAL NONVOLATILE MEMORY 审中-公开
标题翻译：在三维非易失性存储器中控制存储器单元尺寸
公开(公告)号：WO2017172071A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/017626
申请日：2017-02-13
申请人： SANDISK TECHNOLOGIES LLC
发明人： MELIK-MARTIROSIAN, Ashot , SAENZ, Juan
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L27/249 , H01L21/02491 , H01L27/11521 , H01L27/2454 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1266 , H01L45/1273 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： A method is provided that includes forming a vertical bit line disposed in a first direction above a substrate, forming a multi-layer word line disposed in a second direction above the substrate, the second direction perpendicular to the first direction, and forming a memory cell including a nonvolatile memory material at an intersection of the vertical bit line and the multi-layer word line. The multi-layer word line includes a first conductive material layer and a second conductive material layer disposed above the first conductive material layer. The memory cell includes a working cell area encompassed by an intersection of the first conductive material layer and the nonvolatile memory material.
摘要翻译：提供了一种方法，该方法包括：在衬底上方形成设置在第一方向上的垂直位线，形成设置在衬底上方的第二方向上的多层字线，第二方向垂直于在垂直位线和多层字线的交叉处形成包括非易失性存储材料的存储单元。多层字线包括第一导电材料层和设置在第一导电材料层上方的第二导电材料层。存储器单元包括由第一导电材料层和非易失性存储器材料的交叉点包围的工作单元区域。

5. 发明申请

WO2017123498A1 MONOLITHIC THREE DIMENSIONAL MEMORY ARRAYS FORMED USING SACRIFICIAL POLYSILICON PILLARS 审中-公开
标题翻译：用牺牲多硅氧烷柱形成的单晶三维记忆阵列
公开(公告)号：WO2017123498A1
公开(公告)日：2017-07-20
申请号：PCT/US2017/012707
申请日：2017-01-09
申请人： SANDISK TECHNOLOGIES LLC
发明人： TAKAKI, Seje , MINE, Teruyuki
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L21/76877 , H01L21/28273 , H01L21/28282 , H01L21/283 , H01L27/115 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/16
摘要： A method is provided for forming a monolithic three-dimensional memory array. The method includes forming a first vertically-oriented polysilicon pillar above a substrate, the first vertically-oriented polysilicon pillar surrounded by a dielectric material, removing the first vertically-oriented polysilicon pillar to form a first void in the dielectric material, and filling the first void with a conductive material to form a first via.
摘要翻译：提供了一种用于形成单片三维存储器阵列的方法。该方法包括在衬底上方形成第一垂直取向多晶硅柱，第一垂直取向多晶硅柱被介电材料包围，移除第一垂直取向多晶硅柱以在介电材料中形成第一空隙，并且填充第一用导电材料形成第一通孔。

6. 发明申请

WO2017074580A1 RERAM MIM STRUCTURE FORMATION 审中-公开
标题翻译： RERAM MIM结构形成
公开(公告)号：WO2017074580A1
公开(公告)日：2017-05-04
申请号：PCT/US2016/051593
申请日：2016-09-14
申请人： SANDISK TECHNOLOGIES LLC
发明人： TANAKA, Yoichiro
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/2418 , H01L27/2454 , H01L27/2481 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/1683
摘要： Methods for improving the operation of a memory array by arranging a Metal-Insulator-Metal (MIM) structure between a word line and an adjustable resistance bit line structure are described. The MIM structure may correspond with a metal/ReRAM material/metal structure that is arranged between the word line and an intrinsic polysilicon region of the adjustable resistance bit line structure. In one example, a word line may be arranged adjacent to a ReRAM material that is adjacent to a first metal that is adjacent to the intrinsic polysilicon region. In another example, the word line may be arranged adjacent to a ReRAM material that is adjacent to a first metal that is adjacent to a second metal different from the first metal that is adjacent to the intrinsic polysilicon region.
摘要翻译：描述了通过在字线和可调电阻位线结构之间布置金属 - 绝缘体 - 金属（MIM）结构来改善存储器阵列的操作的方法。 MIM结构可以对应于布置在字线与可调电阻位线结构的本征多晶硅区域之间的金属/ ReRAM材料/金属结构。在一个示例中，字线可以被布置为与邻近于本征多晶硅区域的第一金属相邻的ReRAM材料。在另一个示例中，字线可以被布置为与邻近于与邻近于本征多晶硅区域的第一金属不同的第二金属的第一金属相邻的ReRAM材料相邻设置。

7. 发明申请

WO2016048327A1 RARE EARTH METAL & METAL OXIDE ELECTRODE INTERFACING OF OXIDE MEMORY ELEMENT IN RESISTIVE RANDOM ACCESS MEMORY CELL 审中-公开
标题翻译：稀土金属和金属氧化物电极在电阻随机访问存储器单元中的氧化物存储元件的接口
公开(公告)号：WO2016048327A1
公开(公告)日：2016-03-31
申请号：PCT/US2014/057470
申请日：2014-09-25
申请人： INTEL CORPORATION , MAJHI, Prashant , KARPOV, Elijah V. , MUKHERJEE, Niloy , PILLARISETTY, Ravi , SHAH, Uday , DOYLE, Brian S. , CHAU, Robert S.
发明人： MAJHI, Prashant , KARPOV, Elijah V. , MUKHERJEE, Niloy , PILLARISETTY, Ravi , SHAH, Uday , DOYLE, Brian S. , CHAU, Robert S.
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L45/146 , H01L45/08 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/16
摘要： Thin film resistive memory material stacks including at least one of a high work function metal oxide at an interface of a first electrode and a thin film memory material, and a low work function rare earth metal at an interface of a second electrode and the thin film memory material. The high work function metal oxide provides a good Schottky barrier height relative to memory material for high on/off current ratio. Compatibility of the metal oxide with switching oxide reduces cycling loss of oxygen/vacancies for improved memory device durability. The low work function rare earth metal provides high oxygen solubility to enhance vacancy creation within the memory material in as-deposited state for low forming voltage requirements while providing an ohmic contact to the resistive memory material.
摘要翻译：包括在第一电极和薄膜存储材料的界面处的高功函数金属氧化物中的至少一种和在第二电极和薄膜的界面处的低功函数稀土金属的薄膜电阻记忆材料堆叠记忆材料相对于记忆材料，高功函数金属氧化物提供了良好的肖特基势垒高度，用于高开/关电流比。金属氧化物与开关氧化物的相容性降低了氧/空位的循环损失，从而改善了存储器件的耐久性。低功函数稀土金属提供高氧溶解度，以在沉积状态下在存储材料中提供空位创建，用于低成形电压要求，同时向电阻式存储器材料提供欧姆接触。

8. 发明申请

WO2015186164A1 半導体記憶装置审中-公开
标题翻译：半导体存储设备
公开(公告)号：WO2015186164A1
公开(公告)日：2015-12-10
申请号：PCT/JP2014/064571
申请日：2014-06-02
申请人：株式会社日立製作所
发明人：黒土　健三 , 竹村　理一郎 , 笹子　佳孝
IPC分类号： H01L27/105 , H01L45/00
CPC分类号： H01L27/249 , H01L27/2454 , H01L27/2481 , H01L45/06 , H01L45/122 , H01L45/1226 , H01L45/1253 , H01L45/144
摘要：　半導体基板と、第１記憶部と、前記半導体基板と平行な第１の方向に形成された複数の前記第１記憶部からなる第２記憶部と、前記第１の方向と直交し、かつ、前記半導体基板と平行な第２の方向に形成された複数の前記第２記憶部からなる第３記憶部と、前記半導体基板と直交する第３の方向に複数の前記第３記憶部からなる第４記憶部とを備え、前記第２の方向のアドレスを選択する信号線と前記半導体基板を接続する複数のコンタクトを前記第１の方向に延伸されたビット線に干渉しない領域に配置することにより信頼性が高く、また、大容量かつ高速にリード、ライトできる低コストで製造可能な半導体記憶装置を実現することができる。
摘要翻译：半导体存储装置包括：半导体基板; 第一存储单元; 第二存储单元，由平行于半导体基板的第一方向形成的多个第一存储单元构成; 第三存储单元，由沿与第一方向正交的第二方向形成并平行于半导体基板的多个第二存储单元构成; 以及第四存储单元，其由与所述半导体基板正交的第三方向的多个第三存储单元构成，其中，连接用于选择第二方向的地址的信号线和所述半导体基板的多个触点配置在区域不妨碍沿第一方向延伸的位线，从而提供高可靠性的大容量半导体存储装置，其能够以高速读取和写入，并且可以以低成本制造。

9. 发明申请

WO2015148299A1 TRANSISTOR DEVICE WITH GATE BOTTOM ISOLATION AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：具有门底分离的晶体管器件及其制造方法
公开(公告)号：WO2015148299A1
公开(公告)日：2015-10-01
申请号：PCT/US2015/021720
申请日：2015-03-20
申请人： SANDISK 3D LLC
发明人： TAKAKI, Seje
IPC分类号： H01L27/115 , H01L27/10 , G11C13/00 , H01L27/24
CPC分类号： H01L27/11524 , G11C13/0002 , G11C2213/71 , G11C2213/77 , G11C2213/78 , G11C2213/79 , H01L27/101 , H01L27/11556 , H01L27/11582 , H01L27/2454 , H01L27/249 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/16
摘要： An embodiment relates to a transistor device including a pillar of semiconductor material extending vertically from a bottom portion in contact with an electrically conductive contact line, where the electrically conductive contact line extends laterally past the pillar in a horizontal direction, a gate insulating liner layer on a lateral side of the pillar, a gate electrode on the gate insulating layer extending along the lateral side of the pillar, and a region of electrically insulating semiconductor oxide material filling a space between a bottom portion of the gate electrode and a top portion of the electrically conductive contact line.
摘要翻译：一个实施例涉及一种晶体管器件，其包括半导体材料柱，其从与导电接触线接触的底部垂直延伸，其中导电接触线在水平方向上横向延伸穿过柱，栅绝缘衬垫层所述柱的横向侧，所述栅极绝缘层上沿着所述柱的横向侧延伸的栅电极以及填充所述栅电极的底部与所述栅电极的顶部之间的空间的电绝缘半导体氧化物材料的区域导电接触线。

10. 发明申请

WO2015147801A1 TECHNIQUES FOR FORMING NON-PLANAR RESISTIVE MEMORY CELLS 审中-公开
标题翻译：形成非平面电阻记忆细胞的技术
公开(公告)号：WO2015147801A1
公开(公告)日：2015-10-01
申请号：PCT/US2014031735
申请日：2014-03-25
申请人： INTEL CORPORATON , MAJHI PRASHANT , KARPOV ELIJAH V , SHAH UDAY , MUKHERJEE NILOY , KUO CHARLES C , PILLARISETTY RAVI , DOYLE BRIAN S , CHAU ROBERT S
发明人： MAJHI PRASHANT , KARPOV ELIJAH V , SHAH UDAY , MUKHERJEE NILOY , KUO CHARLES C , PILLARISETTY RAVI , DOYLE BRIAN S , CHAU ROBERT S
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L45/08 , H01L27/2409 , H01L27/2436 , H01L45/1226 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1683
摘要： Techniques are disclosed for forming non-planar resistive memory cells, such as non-planar resistive random-access memory (ReRAM or RRAM) cells. The techniques can be used to reduce forming voltage requirements and/or resistances involved (such as the resistance during the low-resistance state) relative to planar resistive memory cells for a given memory cell space. The non-planar resistive memory cell includes a first electrode, a second electrode, and a switching layer disposed between the first and second electrodes. The second electrode may be substantially between opposing portions of the switching layer, and the first electrode may be substantially adjacent to at least two sides of the switching layer, after the non-planar resistive memory cell is formed. In some cases, an oxygen exchange layer (OEL) may be disposed between the switching layer and one of the first and second electrodes to, for example, increase flexibility in incorporating materials in the cell.
摘要翻译：公开了用于形成诸如非平面电阻随机存取存储器（ReRAM或RRAM）单元的非平面电阻存储器单元的技术。该技术可用于相对于给定存储器单元空间的平面电阻存储器单元来减少所涉及的形成电压要求和/或电阻（例如在低电阻状态期间的电阻）。非平面电阻式存储单元包括第一电极，第二电极和设置在第一和第二电极之间的开关层。第二电极可以基本上在开关层的相对部分之间，并且在形成非平面电阻式存储单元之后，第一电极可以基本上与开关层的至少两侧相邻。在一些情况下，氧交换层（OEL）可以设置在开关层与第一和第二电极中的一个之间，以例如增加在电池中引入材料的灵活性。

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