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1. 发明申请

WO2019133243A1 DRIFT MITIGATION WITH EMBEDDED REFRESH 审中-公开
公开(公告)号：WO2019133243A1
公开(公告)日：2019-07-04
申请号：PCT/US2018/064928
申请日：2018-12-11
申请人： MICRON TECHNOLOGY, INC.
发明人： TORTORELLI, Innocenzo , PIROVANO, Agostino , REDAELLI, Andrea , PELLIZZER, Fabio , WANG, Hongmei
IPC分类号： G11C13/00
CPC分类号： G11C29/00 , G11C13/00 , G11C13/0004 , G11C13/0033 , G11C13/004 , G11C29/52 , G11C2013/0052 , G11C2213/71 , H01L27/2409 , H01L27/2427 , H01L27/2463 , H01L27/2481 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/142 , H01L45/143 , H01L45/144
摘要： Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage-a setback voltage-of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.

2. 发明申请

WO2019066849A1 A RESISTIVE RANDOM ACCESS MEMORY DEVICE WITH SWITCHING MULTI-LAYER STACK AND METHODS OF FABRICATION 审中-公开
公开(公告)号：WO2019066849A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/053970
申请日：2017-09-28
申请人： INTEL CORPORATION
发明人： GLASSMAN, Timothy , SEGHETE, Dragos , STRUTT, Nathan , ASURI, Namrata S. , GOLONZKA, Oleg , KOTHARI, Hiten , ANDRUS, Matthew J.
IPC分类号： H01L45/00
CPC分类号： H01L45/08 , H01L27/2436 , H01L45/1233 , H01L45/1266 , H01L45/146 , H01L45/1675
摘要： A memory device includes a bottom electrode above a substrate, a first switching layer on the bottom electrode, a second switching layer including aluminum on the first switching layer, an oxygen exchange layer on the second switching layer and a top electrode on the oxygen exchange layer. The presence of the second switching layer including aluminum on the first switching layer enables a reduction in electro-forming voltage of the memory device.

3. 发明申请

WO2019059892A1 METALLIC GLASS BARRIERS FOR ELECTRODES AND CONTACTS IN SEMICONDUCTOR DEVICES 审中-公开
公开(公告)号：WO2019059892A1
公开(公告)日：2019-03-28
申请号：PCT/US2017/052261
申请日：2017-09-19
申请人： INTEL CORPORATION
发明人： KARPOV, Elijiah, V. , JEZEWSKI, Christopher, J. , KOBRINSKY, Mauro, J. , YOO, Hui, Jae , PILLARISETTY, Ravi
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L45/08 , H01L27/2436 , H01L45/1233 , H01L45/1253 , H01L45/146
摘要： Disclosed are electronic devices, memory devices, and computing devices including a metallic glass barrier material for an electrode or a contact. An electronic device (100) includes a semiconductor substrate (110), an electrical component (120) formed on or in the semiconductor substrate, an electrically conductive material (130) on or in the electrical component and configured to conduct electrical charge at least one of to or from the electrical component, and a barrier material (132) including a metallic glass material in contact with the electrically conductive material. A memory device includes a memory cell including a metallic glass barrier material. A computing device includes an electronic device including a metallic glass barrier material.

4. 发明申请

WO2018100341A1 A CEM SWITCHING DEVICE 审中-公开
公开(公告)号：WO2018100341A1
公开(公告)日：2018-06-07
申请号：PCT/GB2017/053521
申请日：2017-11-23
申请人： ARM LTD
发明人： ARAUJO, Carlos Alberto Paz de , CELINSKA, Jolanta Bozena , REID, Kimberly Gay , SHIFREN, Lucian
IPC分类号： H01L45/00
CPC分类号： H01L45/146 , C23C14/0036 , C23C14/165 , C23C16/45525 , C23C16/50 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/16 , H01L45/1608
摘要： The present techniques generally relate to an improved CEM switching device (350) and methods for its manufacture. In this device, a conductive substrate (370) and/or conductive overlay (380) each comprises a primary layer (370a, 380a) of a conductive material and a secondary layer (370b, 380b) of a conductive material. The primary layer (370a, 380a) contacting the CEM layer (360) is substantially inert to the CEM layer and/or acts an oxygen barrier for the secondary layer at temperatures used for the manufacture of the device.

5. 发明申请

WO2018006131A1 MULTIFUNCTIONAL AND MULTI-BIT RESISTIVE STORAGE MEMORIES 审中-公开
标题翻译：多功能和多位电阻存储器
公开(公告)号：WO2018006131A1
公开(公告)日：2018-01-11
申请号：PCT/AU2017/050699
申请日：2017-07-06
申请人： RMIT UNIVERSITY
发明人： SRIRAM, Sharath , AHMED, Taimur , WALIA, Sumeet , BHASKARAN, Madhu
IPC分类号： H01L45/00 , H01L27/24 , G11C11/56
CPC分类号： G11C13/0069 , G11C11/5685 , G11C2013/0073 , G11C2013/0083 , G11C2013/009 , G11C2213/15 , G11C2213/31 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625
摘要： A memristor device is provided, comprising a first electrode; a second electrode; a cathode metal layer disposed on a surface of the first electrode; and an active region disposed between and in electrical contact with the second electrode and the cathode metal layer, the active region comprising at least one layer of an amorphous metal oxide, wherein the amorphous metal oxide comprises doping atoms of a dopant element selected from the group consisting of aluminium, nickel, iron and chromium, and wherein when a switching voltage is applied between the first and second electrodes, the active region exhibits a resistive switching behaviour. Also provided is a method of fabricating such a memristor device.
摘要翻译：提供了一种忆阻器装置，其包括第一电极; 第二电极; 设置在所述第一电极的表面上的阴极金属层; 以及设置在第二电极和阴极金属层之间并与第二电极和阴极金属层电接触的有源区，有源区包括至少一层非晶金属氧化物，由铝，镍，铁和铬组成，并且其中当在第一和第二电极之间施加开关电压时，有源区呈现出电阻切换行为。还提供了制造这种忆阻器器件的方法。

6. 发明申请

WO2018004625A1 CONDUCTIVE BRIDGE RANDOM ACCESS MEMORY (CBRAM) DEVICES WITH ENGINEERED SIDEWALLS FOR FILAMENT LOCALIZATION 审中-公开
标题翻译：导电桥随机访问存储器（CBRAM）器件，带有工程设计的侧壁用于光纤本地化
公开(公告)号：WO2018004625A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040551
申请日：2016-06-30
申请人： INTEL CORPORATION
发明人： MAJHI, Prashant , KARPOV, Elijah V. , SHAH, Uday , PILLARISETTY, Ravi , MUKHERJEE, Niloy , BIELEFELD, Jeffery D. , INDUKURI, Tejaswi K. , CLARKE, James S.
IPC分类号： H01L45/00
CPC分类号： H01L45/00 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/16
摘要： Approaches for fabricating conductive bridge random access memory (CBRAM) devices with engineered sidewalls for filament localization, and the resulting structures and devices, are described. In an example, a conductive bridge random access memory (CBRAM) device includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate. The CBRAM device also includes a CBRAM element disposed on the conductive interconnect. The CBRAM element includes a first electrode layer disposed on the uppermost surface of the conductive interconnect. A resistance switching layer is disposed on the first electrode layer. The resistance switching layer includes an electrolyte material having doped regions at outermost ends of the electrolyte material but not in a central portion of the electrolyte material. A metal ion source layer is disposed on the resistance switching layer. A second electrode layer is disposed on the metal ion source layer.
摘要翻译：描述了用于制造具有用于灯丝定位的工程侧壁的导电桥随机存取存储器（CBRAM）器件以及所得到的结构和器件的方法。在一个示例中，导电桥随机存取存储器（CBRAM）器件包括设置在设置在衬底上方的层间电介质（ILD）层中的导电互连。 CBRAM器件还包括布置在导电互连上的CBRAM元件。 CBRAM元件包括设置在导电互连的最上表面上的第一电极层。电阻切换层设置在第一电极层上。电阻切换层包括电解质材料，该电解质材料在电解质材料的最外端具有掺杂区域，但不在电解质材料的中心部分。金属离子源层设置在电阻切换层上。第二电极层设置在金属离子源层上。

7. 发明申请

WO2017189088A1 MULTI-LAYER RESISTIVE MEMORY DEVICES 审中-公开
标题翻译：多层电阻存储器件
公开(公告)号：WO2017189088A1
公开(公告)日：2017-11-02
申请号：PCT/US2017/020076
申请日：2017-03-01
申请人： WESTERN DIGITAL TECHNOLOGIES INC.
发明人： BEDAU, Daniel
IPC分类号： G11C13/00
CPC分类号： H01L27/249 , G11C13/0007 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C2213/53 , G11C2213/71 , G11C2213/75 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/1206 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1608
摘要： To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a multi-layer resistive random access memory (ReRAM) array is provided. Active layers of the array each comprise a plurality of ReRAM elements that each include a gate portion having a gate terminal and a memory cell portion with a source terminal and drain terminal. Insulating layers of the array alternate with the active layers and each comprise an insulating material between adjacent active layers. Wordlines span through more than one layer of the array, with each of the wordlines comprising a column of memory cell portions coupled via source terminals and drain terminals of column-associated ReRAM elements. Bitlines each span through an associated active layer of the array, with each of the bitlines comprising a row of gate portions coupled via at least gate terminals of row-associated ReRAM elements.
摘要翻译：为了提供增强的数据存储设备和系统，本文提供了各种系统，体系结构，设备和方法。在第一个例子中，提供了一种多层电阻随机存取存储器（ReRAM）阵列。阵列的有源层各自包括多个ReRAM元件，每个ReRAM元件包括具有栅极端子的栅极部分和具有源极端子和漏极端子的存储器单元部分。阵列的绝缘层与有源层交替并且各自包括相邻有源层之间的绝缘材料。字线跨越阵列的多于一层，每个字线包括经由列关联的ReRAM元件的源极端子和漏极端子耦接的一列存储器单元部分。位线各自跨越阵列的相关有源层，每个位线包括至少经由行相关ReRAM元件的栅极端子耦合的一行栅极部分。

8. 发明申请

WO2017181418A1 一种Cu基阻变存储器的制备方法及存储器审中-公开
公开(公告)号：WO2017181418A1
公开(公告)日：2017-10-26
申请号：PCT/CN2016/080022
申请日：2016-04-22
申请人：中国科学院微电子研究所
发明人：吕杭炳 , 刘明 , 刘琦 , 龙世兵
IPC分类号： H01L45/00
CPC分类号： H01L45/1266 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1273 , H01L45/142 , H01L45/144 , H01L45/16 , H01L45/1683
摘要：一种Cu基阻变存储器的制备方法及存储器，该制备方法包括：对铜下电极（10）构图化合处理生成化合物缓冲层（40），所述化合物缓冲层（40）能够阻止所述铜下电极（10）被氧化；在所述化合物缓冲层（40）上沉积固态电解液材料（50）；在所述固态电解液材料（50）上沉积上电极（60）形成存储器。在上述技术方案中，通过在铜下电极（10）与固态电解液材料（50）之间插入能够阻止铜下电极（10）被氧化的化合物缓冲层（40），以有效避免固态电解液材料（50）生长时对铜下电极（10）的氧化，使电极界面不会因为氧化而变粗糙，从而解决现有技术中Cu基阻变存储器因电极界面粗糙导致的器件可靠性和良率较低的技术问题，进而提高器件的可靠性和良率。

9. 发明申请

WO2017172071A1 CONTROLLING MEMORY CELL SIZE IN THREE DIMENSIONAL NONVOLATILE MEMORY 审中-公开
标题翻译：在三维非易失性存储器中控制存储器单元尺寸
公开(公告)号：WO2017172071A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/017626
申请日：2017-02-13
申请人： SANDISK TECHNOLOGIES LLC
发明人： MELIK-MARTIROSIAN, Ashot , SAENZ, Juan
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L27/249 , H01L21/02491 , H01L27/11521 , H01L27/2454 , H01L45/04 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1266 , H01L45/1273 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： A method is provided that includes forming a vertical bit line disposed in a first direction above a substrate, forming a multi-layer word line disposed in a second direction above the substrate, the second direction perpendicular to the first direction, and forming a memory cell including a nonvolatile memory material at an intersection of the vertical bit line and the multi-layer word line. The multi-layer word line includes a first conductive material layer and a second conductive material layer disposed above the first conductive material layer. The memory cell includes a working cell area encompassed by an intersection of the first conductive material layer and the nonvolatile memory material.
摘要翻译：提供了一种方法，该方法包括：在衬底上方形成设置在第一方向上的垂直位线，形成设置在衬底上方的第二方向上的多层字线，第二方向垂直于在垂直位线和多层字线的交叉处形成包括非易失性存储材料的存储单元。多层字线包括第一导电材料层和设置在第一导电材料层上方的第二导电材料层。存储器单元包括由第一导电材料层和非易失性存储器材料的交叉点包围的工作单元区域。

10. 发明申请

WO2017141043A1 FABRICATION OF CORRELATED ELECTRON MATERIAL DEVICES METHOD TO CONTROL CARBON 审中-公开
标题翻译：相关电子材料器件控制碳的方法的研究
公开(公告)号：WO2017141043A1
公开(公告)日：2017-08-24
申请号：PCT/GB2017/050415
申请日：2017-02-17
申请人： ARM LTD
发明人： REID, Kimberly Gay , SHIFREN, Lucian
IPC分类号： H01L45/00 , C23C16/18
CPC分类号： H01L49/003 , C23C16/406 , C23C16/45527 , C23C16/45553 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L45/1641
摘要： The present techniques generally relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, precursors, in a gaseous form, may be utilized in a chamber to build a film of correlated electron materials comprising various impedance characteristics.
摘要翻译：本技术一般涉及例如用于执行切换功能的相关电子材料的制造。在实施例中，气体形式的前体可用于室中以构建包含各种阻抗特性的相关电子材料的膜。

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