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1. 发明申请

WO2023079863A1 半導体記憶装置审中-公开
公开(公告)号：WO2023079863A1
公开(公告)日：2023-05-11
申请号：PCT/JP2022/036022
申请日：2022-09-27
申请人：ソニーセミコンダクタソリューションズ株式会社
发明人：成竹　功夫 , 石川　展之 , 木下　善彦 , 本村　哲夫 , 池田　一文 , 尾白　吏 , 島田　智子 , 永松　健一 , 渡邉　浩二
IPC分类号： G11C7/14 , G11C17/16 , G11C17/18
摘要：［課題］読み出し動作をより適切に行う。［解決手段］半導体記憶装置は、第１電圧を供給する第１電圧供給線と、前記第１電圧とは異なる第２電圧を供給する第２電圧供給線と、の間に並列に接続される１つ以上の第１メモリセルと、前記第２電圧供給線と、前記第１電圧を供給する第３電圧供給線と、の間に並列に接続される１つ以上の第２メモリセルと、を備え、前記第１メモリセルのそれぞれは、第１状態又は第２状態に応じた抵抗値を有する第１記憶素子と、前記第１記憶素子と前記第１電圧供給線との間に接続される第１セルトランジスタと、を有し、前記第２メモリセルのそれぞれは、第１状態又は第２状態に応じた抵抗値を有する第２記憶素子と、前記第２記憶素子と前記第３電圧供給線との間に接続される第２セルトランジスタと、を有する。

2. 发明申请

WO2022183649A1 熔丝故障修复电路审中-公开
公开(公告)号：WO2022183649A1
公开(公告)日：2022-09-09
申请号：PCT/CN2021/105069
申请日：2021-07-07
申请人：长鑫存储技术有限公司
发明人：王科竣
IPC分类号： G11C17/16
摘要：本申请提供一种熔丝故障修复电路，包括熔丝阵列、信号存储模块和扫描修复模块。熔丝阵列包括冗余熔丝阵列和非冗余熔丝阵列，熔丝阵列无故障时冗余熔丝阵列无信号输出，非冗余熔丝阵列输出S个第一逻辑信号。信号存储模块中每个存储单元用于存储一个连接的熔丝单元发送的第一逻辑信号。扫描修复模块用于扫描信号存储模块中的存储单元，并在扫描到故障存储单元时，确定故障存储单元连接的第一熔丝单元发生故障，将第一熔丝单元替换为与第一熔丝单元对应的第一冗余熔丝单元。其中第一冗余熔丝单元属于冗余熔丝阵列，第一冗余熔丝单元对应的第一逻辑信号为正常信号。本申请可以对故障的熔丝阵列进行修复，以提高电子熔丝半导体存储器的利用率。

3. 发明申请

WO2022059176A1 半導体装置审中-公开
公开(公告)号：WO2022059176A1
公开(公告)日：2022-03-24
申请号：PCT/JP2020/035503
申请日：2020-09-18
申请人：タワー　パートナーズ　セミコンダクター株式会社 , タワー　セミコンダクター　リミテッド
发明人：平野　博茂 , 栗山　寛明 , 坂上　雅彦 , グットマン　ミカ , サリグ　エレズ , ロイジン　ヤコフ
IPC分类号： G11C17/16 , G11C17/18
摘要：半導体装置は、電気的に１回限りの書き込みが可能に構成され、２値を記憶する記憶素子（１）と、第１ノード信号（Ｎ１）を介して記憶素子（１）に接続され、記憶素子（１）への書き込みを指示する書き込み制御信号（ＣＴ１）に基づいて記憶素子（１）への書き込みをする書き込み制御部（２）と、第１ノード信号（Ｎ１）を測定して得られた測定信号から記憶素子（１）が書き込み状態であることを検知する書き込み状態検知回路（５）とを有する記憶素子書き込みユニット（１０）を備える。書き込み制御部（２）は、記憶素子（１）への書き込みを開始した後に、書き込み状態検知回路（５）から記憶素子（１）が書き込み状態であることを示す検知信号を受けた場合に、記憶素子（１）が書き込み状態であることが検知されてから一定期間の経過後に書き込み動作を停止する。

4. 发明申请

WO2022042836A1 VERIFIABLE ONE-TIME PROGRAMMABLE MEMORY DEVICE 审中-公开
公开(公告)号：WO2022042836A1
公开(公告)日：2022-03-03
申请号：PCT/EP2020/073889
申请日：2020-08-26
申请人： TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
发明人： LINDSKOG, Niklas , ENGLUND, Håkan
IPC分类号： G11C11/00 , G11C17/14 , G11C17/16 , G11C17/18 , G11C8/12
摘要： There is provided a verifiable OTP memory device, the memory device comprising an MTP memory block and an OTP memory block for storing data, and a memory controller. The memory controller is configured to handle write requests and read requests. Each write request and read request pertains to writing data to, and reading data from, respectively, a requested position in either the MTP memory block or the OTP memory block. The memory controller is configured to, in response to the write requests, write the data to the requested position in either the MTP memory block or the OTP memory block. The memory controller is configured to, in response to the read requests, output data as combined from the requested position in the MTP memory block and the requested position in the OTP memory block, regardless if the read requests are for the MTP memory block or the OTP memory block.

5. 发明申请

WO2022031349A1 THREE-DIMENSIONAL NOR-NAND COMBINATION MEMORY DEVICE AND METHOD OF MAKING THE SAME 审中-公开
公开(公告)号：WO2022031349A1
公开(公告)日：2022-02-10
申请号：PCT/US2021/034643
申请日：2021-05-27
申请人： SANDISK TECHNOLOGIES LLC
发明人： CUI, Zhixin , CHIBVONGODZE, Hardwell , GAUTAM, Rajdeep
IPC分类号： G11C16/10 , G11C11/22 , G11C16/04 , G11C16/26 , G11C17/16 , G11C17/18 , H01L23/522 , G11C11/005 , G11C11/223 , G11C11/2273 , G11C11/2275 , G11C16/0408 , G11C16/0466 , G11C2216/26 , H01L23/5226 , H01L27/11206 , H01L27/11519 , H01L27/11521 , H01L27/11556 , H01L27/11565 , H01L27/11568 , H01L27/11582 , H01L27/11587 , H01L27/1159 , H01L27/11597
摘要： First alternating stacks of first insulating strips and first spacer material strips is formed in a first device region, second alternating stacks of second insulating strips and second spacer material strips are formed in a second device region. Each of the first line trenches is filled with a respective laterally alternating sequence of memory stack structures and first dielectric pillar structures to form a three-dimensional NAND memory. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements. Each of the second line trenches with a respective laterally alternating sequence of active region assemblies of lateral field effect transistors and second dielectric pillar structures to form a three-dimensional NOR memory. Each of the active region assemblies includes a source pillar, a drain pillar, and a tubular channel region. The spacer material strips include, or are subsequently replaced with, electrically conductive strips.

6. 发明申请

WO2021247331A1 APPARATUSES, SYSTEMS, AND METHODS FOR FUSE ARRAY BASED DEVICE IDENTIFICATION 审中-公开
公开(公告)号：WO2021247331A1
公开(公告)日：2021-12-09
申请号：PCT/US2021/034335
申请日：2021-05-26
申请人： MICRON TECHNOLOGY, INC.
发明人： MORISHITA, Yoshihito , KONDO, Chikara
IPC分类号： G06F21/73 , G06F21/72 , G06F21/78 , H04L9/06 , G11C11/4078 , G11C11/4085 , G11C16/20 , G11C17/16 , G11C29/027 , H04L9/0643
摘要： Apparatuses, systems, and methods for fuse based device identification. A device may include a number of fuses which are used to encode permanent information on the device. The device may receive an identification request, and may generate an identification number based on the states of at least a portion of the fuses. For example, the device may include a hash generator, which may generate the identification number by using the fuse information as a seed for a hash algorithm.

7. 发明申请

WO2020154647A1 APPARATUSES AND METHODS FOR SOFT POST/PACKAGE REPAIR 审中-公开
公开(公告)号：WO2020154647A1
公开(公告)日：2020-07-30
申请号：PCT/US2020/015031
申请日：2020-01-24
申请人： MICRON TECHNOLOGY, INC.
发明人： WILSON, Alan J.
IPC分类号： G11C29/00 , G11C17/16 , G11C17/18
摘要： Embodiments of the disclosure are drawn to apparatuses and methods for soft post-package repair (SPPR). After packaging, it may be necessary to perform post-package repair operations on rows of the memory. During a scan mode of an SPPR operation, addresses provided by a fuse bank may be examined to determine if they are open addresses or if the bad row of memory is a redundant row of memory. The open addresses and the bad redundant addresses may be stored in volatile storage elements, such as in latch circuits. During a soft send mode of a SPPR operation, the address previously associated with the bad row of memory may be associated with the open address instead, and the address of the bad redundant row may be disabled.

8. 发明申请

WO2020028291A1 POWER TRANSISTOR COUPLED TO MULTIPLE SENSE TRANSISTORS 审中-公开
公开(公告)号：WO2020028291A1
公开(公告)日：2020-02-06
申请号：PCT/US2019/044024
申请日：2019-07-30
申请人： THE INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： JOARDAR, Kuntal , CHU, Min , KRISHNAMURTHY, Vijay , HARJONO, Tikno , CHAUHAN, Ankur , HEGDE, Vinayak , SRIVASTAVA, Manish
IPC分类号： H01L25/00 , G01R19/00 , G11C17/16 , G11C17/18 , H01L23/5256 , H01L27/11206
摘要： An electronic device comprises a first semiconductor die (102); a power transistor (104) integrated in the first semiconductor die, the power transistor comprising a first gate (104g), a first terminal (104s), and a second terminal (104d); a first sense transistor (106) integrated in the first semiconductor die, the first sense transistor comprising a second gate (106g) and third (106s) and fourth terminals (106d), the second gate coupled to the first gate and the fourth terminal coupled to the second terminal; a first resistor (106R) having a first temperature coefficient; a second sense transistor (108) integrated in the first semiconductor die, the second sense transistor comprising a third gate (108g) and seventh (l08s) and eighth (108d) terminals, the third gate coupled to the first gate and the eighth terminal coupled to the second terminal; and a second resistor (108R) having a second temperature coefficient.

9. 发明申请

WO2018044755A1 FUSE STATE SENSING CIRCUITS, DEVICES AND METHODS 审中-公开
标题翻译：保险丝状态检测电路，装置和方法
公开(公告)号：WO2018044755A1
公开(公告)日：2018-03-08
申请号：PCT/US2017/048810
申请日：2017-08-28
申请人： SKYWORKS SOLUTIONS, INC.
发明人： YAN, Yan , CHOI, Yunyoung , LEE, Junhyung
IPC分类号： G11C17/16 , G11C17/18 , G11C7/06
摘要： Fuse state sensing circuits, devices and methods. In some embodiments, a fuse state sensing circuit can include an enable block configured to enable a flow of a fuse current resulting from a supply voltage to a fuse element upon receipt of an enable signal substantially at the same time as when the supply voltage is applied. The fuse state sensing circuit can further include a current control block tailored to control an amount of the fuse current. The fuse state sensing circuit can further include a decision block implemented to generate an output representative of a state of the fuse element based on the fuse current, with the output being generated during a ramp-up portion of the application of the supply voltage.
摘要翻译：保险丝状态检测电路，装置和方法。在一些实施例中，熔丝状态感测电路可以包括启用块，该启用块被配置为基本上在施加电源电压的同时接收到启用信号时启用从电源电压产生的熔丝电流到熔丝元件的流动。熔丝状态感测电路可以进一步包括适合于控制熔丝电流量的电流控制块。熔丝状态感测电路还可以包括判定块，该判定块被实现为基于熔丝电流产生表示熔丝元件的状态的输出，其中输出在施加电源电压的斜升部分期间产生。 / p>

10. 发明申请

WO2017171865A1 INTEGRATED CIRCUIT DEVICE USING MULTIPLE ONE-TIME PROGRAMMABLE BITS TO CONTROL ACCESS TO A RESOURCE 审中-公开
标题翻译：集成电路设备使用多个一次性可编程位来控制对资源的访问
公开(公告)号：WO2017171865A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/025691
申请日：2016-04-01
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
发明人： MCWILLIAMS, John L.
IPC分类号： G11C17/00 , G11C17/16
摘要： An integrated circuit device that utilizes multiple OTP bits to enable and re-enable access to evaluation and testing components comprises a set of multiple one-time programmable (OTP) bits, a programming module operable to trigger a change in each bit of the set of multiple OTP bits, decode logic to determine a value for a collective state of the set of multiple OTP bits, and a control element to control access to at least one resource of the integrated circuit device based on a value of the collective state for the set of multiple OTP bits.
摘要翻译：利用多个OTP位来启用和重新启用对评估和测试组件的访问的集成电路装置包括一组多个一次可编程（OTP）位，编程模块，其可操作以触发在所述一组多个OTP位的每一位中改变，解码逻辑以确定所述一组多个OTP位的集体状态的值，以及控制元件，用于基于所述集合电路装置的至少一个资源来控制对所述集成电路装置的至少一个资源的访问一组多个OTP位的集合状态值。

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