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1. 发明申请

WO2011062714A2 INTEGRATED MEMORY ARRAYS, AND METHODS OF FORMING MEMORY ARRAYS 审中-公开
标题翻译：集成存储器阵列和形成存储器阵列的方法
公开(公告)号：WO2011062714A2
公开(公告)日：2011-05-26
申请号：PCT/US2010052918
申请日：2010-10-15
申请人： MICRON TECHNOLOGY INC , TANG SANH D , FUCSKO JANOS
发明人： TANG SANH D , FUCSKO JANOS
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L21/768 , H01L27/112 , H01L27/11206 , H01L27/228 , H01L27/24
摘要： Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry.
摘要翻译：一些实施例包括形成存储器阵列的方法。一叠半导体材料板可以被图案化以将这些板细分为多个片。导电层可沿着部件的侧壁边缘形成。然后可以将这些部件图案化成一个导线阵列，该阵列具有垂直列和水平行。单独的导线可以具有连接到导电层的第一端，可以具有与第一端相对的第二端，并且可以在第一端和第二端之间具有中间区域。栅极材料可以沿着中间区域形成。存储器单元结构可以形成在导线的第二端。多个垂直延伸的电互连可以通过存储单元结构连接到导线，其中各个垂直延伸的电互连沿阵列的各个列。一些实施例包括并入集成电路的存储器阵列。

2. 发明申请

WO2011036770A1 メモリ機能付きパストランジスタ回路およびこのパストランジスタ回路を有するスイッチングボックス回路审中-公开
标题翻译：具有存储功能的通用晶体管电路，以及提供有通用晶体管电路的开关盒电路
公开(公告)号：WO2011036770A1
公开(公告)日：2011-03-31
申请号：PCT/JP2009/066678
申请日：2009-09-25
申请人：株式会社東芝 , 杉山英行 , 棚本哲史 , 丸亀孝生 , 石川瑞恵 , 井口智明 , 斉藤好昭
发明人：杉山　英行 , 棚本　哲史 , 丸亀　孝生 , 石川　瑞恵 , 井口　智明 , 斉藤　好昭
IPC分类号： H01L29/82 , H01L21/8234 , H01L21/8246 , H01L27/088 , H01L27/105 , H01L43/08
CPC分类号： H01L27/112 , H03K19/17736
摘要：［課題］高集積化および低消費電力化が可能なパストランジスタ回路を提供する。［解決手段］第１の信号線に接続される第１の入出力端子２４と、第２の信号線に接続される第２の入出力端子２６と、一端が第１の電源に接続される第１の素子１０ａと、第１の素子の他端に一端が接続され、他端が第２の電源に接続される第２の素子１０ｂと、第１の素子の他端にソースが接続され、ゲートに第１の制御信号を受ける第１のトランジスタ１０ｃと、第１のトランジスタのドレインにゲートが接続され、第１の入出力端子にソースが接続され、第２の入出力端子にドレインが接続された第２のトランジスタ１０ｄと、を備え、第１および第２の素子のうちの少なくとも一方が不揮発性メモリ素子であり、他方がＭＯＳＦＥＴである。
摘要翻译：可以实现更高集成度并消耗更少功率的传输晶体管电路。传输晶体管电路设置有：连接到第一信号线的第一输入/输出端子（24）; 连接到第二信号线的第二输入/输出端子（26）; 第一装置（10a），其一端连接到第一电源; 第二装置（10b），其一端连接到第一装置的另一端，另一端连接到第二电源; 第一晶体管（10c），其源极连接到第一器件的另一端，并且其栅极接收第一控制信号; 以及第二晶体管（10d），其栅极连接到第一晶体管的漏极，源极连接到第一输入/输出端子，其漏极连接到第二输入/输出端子。第一和第二器件中的至少一个器件是非易失性存储器件，而另一个器件是MOSFET。

3. 发明申请

WO2007079295A3 DENSE READ-ONLY MEMORY 审中-公开
标题翻译： DENSE只读存储器
公开(公告)号：WO2007079295A3
公开(公告)日：2008-06-12
申请号：PCT/US2006061255
申请日：2006-11-27
申请人： NOVELICS LLC , WINOGRAD GIL I , AFGHAHI MORTEZA , TERZIOGLU ESIN
发明人： WINOGRAD GIL I , AFGHAHI MORTEZA , TERZIOGLU ESIN
IPC分类号： G06F12/00
CPC分类号： G11C17/10 , H01L27/112 , H01L27/11226
摘要： In one embodiment, a read-only memory (ROM) is provided that includes: a plurality of word lines; a plurality of bit lines; a plurality of memory cell transistors arranged in rows corresponding to the word lines such that if a word line is asserted the corresponding memory cell transistors are conducting, the memory cell transistors also being arranged in columns corresponding to the bit lines; wherein each column of memory cell transistors is arranged into column groups, each column group including an access transistor coupled to the corresponding bit line, the remaining transistors in the column group being coupled in series from the access transistor to a last transistor in the column group, the last transistor in the column group being coupled to a voltage node.
摘要翻译：在一个实施例中，提供了只读存储器（ROM），其包括：多个字线; 多个位线; 多个存储单元晶体管，其布置成与字线对应的行，使得如果字线被断言，相应的存储单元晶体管正在导通，则存储单元晶体管也被布置在与位线对应的列中; 其中每列存储单元晶体管被布置成列组，每个列组包括耦合到对应位线的存取晶体管，列组中的剩余晶体管从存取晶体管串联耦合到列组中的最后一个晶体管列组中的最后一个晶体管耦合到电压节点。

4. 发明申请

WO2008057257A2 ONE-TIME-PROGRAMMABLE LOGIC BIT WITH MULTIPLE LOGIC ELEMENTS 审中-公开
标题翻译：具有多个逻辑元素的一次可编程逻辑位
公开(公告)号：WO2008057257A2
公开(公告)日：2008-05-15
申请号：PCT/US2007/022657
申请日：2007-10-25
申请人： XILINX, INC.
发明人： PAAK, Sunhom , IM, Hsung, Jai , ANG, Boon, Yong
IPC分类号： H01L21/8246 , H01L27/105 , H01L27/112 , H01L27/118
CPC分类号： G11C17/18 , H01L23/5252 , H01L23/5256 , H01L27/101 , H01L27/105 , H01L27/112 , H01L27/11206 , H01L27/11286 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： A memory cell with a logic bit has a first one-time-programmable ("OTP") memory element providing a first OTP memory element output and a second OTP memory element providing a second OTP memory element output. A logic operator coupled to the first OTP memory element output and to the second OTP memory element output and provides a binary memory output of the memory cell. In a particular embodiment, the first OTP memory element is a different type of OTP memory than the second OTP memory element.
摘要翻译：具有逻辑位的存储器单元具有提供第一OTP存储器元件输出的第一一次可编程（“OTP”）存储器元件和提供第二OTP存储器元件输出的第二OTP存储器元件。耦合到第一OTP存储器元件输出和第二OTP存储器元件输出的逻辑运算器，并提供存储器单元的二进制存储器输出。在特定实施例中，第一OTP存储器元件是与第二OTP存储器元件不同类型的OTP存储器。

5. 发明申请

WO2007059480A3 POLYCIDE FUSE WITH REDUCED PROGRAMMING TIME 审中-公开
标题翻译：聚碳酸酯保险丝减少编程时间
公开(公告)号：WO2007059480A3
公开(公告)日：2008-01-17
申请号：PCT/US2006060859
申请日：2006-11-14
申请人： LATTICE SEMICONDUCTOR CORP
发明人： JIANG CHUN , LOGIE STEWART , MEHTA SUNIL
IPC分类号： H01L21/82 , H01L27/10
CPC分类号： H01L23/5256 , G11C17/16 , H01L27/112 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a polycide fuse is provided that includes: a polysilicon layer; a silicide layer formed on the polysilicon layer; and a silicon nitride layer formed on the silicide layer by RTCVD, the silicon nitride layer having a relatively low hydrogen concentration and relatively low mechanical stress.
摘要翻译：在一个实施例中，提供了多晶硅熔丝，其包括：多晶硅层; 形成在所述多晶硅层上的硅化物层; 以及通过RTCVD在硅化物层上形成的氮化硅层，氮化硅层具有相对低的氢浓度和相对低的机械应力。

6. 发明申请

WO2007019109A2 ONE TIME PROGRAMMABLE MEMORY AND METHOD OF OPERATION 审中-公开
标题翻译：一次性可编程存储器和操作方法
公开(公告)号：WO2007019109A2
公开(公告)日：2007-02-15
申请号：PCT/US2006029704
申请日：2006-07-28
申请人： FREESCALE SEMICONDUCTOR INC , HOEFLER ALEXANDER B , CHINDALORE GOWRISHANKAR L
发明人： HOEFLER ALEXANDER B , CHINDALORE GOWRISHANKAR L
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18 , H01L27/112
摘要： A one time programmable (OTP) memory (10) has two-bit cells (14) for increasing density. Each cell (14) has two select transistors (20, 24) and a programmable transistor (22) in series between the two select transistors. The programmable transistor (22) has two independent storage locations (22). One is between the gate (48) and a first source/drain region (66) and the second is between the gate (48) and a second source/drain region (68). The storage locations (72) are portions of the gate dielectric (60) where the sources or drains (66, 68) overlap the gate (48) and are independently programmed by selectively passing a programming current (44) through them. The programming current (44) is of sufficient magnitude and duration to permanently reduce the impedance by more than three orders of magnitude of the storage locations (72) to be programmed. The programming current (44) is limited in magnitude to avoid damage to other circuit elements and is preferably induced at least in part by applying a negative voltage to the gate (48) of the programming transistor (22).
摘要翻译：一次可编程（OTP）存储器（10）具有用于增加密度的两位单元（14）。每个单元（14）具有串联在两个选择晶体管之间的两个选择晶体管（20,24）和可编程晶体管（22）。可编程晶体管（22）具有两个独立的存储位置（22）。一个在栅极（48）和第一源极/漏极区域（66）之间，第二栅极（48）和第二源极/漏极区域（68）之间。存储位置（72）是栅极电介质（60）的部分，其中源极或漏极（66,68）与栅极（48）重叠，并且通过选择性地使编程电流（44）通过它们而被独立编程。编程电流（44）具有足够的幅度和持续时间，以将阻抗永久地减小待编程的存储位置（72）超过三个数量级。编程电流（44）的幅度受到限制以避免损坏其它电路元件，并且优选地通过向编程晶体管（22）的栅极（48）施加负电压至少部分地被感应。

7. 发明申请

WO2006085633A1 MEMORY ELEMENT AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：存储元件和半导体器件
公开(公告)号：WO2006085633A1
公开(公告)日：2006-08-17
申请号：PCT/JP2006/302413
申请日：2006-02-07
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD. , SATO, Takehisa , YUKAWA, Mikio , TAKANO, Tamae , ASAMI, Yoshinobu , YAMAZAKI, Shunpei
发明人： YUKAWA, Mikio , TAKANO, Tamae , ASAMI, Yoshinobu , YAMAZAKI, Shunpei
IPC分类号： H01L27/105 , G06K19/07 , G06K19/077 , G06K19/10 , H01L49/02
CPC分类号： H01L27/112 , G11C17/146 , G11C17/16
摘要： It is an object of the present invention to provide a nonvolatile memory device, in which additional writing is possible other than in manufacturing and forgery and the like due to rewriting can be prevented, and a semiconductor device having the memory device. It is another object of the present invention to provide an inexpensive and nonvolatile memory device with high reliability and a semiconductor device. According to one feature of the present invention, a memory device includes a first conductive layer formed over an insulating surface, a second conductive layer, a first insulating layer interposed between the first conductive layer and the second conductive layer, and a second insulating layer which covers a part of the first conductive layer, wherein the first insulating layer covers an edge portion of the first conductive layer, the insulating surface, and the second insulating layer.
摘要翻译：本发明的一个目的是提供一种非易失性存储器件，其中除了可以防止由于重写而在制造和伪造等之外，还可能进行附加写入，以及具有存储器件的半导体器件。本发明的另一个目的是提供一种具有高可靠性的廉价且非易失性的存储器件和半导体器件。根据本发明的一个特征，一种存储器件包括：在绝缘表面上形成的第一导电层，第二导电层，介于第一导电层和第二导电层之间的第一绝缘层;以及第二绝缘层，覆盖第一导电层的一部分，其中第一绝缘层覆盖第一导电层，绝缘表面和第二绝缘层的边缘部分。

8. 发明申请

WO2006051487A1 FLASH- AND ROM- MEMORY 审中-公开
标题翻译： FLASH-和ROM-存储器
公开(公告)号：WO2006051487A1
公开(公告)日：2006-05-18
申请号：PCT/IB2005/053672
申请日：2005-11-08
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VERHAAR, Rob , DORMANS, Guido, J., M. , STORMS, Maurits , CUPPENS, Roger , LIST, Frans, J. , BEURZE, Robert, H.
发明人： VERHAAR, Rob , DORMANS, Guido, J., M. , STORMS, Maurits , CUPPENS, Roger , LIST, Frans, J. , BEURZE, Robert, H.
IPC分类号： H01L27/112 , H01L27/115 , H01L21/8246 , H01L21/8247
CPC分类号： H01L27/1122 , H01L27/112 , H01L27/11226 , H01L27/115
摘要： Method for conversion of a Flash memory cell on a first semiconductor device to a ROM memory cell in a second semiconductor device, the first and second semiconductor device each being arranged on a semiconductor substrate and each comprising an identical device portion and an identical wiring scheme for wiring the device portion to the Flash memory cell and to the ROM memory cell, respectively; the Flash memory cell being made in non-volatile memory technology and comprising an access transistor and a floating transistor, the floating transistor comprising a floating gate and a control gate; the ROM memory cell being made in a baseline technology and comprising a single gate transistor, which method includes manipulating a layout of at least one baseline mask as used in the baseline technology; the manipulation including: incorporating into the layout of the at least one baseline mask a layout of the Flash memory cell, and converting the layout of the Flash memory cell to a layout of one ROM memory cell by eliminating, from the at least one baseline mask, a layout for the floating transistor from the layout of the Flash memory cell and designating the layout of the access transistor of the Flash memory cell as a layout of the single gate transistor of the ROM memory cell.
摘要翻译：用于将第一半导体器件上的闪存单元转换为第二半导体器件中的ROM存储单元的方法，所述第一和第二半导体器件各自布置在半导体衬底上，并且每个包括相同的器件部分和相同的布线方案将设备部分分别连接到闪存单元和ROM存储单元; 所述闪存单元由非易失性存储器技术制成并且包括存取晶体管和浮置晶体管，所述浮动晶体管包括浮置栅极和控制栅极; 所述ROM存储器单元是在基线技术中制成并且包括单个栅极晶体管，该方法包括操作基线技术中使用的至少一个基线掩模的布局; 所述操作包括：将所述至少一个基准掩码的布局合并到所述闪存单元的布局中，以及通过从所述至少一个基线掩码中消除所述闪存单元的布局而将所述闪存单元的布局转换为一个ROM存储器单元的布局，根据闪存单元的布局布置浮动晶体管，并指定闪存单元的存取晶体管的布局作为ROM存储单元的单栅极晶体管的布局。

9. 发明申请

WO2005091300A1 PRINTED MAGNETIC ROM - MPROM 审中-公开
标题翻译：打印磁性ROM - MPROM
公开(公告)号：WO2005091300A1
公开(公告)日：2005-09-29
申请号：PCT/IB2005/050797
申请日：2005-03-03
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PHILLIPS, Gavin
发明人： PHILLIPS, Gavin
IPC分类号： G11C11/16
CPC分类号： H01L27/112 , B82Y10/00 , G06K9/0002 , G11C11/16 , H01L27/11206 , H01L27/22 , H01L27/228
摘要： The invention relates to a method for storing information on a storage device (100) by depositing electro-magnetic material (104) in a pattern on a sensor surface (106) of the storage device, the pattern representing the information to be stored. The storage device (100) comprises an array of sensor elements (101) that are sensitive to electro-magnetic material (104) within a near field working distance (105). The read-out is done by a resistance measurement which relies on a magneto resistance phenomenon detected in a multilayer stack of the sensor elements (101). The storage device (100), comprising the deposited pattern of electro-magnetic material (104), is a Read Only Memory device. The deposition of the pattern is, for example, possible by scanning a depositing unit (403), e.g. a printer head, in a line-by-line motion across the sensor surface (106), resulting in a Printed Magnetic ROM. This device can also be used as a fingerprint sensor, if a finger is used as template.
摘要翻译：本发明涉及一种通过以存储装置的传感器表面（106）上的图案沉积电磁材料（104）来将信息存储在存储装置（100）上的方法，该图案表示要存储的信息。存储装置（100）包括在近场工作距离（105）内对电磁材料（104）敏感的传感器元件阵列（101）。通过电阻测量完成读出，该电阻测量依赖于在传感器元件（101）的多层堆叠中检测到的磁阻现象。包括电磁材料（104）的沉积图案的存储装置（100）是只读存储装置。图案的沉积例如可以通过扫描沉积单元（403），例如，打印机头，跨越传感器表面（106）并行运动，产生印刷磁性ROM。如果手指用作模板，该设备也可以用作指纹传感器。

10. 发明申请

WO2005001899A3 NON-VOLATILE ELECTROMECHANICAL FIELD EFFECT DEVICES AND CIRCUITS USING SAME AND METHODS OF FORMING SAME 审中-公开
标题翻译：非挥发性电化学效应装置和使用其的电路及其形成方法
公开(公告)号：WO2005001899A3
公开(公告)日：2005-06-09
申请号：PCT/US2004018349
申请日：2004-06-09
申请人： NANTERO INC , BERTIN CLAUDE L , RUECKES THOMAS , SEGAL BRENT M , VOGELI BERNHARD , BROCK DARREN K , JAIPRAKASH VENKATACHALAM C
发明人： BERTIN CLAUDE L , RUECKES THOMAS , SEGAL BRENT M , VOGELI BERNHARD , BROCK DARREN K , JAIPRAKASH VENKATACHALAM C
IPC分类号： G11C7/06 , G11C8/02 , G11C11/00 , G11C11/50 , G11C13/02 , G11C16/02 , G11C16/04 , G11C17/16 , G11C23/00 , H01H59/00 , H01J1/62 , H01L20060101 , H01L21/336 , H01L21/82 , H01L21/8246 , H01L27/112 , H01L27/115 , H01L27/28 , H01L29/06 , H01L29/423 , H01L29/739 , H01L29/745 , H01L29/76 , H01L51/00 , H01L51/05 , H01L51/30 , H03K17/16
CPC分类号： H01L29/78 , B82Y10/00 , B82Y99/00 , G11C7/065 , G11C13/025 , G11C16/0416 , G11C17/16 , G11C17/165 , G11C23/00 , G11C2213/16 , G11C2213/17 , G11C2213/79 , H01H1/0094 , H01L27/10 , H01L27/1052 , H01L27/112 , H01L27/11206 , H01L27/115 , H01L27/286 , H01L29/0665 , H01L29/0673 , H01L29/42324 , H01L51/0048 , H01L51/0052 , H01L51/0508 , Y10S977/708 , Y10S977/724 , Y10S977/742 , Y10S977/762 , Y10S977/936 , Y10S977/938 , Y10S977/94 , Y10S977/943
摘要： Non-volatile field effect devices and circuits using same. A non-volatile field effect transistor utilizes a nanatube-based mechanical switch (30). The switch location can be at the source, drain or gate locations of the field effect transistor. Under one embodiment, the field effect device includes a source region and a drain region with a channel region (27) disposed therebetween. The source region is connected to a corresponding terminal (T2). A gate structure is disposed over the channel region and connected to a corresponding terminal (T1). A nanotube switching element (30) is responsive to a first control terminal (T3) and a second control terminal (T4) and is electrically positioned in series between the drain region and a terminal corresponding to the drain region. The nanotube switching element is electromechanically operable to one of an open and closed state to thereby open or close an electrical communication path between the drain region and its corresponding terminal.
摘要翻译：非易失性场效应器件和使用其的电路。非易失性场效应晶体管利用基于纳米管的机械开关（30）。开关位置可以在场效应晶体管的源极，漏极或栅极位置。在一个实施例中，场效应器件包括源极区域和漏极区域，其间设置有沟道区域（27）。源极区域连接到相应的端子（T2）。栅极结构设置在沟道区域上并连接到相应的端子（T1）。纳米管开关元件（30）响应于第一控制端（T3）和第二控制端（T4），并且电连接地位于漏区和与漏区对应的端子之间。纳米管开关元件在机械上可操作地处于打开和关闭状态之一，从而打开或闭合漏极区域及其对应端子之间的电连通路径。

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