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1. 发明申请

WO2016102166A1 VERFAHREN ZUM ELEKTRISCHEN KONTAKTIEREN EINES BAUTEILS UND BAUTEILEVERBUND 审中-公开
标题翻译：法电触头的组成部分，零部件复合
公开(公告)号：WO2016102166A1
公开(公告)日：2016-06-30
申请号：PCT/EP2015/078524
申请日：2015-12-03
申请人： ROBERT BOSCH GMBH
发明人： SCHAAF, Ulrich , BERSCHAUER, Kristina , WAHL, Ruben , LORENZ, Enno , KUGLER, Andreas
IPC分类号： H01L23/48
CPC分类号： H01L24/82 , H01L24/24 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/83 , H01L2224/2402 , H01L2224/24051 , H01L2224/24227 , H01L2224/2919 , H01L2224/32014 , H01L2224/32225 , H01L2224/73267 , H01L2224/82101 , H01L2224/82102 , H01L2224/82105 , H01L2224/82106 , H01L2224/83862 , H01L2224/92244 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/351 , H01L2924/37001 , H01L2924/00012 , H01L2924/00014 , H01L2924/07802
摘要： Die Erfindung betrifft ein Verfahren zum elektrischen Kontaktieren eines Bauteils (1), wobei das Bauteil (1) auf einem Schaltungsträger (10) angeordnet wird, der einen ersten Anschlussbereich (11) aufweist, und wobei der erste Anschlussbereich (11) mittels einer elektrisch leitenden Schicht (25) mit einem zweiten, dem Bauteil (1) zugeordneten Anschlussbereich (3) verbunden wird. Erfindungsgemäß ist es vorgesehen, dass das Bauteil (1) zumindest im Übergangsbereich zwischen dem Bauteil (1) und dem Schaltungsträger (10) zur Überbrückung unterschiedlicher Höhenniveaus zwischen dem Schaltungsträger (10) und dem Bauteil (1) mit einem insbesondere folienartigen Ausgleichselement (20) überdeckt wird, und dass das Ausbilden der elektrisch leitenden Schicht (25) nach dem Anordnen des Ausgleichselements (20) erfolgt.
摘要翻译：本发明涉及一种用于电接触的组件（1），其中一个电路载体（10）上的组件（1）被设置，由导电的装置的第一端子部（11），并且其中所述第一端子区域（11）层（25）与第二，与所述连接区域（3）相关联的组件（1）连接。根据本发明，提供的是至少在组分（1）和所述电路支撑件（10），用于在电路载体（10）之间的桥接不同的高度水平和部件之间的过渡区域（1）具有特别膜状补偿元件（20）中的组分（1）被覆盖，并且所述补偿元件（20）的放置之后的导电层（25）的是，成形。

2. 发明申请

WO2014020479A3 POST-CMOS PROCESSING AND 3D INTEGRATION BASED ON DRY-FILM LITHOGRAPHY 审中-公开
标题翻译：基于干膜光刻的后CMOS处理和3D集成
公开(公告)号：WO2014020479A3
公开(公告)日：2014-04-10
申请号：PCT/IB2013055946
申请日：2013-07-19
申请人： ECOLE POLYTECH
发明人： GUIDUCCI CARLOTTA , LEBLEBICI YUSUF , TEMIZ YÜKSEL
IPC分类号： H01L21/60 , H01L21/683 , H01L21/768 , H01L21/98 , H01L23/31 , H01L23/48 , H01L25/065
CPC分类号： H01L25/50 , G03F7/2022 , G03F7/32 , H01L21/568 , H01L21/6835 , H01L21/76898 , H01L23/3185 , H01L24/02 , H01L24/05 , H01L24/24 , H01L24/27 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L2221/68381 , H01L2224/02313 , H01L2224/0239 , H01L2224/05166 , H01L2224/05624 , H01L2224/24011 , H01L2224/24051 , H01L2224/24146 , H01L2224/27002 , H01L2224/32145 , H01L2224/73267 , H01L2224/82002 , H01L2224/82005 , H01L2224/8201 , H01L2224/82101 , H01L2224/82106 , H01L2224/82143 , H01L2224/83143 , H01L2224/83203 , H01L2224/8385 , H01L2224/9202 , H01L2224/92244 , H01L2224/94 , H01L2225/06541 , H01L2225/06544 , H01L2225/06565 , H01L2924/01322 , H01L2924/10253 , H01L2924/1461 , H01L2924/00014 , H01L2924/01013 , H01L2924/00013 , H01L2224/83 , H01L2224/82 , H01L2924/00
摘要： A method for performing a post processing patterning on a diced chip having a footprint, comprises the steps of: - providing a support wafer; - applying a first dry film photoresist to the support wafer; - positioning a mask corresponding to the footprint of the diced chip on the first dry film photoresist; - exposing the mask and the first dry film photoresist to UV radiation; - removing the mask; - developing the exposed first dry film photoresist to obtain a cavity corresponding to the diced chip; - positioning the diced chip inside the cavity; - applying a second dry film photoresist to the first film photoresist and the diced chip; - exposing and developing the second dry film photoresist applied to the diced chip in accordance with the post processing pattern; and - performing an anisotropic dry etching of the chip to form a via therein. Furthermore, a method for obtaining a stack of two semiconductor chips or wafers in a back to face configuration, whereby at least one of the semiconductor chips or wafers comprises a through silicon via (TSV), comprises the steps of: - providing a first semiconductor chip or wafer; - providing a second semiconductor chip or wafer; - making a hole through the second semiconductor chip or wafer from a face side to a back side; - applying the face side of second semiconductor chip or wafer on a release tape; - depositing parylene on the assembly of the second semiconductor chip or wafer and the release tape, thereby obtaining a sidewall passivation in the hole and a bonding layer on the back side of the second semiconductor chip or wafer; - releasing the release tape, thereby obtaining a membrane of parylene covering an opening of the hole on the front side; - positioning the back side of the second semiconductor chip or wafer relative to a face side of the first semiconductor chip or wafer; - bonding the second semiconductor chip or wafer to the first semiconductor chip or wafer by applying pressure and heat; - removing the membrane of parylene by directional etching; and - electrically connecting the face side of the second semiconductor chip or wafer to the face side of the first semiconductor chip or wafer by depositing a conductor inside the hole, thereby obtaining the TSV.
摘要翻译：一种用于在具有占地面积的切割芯片上执行后处理图案化的方法包括以下步骤： - 提供支撑晶片; - 将第一干膜光致抗蚀剂施加到所述支撑晶片; - 将对应于切割芯片的覆盖区的掩模定位在第一干膜光致抗蚀剂上; - 将所述掩模和所述第一干膜光致抗蚀剂暴露于UV辐射; - 去除面膜; - 将暴露的第一干膜光致抗蚀剂显影以获得对应于切割芯片的腔; - 将切割的芯片定位在腔内; - 将第二干膜光致抗蚀剂施加到第一膜光致抗蚀剂和切割的芯片上; - 根据后处理图案曝光和显影施加到切割的芯片上的第二干膜光致抗蚀剂; 以及 - 对所述芯片进行各向异性干蚀刻以在其中形成通孔。此外，一种用于以背对面配置获得两个半导体芯片或晶片的堆叠的方法，由此半导体芯片或晶片中的至少一个包括贯穿硅通孔（TSV），包括以下步骤： - 提供第一半导体芯片或晶片; - 提供第二半导体芯片或晶片; - 从第二半导体芯片或晶片从正面到背面形成一个孔; - 将第二半导体芯片或晶片的表面施加在释放带上; - 将聚对二甲苯沉积在第二半导体芯片或晶片和释放带的组件上，从而在孔中获得侧壁钝化和在第二半导体芯片或晶片的背面上的结合层; - 释放释放带，从而获得覆盖前侧的孔的开口的聚对二甲苯膜; - 相对于所述第一半导体芯片或晶片的正面侧定位所述第二半导体芯片或晶片的背面; - 通过施加压力和热量将所述第二半导体芯片或晶片接合到所述第一半导体芯片或晶片; - 通过定向蚀刻去除聚对二甲苯膜; 以及 - 通过在孔内沉积导体，将第二半导体芯片或晶片的表面侧电连接到第一半导体芯片或晶片的正面，从而获得TSV。

3. 发明申请

WO2011126726A1 ELECTRICALLY BONDED ARRAYS OF TRANSFER PRINTED ACTIVE COMPONENTS 审中-公开
标题翻译：传输打印活动组件的电粘结阵列
公开(公告)号：WO2011126726A1
公开(公告)日：2011-10-13
申请号：PCT/US2011/029365
申请日：2011-03-22
申请人： SEMPRIUS, INC. , MENARD, Etienne , BOWER, Christopher , MEITL, Matthew , GARROU, Philip
发明人： MENARD, Etienne , BOWER, Christopher , MEITL, Matthew , GARROU, Philip
IPC分类号： H01L21/77
CPC分类号： H05K7/06 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L24/02 , H01L24/05 , H01L24/08 , H01L24/24 , H01L24/27 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/83 , H01L24/92 , H01L27/1214 , H01L27/1266 , H01L27/14618 , H01L31/0203 , H01L31/048 , H01L2221/6835 , H01L2221/68372 , H01L2221/68381 , H01L2224/02371 , H01L2224/02372 , H01L2224/0239 , H01L2224/04026 , H01L2224/05548 , H01L2224/056 , H01L2224/08238 , H01L2224/24011 , H01L2224/24137 , H01L2224/24147 , H01L2224/24226 , H01L2224/245 , H01L2224/24998 , H01L2224/2731 , H01L2224/29078 , H01L2224/291 , H01L2224/29101 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/29344 , H01L2224/3012 , H01L2224/32104 , H01L2224/32146 , H01L2224/32227 , H01L2224/73267 , H01L2224/76155 , H01L2224/80203 , H01L2224/80224 , H01L2224/81192 , H01L2224/82007 , H01L2224/821 , H01L2224/82102 , H01L2224/82106 , H01L2224/83093 , H01L2224/83121 , H01L2224/83191 , H01L2224/83192 , H01L2224/83805 , H01L2224/83815 , H01L2224/8384 , H01L2224/83851 , H01L2224/83855 , H01L2224/83859 , H01L2224/83862 , H01L2224/83868 , H01L2224/83871 , H01L2224/83874 , H01L2224/92143 , H01L2224/92244 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01057 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/0133 , H01L2924/014 , H01L2924/10329 , H01L2924/12041 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/15787 , H01S5/02236 , H01S5/02276 , H05K1/18 , H05K3/0058 , H05K3/10 , H05K13/04 , H05K13/046 , Y02E10/50 , Y10T29/41 , Y10T29/4913 , Y10T29/49139 , H01L2924/00014 , H01L2924/00 , H01L2224/13111
摘要： An active component array includes a target substrate having one or more contacts formed on a side of the target substrate, and one or more printable active components distributed over the target substrate. Each active component includes an active layer having a top side and an opposing bottom side and one or more active element(s) formed on or in the top side of the active layer. The active element(s) are electrically connected to the contact(s), and the bottom side is adhered to the target substrate. Related fabrication methods are also discussed.
摘要翻译：有源元件阵列包括具有形成在目标基板一侧上的一个或多个触点的目标基板和分布在目标基板上的一个或多个可印刷的有源元件。每个有源部件包括有源层，其具有形成在有源层的顶侧上或其中的顶侧和相对的底侧以及一个或多个有源元件。有源元件电连接到触点，并且底侧粘附到目标基板。还讨论了相关的制造方法。

4. 发明申请

WO2015175131A1 FLEXIBLE DISPLAY AND METHOD OF FORMATION WITH SACRIFICIAL RELEASE LAYER 审中-公开
标题翻译：柔性显示和形式与强制释放层的方法
公开(公告)号：WO2015175131A1
公开(公告)日：2015-11-19
申请号：PCT/US2015/025873
申请日：2015-04-15
申请人： LUXVUE TECHNOLOGY CORPORATION
发明人： BIBL, Andreas , GOLDA, Dariusz
IPC分类号： G09F9/30 , H01L25/075 , H01L25/16 , H01L27/12 , H05K1/18
CPC分类号： H01L25/167 , G09F9/301 , H01L21/6835 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/97 , H01L25/0753 , H01L27/1266 , H01L27/15 , H01L27/153 , H01L27/156 , H01L2221/68318 , H01L2221/68359 , H01L2221/68381 , H01L2224/11462 , H01L2224/1147 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/16227 , H01L2224/24101 , H01L2224/24105 , H01L2224/24227 , H01L2224/245 , H01L2224/27462 , H01L2224/2747 , H01L2224/291 , H01L2224/29109 , H01L2224/29111 , H01L2224/32227 , H01L2224/73259 , H01L2224/73267 , H01L2224/81005 , H01L2224/81192 , H01L2224/81424 , H01L2224/81438 , H01L2224/81444 , H01L2224/81466 , H01L2224/81486 , H01L2224/8149 , H01L2224/81805 , H01L2224/81825 , H01L2224/8183 , H01L2224/82005 , H01L2224/82102 , H01L2224/82104 , H01L2224/82106 , H01L2224/83005 , H01L2224/83192 , H01L2224/83424 , H01L2224/83438 , H01L2224/83444 , H01L2224/83466 , H01L2224/83486 , H01L2224/8349 , H01L2224/83805 , H01L2224/83825 , H01L2224/8383 , H01L2224/92224 , H01L2224/92244 , H01L2224/97 , H01L2924/10161 , H01L2924/10162 , H01L2924/12041 , H01L2924/14 , H01L2924/15156 , H01L2924/18161 , H01L2924/18162 , H05K1/189 , H05K3/4682 , H05K2201/10106 , H01L2924/00014 , H01L2924/014 , H01L2924/01074 , H01L2924/01013 , H01L2924/01014 , H01L2924/0781 , H01L2924/01038 , H01L2924/053 , H01L2924/06 , H01L2924/01006 , H01L2924/01047 , H01L2924/01079 , H01L2924/01042 , H01L2924/01022 , H01L2924/01071 , H01L2224/81 , H01L2224/82 , H01L2224/83
摘要： A flexible display panel (103) and method of formation with a sacrificial release layer are described. The method of manufacturing a flexible display system includes forming a sacrificial layer on a carrier substrate (101). A flexible display substrate (105) is formed on the sacrificial layer, with a plurality of release openings (111) that extend through the flexible display substrate (105) to the sacrificial layer. An array of LEDs (106) and a plurality of microchips (108) are transferred onto the flexible display substrate (105) to form a flexible display panel (103). The sacrificial layer is selectively removed such that the flexible display panel (103) attaches to the carrier substrate (101) by a plurality of support posts. The flexible display panel (103) is removed from the carrier substrate (101) and is electrically coupled with display components to form a flexible display system.
摘要翻译：描述了柔性显示面板（103）及其形成方法。柔性显示系统的制造方法包括在载体基板（101）上形成牺牲层。柔性显示基板（105）形成在牺牲层上，多个释放开口（111）延伸穿过柔性显示基板（105）至牺牲层。一组LED（106）和多个微芯片（108）被转移到柔性显示基板（105）上以形成柔性显示面板（103）。选择性地去除牺牲层，使得柔性显示面板（103）通过多个支撑柱附接到载体基板（101）。柔性显示面板（103）从载体基板（101）移除并与显示部件电耦合以形成柔性显示系统。

5. 发明申请

WO2013109593A2 LASER ASSISTED TRANSFER WELDING PROCESS 审中-公开
标题翻译：激光辅助传输焊接工艺
公开(公告)号：WO2013109593A2
公开(公告)日：2013-07-25
申请号：PCT/US2013/021686
申请日：2013-01-16
申请人： SEMPRIUS, INC. , THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS
发明人： MENARD, Etienne , MEITL, Matthew , ROGERS, John A.
IPC分类号： H01L21/60
CPC分类号： H01L27/1266 , H01L21/6835 , H01L21/76898 , H01L21/7806 , H01L23/481 , H01L23/544 , H01L24/02 , H01L24/05 , H01L24/08 , H01L24/24 , H01L24/27 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/73 , H01L24/75 , H01L24/799 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/97 , H01L24/98 , H01L27/1214 , H01L27/14618 , H01L31/0203 , H01L31/043 , H01L31/048 , H01L31/1892 , H01L2221/68318 , H01L2221/68322 , H01L2221/6835 , H01L2221/68368 , H01L2221/68372 , H01L2221/68381 , H01L2223/5442 , H01L2223/54426 , H01L2223/54486 , H01L2224/02371 , H01L2224/02372 , H01L2224/0239 , H01L2224/04026 , H01L2224/05548 , H01L2224/056 , H01L2224/08238 , H01L2224/24011 , H01L2224/24137 , H01L2224/24147 , H01L2224/24226 , H01L2224/245 , H01L2224/24998 , H01L2224/2731 , H01L2224/29078 , H01L2224/291 , H01L2224/29101 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/29344 , H01L2224/3012 , H01L2224/32104 , H01L2224/32146 , H01L2224/32227 , H01L2224/73267 , H01L2224/75263 , H01L2224/75314 , H01L2224/7598 , H01L2224/76155 , H01L2224/80203 , H01L2224/80224 , H01L2224/82007 , H01L2224/821 , H01L2224/82102 , H01L2224/82106 , H01L2224/83093 , H01L2224/83121 , H01L2224/83132 , H01L2224/83191 , H01L2224/83192 , H01L2224/83224 , H01L2224/83805 , H01L2224/83815 , H01L2224/8384 , H01L2224/83851 , H01L2224/83855 , H01L2224/83859 , H01L2224/83862 , H01L2224/83868 , H01L2224/83871 , H01L2224/83874 , H01L2224/92244 , H01L2224/9512 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01057 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/0133 , H01L2924/014 , H01L2924/10329 , H01L2924/12041 , H01L2924/12044 , H01L2924/14 , H01L2924/15787 , H01S5/02236 , H01S5/02276 , H05K1/18 , H05K13/04 , H05K13/046 , Y02E10/50 , Y10T29/49124 , Y10T29/51 , H01L2924/00014 , H01L2924/00 , H01L2224/13111
摘要： Methods of operating a base station serving a cell in a heterogeneous network and at least one relay node serving a subcell of the cell, in which a user equipment unit connects to the network via the base station or the relay node, are provided. The methods include receiving uplink access (Uu) signals at the relay node from the user equipment unit in a first frequency range, and transmitting uplink backhaul (Un) signals from the relay node to the base station in a second frequency range that is different from the first frequency range.
摘要翻译：提供服务于异构网络中的小区的基站和至少一个服务小区的子小区的中继节点的方法，其中用户设备单元经由基站或中继节点连接到网络。所述方法包括在第一频率范围内从所述用户设备单元在所述中继节点处接收上行接入（Uu）信号，并且在与所述中继节点不同的第二频率范围内从所述中继节点向所述基站发送上行回程（Un）信号第一个频率范围。

6. 发明申请

WO2012040735A2 METHODS OF FORMING FULLY EMBEDDED BUMPLESS BUILD-UP LAYER PACKAGES AND STRUCTURES FORMED THEREBY 审中-公开
标题翻译：形成完全嵌入式无损建筑层包装和由其形成的结构的方法
公开(公告)号：WO2012040735A2
公开(公告)日：2012-03-29
申请号：PCT/US2011053325
申请日：2011-09-26
申请人： INTEL CORP , NALLA RAVI K , MANUSHAROW MATHEW J , MALATKAR PRAMOD
发明人： NALLA RAVI K , MANUSHAROW MATHEW J , MALATKAR PRAMOD
IPC分类号： H01L23/48 , H01L23/12 , H01L23/485
CPC分类号： H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/49816 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/82 , H01L24/93 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/20 , H01L2224/21 , H01L2224/2101 , H01L2224/211 , H01L2224/22 , H01L2224/2201 , H01L2224/221 , H01L2224/24011 , H01L2224/24146 , H01L2224/251 , H01L2224/25105 , H01L2224/2518 , H01L2224/82005 , H01L2224/821 , H01L2224/82101 , H01L2224/82106 , H01L2224/93 , H01L2225/06524 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/014 , H01L2924/12042 , H01L2924/181 , H01L2924/18162 , H01L2224/82 , H01L2221/68304 , H01L2924/00
摘要： Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include a die embedded in a coreless substrate, wherein a mold compound surrounds the die, and wherein the die comprises TSV connections on a first side and C4 pads on a second side of the die, a dielectric material on a first side and on a second side of the mold compound; and interconnect structures coupled to the C4 pads and to the TSV pads. Embodiments further include forming packaging structures wherein multiple dies are fully embedded within a BBUL package without PoP lands.
摘要翻译：描述了形成微电子封装结构和由此形成的相关结构的方法。这些方法可以包括嵌入无芯基板中的管芯，其中模制化合物围绕管芯，并且其中管芯包括第一侧上的TSV连接和管芯第二侧上的C4焊盘，第一侧上的电介质材料以及在模塑料的第二侧上; 以及耦合到C4焊盘和TSV焊盘的互连结构。实施例还包括形成封装结构，其中多个管芯完全嵌入在没有PoP焊盘的BBUL封装内。

7. 发明申请

WO2015095836A2 HIGHLY SCALABLE FABRICATION TECHNIQUES AND PACKAGING DEVICES FOR ELECTRONIC CIRCUITS 审中-公开
标题翻译：用于电子电路的高可扩展的制造技术和包装设备
公开(公告)号：WO2015095836A2
公开(公告)日：2015-06-25
申请号：PCT/US2014/071741
申请日：2014-12-19
申请人： THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
发明人： COLEMAN, Todd, Prentice , KIM, Yun, Soung , BAJEMA, Michael , WEINREB, Robert, N.
IPC分类号： H01L21/328
CPC分类号： H05K1/118 , H01L21/4853 , H01L21/4857 , H01L21/56 , H01L23/145 , H01L23/5387 , H01L23/5389 , H01L24/24 , H01L24/25 , H01L24/82 , H01L33/62 , H01L2224/24011 , H01L2224/2402 , H01L2224/24101 , H01L2224/24137 , H01L2224/25175 , H01L2224/82005 , H01L2224/82051 , H01L2224/82106 , H01L2224/82951 , H01L2224/97 , H01L2933/0066 , H05K1/025 , H05K1/0393 , H05K1/189 , H05K3/303 , H05K3/4644 , H05K3/465 , H05K3/4682 , H05K2201/0154 , H05K2201/0162 , H05K2201/0209 , H05K2201/026 , H05K2201/10037 , H05K2201/10106 , H05K2201/10121 , H05K2201/10151 , H05K2201/10166 , H05K2201/10174 , H05K2201/10522 , H05K2203/0173 , H05K2203/1316 , H05K2203/1469 , H05K3/467 , H01L2224/82
摘要： Disclosed are highly scalable fabrication methods for producing electronic circuits, devices, and systems. In one aspect, a fabrication method includes attaching an electronic component at a location on a substrate including a flexible and electrically insulative material; forming a template to encase the electronic component by depositing a material in a phase to conform on the surfaces of the electronic component and the substrate, and causing the material to change to solid form; and producing a circuit or electronic device by forming openings in the substrate to expose conductive portions of the electronic component, creating electrical interconnections coupled to at least some of the conductive portions in a selected arrangement on the substrate, and depositing a layer of an electrically insulative and flexible material over the electrical interconnections on the substrate to form a flexible base of the circuit, in which the produced circuit or electronic device is encased in the template.
摘要翻译：公开了用于生产电子电路，设备和系统的高度可扩展的制造方法。一方面，一种制造方法，包括在包括柔性和电绝缘材料的基板上的位置处附接电子部件; 形成模板以通过在相位上沉积材料以使电子部件和基板的表面相符合并使材料变为固体形式来包住电子部件; 以及通过在所述衬底中形成开口以暴露所述电子部件的导电部分来产生电路或电子器件，从而在所述衬底上以所选择的布置形成耦合到至少一些所述导电部分的电互连，以及沉积电绝缘层以及在衬底上的电互连上的柔性材料，以形成电路的柔性基座，其中所产生的电路或电子器件被封装在模板中。

8. 发明申请

WO2014020479A2 Post-CMOS Processing and 3D Integration Based on Dry-Film Lithography 审中-公开
标题翻译：基于干膜平版印刷的CMOS后处理和3D集成
公开(公告)号：WO2014020479A2
公开(公告)日：2014-02-06
申请号：PCT/IB2013/055946
申请日：2013-07-19
申请人： ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)
发明人： GUIDUCCI, Carlotta , LEBLEBICI, Yusuf , TEMIZ, Yüksel
IPC分类号： H01L21/60
CPC分类号： H01L25/50 , G03F7/2022 , G03F7/32 , H01L21/568 , H01L21/6835 , H01L21/76898 , H01L23/3185 , H01L24/02 , H01L24/05 , H01L24/24 , H01L24/27 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/0657 , H01L2221/68381 , H01L2224/02313 , H01L2224/0239 , H01L2224/05166 , H01L2224/05624 , H01L2224/24011 , H01L2224/24051 , H01L2224/24146 , H01L2224/27002 , H01L2224/32145 , H01L2224/73267 , H01L2224/82002 , H01L2224/82005 , H01L2224/8201 , H01L2224/82101 , H01L2224/82106 , H01L2224/82143 , H01L2224/83143 , H01L2224/83203 , H01L2224/8385 , H01L2224/9202 , H01L2224/9205 , H01L2224/92244 , H01L2224/94 , H01L2225/06541 , H01L2225/06544 , H01L2225/06565 , H01L2924/01322 , H01L2924/10253 , H01L2924/1461 , H01L2924/00014 , H01L2924/01013 , H01L2924/00013 , H01L2224/83 , H01L2224/82 , H01L2924/00
摘要： A method for performing a post processing pattern on a diced chip having a foot print, comprises the steps of providing a support wafer; applying a first dry film photoresist to the support wafer; positioning a mask corresponding to the footprint of the diced chip on the first dry film photoresist; expose the mask and the first dry film photoresist to UV radiation; remove the mask; photoresist develop the exposed first dry film photoresist to obtain a cavity corresponding to the diced chip; positioning the diced chip inside the cavity; applying a second dry film photoresist to the first film photoresist and the diced chip; and expose and develop the second dry film photoresist applied to the diced chip in accordance with the post processing pattern.
摘要翻译：一种用于在具有脚印的切割芯片上执行后处理图案的方法，包括以下步骤：提供支撑晶片; 将第一干膜光致抗蚀剂施加到所述支撑晶片; 将对应于切割的芯片的覆盖区的掩模定位在第一干膜光致抗蚀剂上; 将掩模和第一干膜光致抗蚀剂暴露于UV辐射; 取下面具; 光致抗蚀剂显影曝光的第一干膜光致抗蚀剂以获得与切割芯片相对应的空腔; 将切割的芯片定位在腔内; 将第二干膜光致抗蚀剂施加到第一膜光致抗蚀剂和切割的芯片上; 并且根据后处理图案曝光和显影施加到切割的芯片上的第二干膜光致抗蚀剂。

9. 发明申请

WO2012006063A2 MICROELECTRONIC PACKAGE AND METHOD OF MANUFACTURING SAME 审中-公开
标题翻译：微电子封装及其制造方法
公开(公告)号：WO2012006063A2
公开(公告)日：2012-01-12
申请号：PCT/US2011/042126
申请日：2011-06-28
申请人： INTEL CORPORATION , NALLA, Ravi, K. , MANUSHAROW, Mathew, J. , DELANEY, Drew
发明人： NALLA, Ravi, K. , MANUSHAROW, Mathew, J. , DELANEY, Drew
IPC分类号： H01L23/48 , H05K3/46 , H01L21/60
CPC分类号： H01L23/481 , H01L23/5389 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/25 , H01L24/48 , H01L24/82 , H01L24/83 , H01L25/0655 , H01L25/105 , H01L2224/0401 , H01L2224/04105 , H01L2224/05009 , H01L2224/0557 , H01L2224/06181 , H01L2224/16225 , H01L2224/16227 , H01L2224/24137 , H01L2224/2518 , H01L2224/32245 , H01L2224/48227 , H01L2224/73267 , H01L2224/82105 , H01L2224/82106 , H01L2224/83203 , H01L2224/92244 , H01L2225/1035 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01076 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/1461 , H01L2924/19041 , H01L2924/19042 , H01L2924/30107 , H01L2924/00 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A microelectronic package includes a substrate (110), a die (120) embedded within the substrate, the die having a front side (121) and a back side (122) and a through-silicon-via (123) therein, build-up layers (130) built up over the front side of the die, and a power plane (140) in physical contact with the back side of the die. In another embodiment, the microelectronic package comprises a substrate (210), a first die (220) and a second die (260) embedded in the substrate and having a front side (221, 261) and a back side (222, 262) and a through-silicon-via (223, 263) therein, build-up layers (230) over the front sides of the first and second dies, and an electrically conductive structure (240) in physical contact with the back sides of the first and second dies.
摘要翻译：微电子封装包括衬底（110），嵌入衬底内的管芯（120），管芯具有前侧（121）和后侧（122）以及贯通硅通孔（123）在模具的前侧构建的升高层（130）和与模具的背面物理接触的动力平面（140）。在另一个实施例中，微电子封装包括衬底（210），嵌入衬底中的第一裸片（220）和第二裸片（260），并具有正面（221,261）和背面（222,262）和其中的穿硅通孔（223,263），在第一和第二模具的前侧上方的堆积层（230），以及与第一和第二模具的背面物理接触的导电结构（240）和第二个死亡。

10. 发明申请

WO2017123085A1 LITHOGRAPHIC DEFINED 3D LATERAL WIRING 审中-公开
标题翻译：光刻定义的3D横向布线
公开(公告)号：WO2017123085A1
公开(公告)日：2017-07-20
申请号：PCT/NL2017/050009
申请日：2017-01-09
申请人： TECHNISCHE UNIVERSITEIT DELFT
发明人： ESFAHANI, Zahra Kolahdouz , VAN ZEIJL, Hendrikus Wilhelmus , ZHANG, Guo Qi
IPC分类号： H01L21/60 , H01L23/48 , G03F7/16 , G03F7/09 , G03F7/20 , G03F9/00 , B05D1/00 , B05D1/02 , G03F7/30 , G03F7/00
CPC分类号： H01L24/82 , G03F7/0037 , G03F7/162 , G03F7/168 , G03F7/2022 , G03F7/70416 , H01L24/24 , H01L2224/24011 , H01L2224/24051 , H01L2224/24998 , H01L2224/2518 , H01L2224/73267 , H01L2224/82106 , H01L2224/82986 , H01L2224/8385 , H01L2924/10253 , H01L2924/12041 , H01L2924/14 , H01L2924/1461 , H01L2924/00014
摘要： The present invention is in the field of a semiconductor product having lithographic defined lateral wiring, a process fo making such a product, use of said process, and a chip or a chip in package having such wiring. In semiconductor processes functional electrical elements which need to be connected to an outside world by electrical conducting wires. The process used for lithographic defined lateral metal wiring in a package comprises the steps of providing a chip and a substrate, optionally placing the chip on the substrate, providing a passivation layer covering the chip, and providing openings in the passivation layer to metal pads.
摘要翻译：本发明属于具有光刻定义的横向布线的半导体产品领域，制造这种产品的工艺，所述工艺的用途以及具有这种布线的芯片或芯片封装。在半导体工艺中，需要通过电导线连接到外部世界的功能电子元件。用于封装中的光刻限定的横向金属布线的工艺包括以下步骤：提供芯片和衬底，可选地将芯片放置在衬底上，提供覆盖芯片的钝化层，以及将钝化层中的开口提供到金属焊盘。

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