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1. 发明申请

WO2017189074A1 INDEPENDENT MULTI-PLANE READ AND LOW LATENCY HYBRID READ 审中-公开
标题翻译：独立的多平面读取和低延时混合读取
公开(公告)号：WO2017189074A1
公开(公告)日：2017-11-02
申请号：PCT/US2017/018547
申请日：2017-02-19
申请人： SANDISK TECHNOLOGIES LLC
发明人： SHAH, Grishma , LI, Yan , CHEN, Jian , LOUIE, Kenneth , YANG, Nian Niles
IPC分类号： G11C16/26 , G11C11/56 , G11C16/04 , G11C7/10
CPC分类号： G11C7/1009 , G11C7/1015 , G11C7/1039 , G11C7/1063 , G11C11/56 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C2211/563 , G11C2216/20
摘要： Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading from selected word lines in the planes. In one approach, different types of read operations are performed in different planes, such as a multi-level cell read, e.g., a lower, middle or upper page read and a single-level cell (SLC) read. When the read operation in one plane uses fewer read voltages than another plane, the read data can be output early from the one plane while read operations continue on the other plane. The external controller can also command a cache release for one plane after outputting data from the caches of another plane. Read voltages can be set for each plane in a respective set of registers.
摘要翻译：
读取操作在多平面存储设备中执行。状态机将外部控制器连接到每个存储单元平面以允许从平面中的选定字线进行读取。在一种方法中，在不同平面中执行不同类型的读取操作，诸如多级单元读取，例如，较低，中间或较高页面读取和单级单元（SLC）读取。当一个平面中的读取操作使用比另一个平面更少的读取电压时，读取数据可以从一个平面提前输出，而读取操作在另一个平面上继续。在从另一个平面的高速缓存输出数据后，外部控制器也可以为一个平面命令缓存释放。读取电压可以为相应寄存器组中的每个平面设置。

2. 发明申请

WO2016014731A1 YUKAI VSL-BASED VT-COMPENSATION FOR NAND MEMORY 审中-公开
标题翻译： YUKAI基于VSL的NAND存储器的VT补偿
公开(公告)号：WO2016014731A1
公开(公告)日：2016-01-28
申请号：PCT/US2015/041636
申请日：2015-07-22
申请人： APLUS FLASH TECHNOLOGY, INC.
发明人： LEE, Peter, Wung
IPC分类号： G11C8/14 , G11C11/40 , G11C16/04
CPC分类号： G11C11/5635 , G11C7/14 , G11C7/18 , G11C11/56 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/14 , G11C16/24 , G11C16/26 , G11C16/3445 , G11C16/3459 , G11C29/50 , G11C2029/5002
摘要： A YUKAI NAND array comprising multiple strings associated with hierarchical global/local bit lines (GBL/LBL) and each string being associated with one LBL and having adjacent LBL as a dedicated local source line (LSL) without a common source line to connect all strings. Each of the LBLs is interleavingly associated with either an Odd or Even string selected via one pair of dummy cells inserted in each string and is used as one on-chip PCACHE register with full BL-shielding without wasting extra silicon area to allow batch- based multiple concurrent MLC All-BL, All-Vtn-Program and Alternative-WL program, Odd/Even read and verify operations with options of providing individual and common VSL-based Vt-compensation and VLBL compensations to mitigate high WL-WL and BL-BL coupling effects. Bias conditions in each string are provided to correctly sense highly-negative erase-verify voltage, multiple negative program-verify voltages and without VDS punch-through, breakdown and body-effect in both boundary and non-boundary WLs cells.
摘要翻译：包含与分级全局/局部位线（GBL / LBL）相关联的多个串的YUKAI NAND阵列，每个串与一个LBL相关联，并且具有相邻的LBL作为专用本地源线（LSL），而没有公共源线连接所有字符串。每个LBL与通过插入每个串中的一对虚拟单元选择的奇数或偶数字符串进行交织关联，并且被用作具有完全BL屏蔽的一个片上PCACHE寄存器，而不浪费额外的硅面积以允许基于批次多个并发的MLC全BL，全Vtn程序和替代WL程序，奇/偶读取和验证操作，具有提供单独和常见的基于VSL的Vt补偿和VLBL补偿的选项，以减轻高WL-WL和BL- BL耦合效应。提供每个串中的偏置条件以正确检测边界和非边界WL单元中的高负值擦除验证电压，多个负编程验证电压以及VDS穿透，击穿和体效应。

3. 发明申请

WO2015187800A1 SYSTEMS AND METHODS FOR ACOUSTIC WAVE ENABLED DATA STORAGE 审中-公开
标题翻译：声波波形数据存储的系统和方法
公开(公告)号：WO2015187800A1
公开(公告)日：2015-12-10
申请号：PCT/US2015/033936
申请日：2015-06-03
申请人： ELWHA LLC , DAVIDSON, Howard L. , PASCH, Nicholas F. , RUDDER, Eric D. , TEGREENE, Clarence T.
发明人： DAVIDSON, Howard L. , PASCH, Nicholas F. , RUDDER, Eric D. , TEGREENE, Clarence T. , BARNES, Philip Lionel , CHIN, Hon Wah , HALLMAN, Kimberly D.A. , HYDE, Roderick A. , ISHIKAWA, Muriel Y. , KARE, Jordin T. , LEE, Brian , LORD, Robert W. , MUNDIE, Craig J. , MYHRVOLD, Nathan P. , TREMBLAY, Marc , TUCKERMAN, David B. , WHITMER, Charles , WOOD, Lowell L., Jr.
IPC分类号： G11C13/00 , G11C7/10
CPC分类号： G11C19/00 , G11C7/10 , G11C8/005 , G11C11/56
摘要： The present disclosure provides systems and methods for storing, reading, and writing data using particle-based acoustic wave driven shift registers. The shift registers may physically shift particles along rows and/or columns of wells through the interactions of two parallel surfaces. A transducer may generate an acoustic wave to displace one or more of the two parallel surfaces. The particles may be transferred to and/or otherwise constrained by a buffer surface during at least a portion of the acoustic wave, such that the particles may be shifted during one or more cycles of the acoustic wave. In various embodiments, the amplitude of the acoustic wave may correspond to the spacing distance between each of the wells. The wells may be physical and/or potential wells.
摘要翻译：本公开提供了使用基于粒子的声波驱动移位寄存器来存储，读取和写入数据的系统和方法。移位寄存器可以通过两个平行表面的相互作用来物理地沿着井和/或列的井移动颗粒。换能器可以产生声波以移动两个平行表面中的一个或多个。在声波的至少一部分期间，颗粒可以被转移到和/或以其它方式被缓冲表面约束，使得在声波的一个或多个循环期间颗粒可能被移位。在各种实施例中，声波的幅度可以对应于每个孔之间的间隔距离。井可以是物理和/或潜在井。

4. 发明申请

WO2015167509A1 DIFFERENTIAL WRITING FOR LIFE EXTENSION OF PORTIONS OF A MEMORY DEVICE 审中-公开
标题翻译：用于存储器件的生命延长的差异写作
公开(公告)号：WO2015167509A1
公开(公告)日：2015-11-05
申请号：PCT/US2014/036085
申请日：2014-04-30
申请人： EMPIRE TECHNOLOGY DEVELOPMENT LLC
发明人： OH, Hyun Oh , KWAK, Jin Sam , SON, Ju Hyung
IPC分类号： G11C11/00 , G11C29/00 , G11C29/04
CPC分类号： G11C16/10 , G06F11/1076 , G11C11/56 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C16/349 , G11C29/50004 , G11C29/52
摘要： Technologies are generally described that relate to differential writing for life extension of portions of non-volatile memory that have a likelihood of error that satisfies a defined condition. An example method may include determining that at least two components of a memory device satisfy a defined condition; writing to a first component of the at least two components with first data having a first representation. The method may also include writing to a second component of the at least two components with second data having a second representation different from the first representation, wherein the second data comprises at least a portion that is bit inverted relative to the first data.
摘要翻译：通常描述涉及具有满足定义条件的错误可能性的非易失性存储器的部分的延长的差分写入的技术。示例性方法可以包括确定存储器件的至少两个部件满足定义的条件; 用具有第一表示的第一数据写入至少两个分量的第一分量。该方法还可以包括用具有不同于第一表示的第二表示的第二数据写入至少两个分量的第二分量，其中第二数据包括相对于第一数据被倒置的部分。

5. 发明申请

WO2015160330A1 RANK DETERMINATION 审中-公开
标题翻译：排名决定
公开(公告)号：WO2015160330A1
公开(公告)日：2015-10-22
申请号：PCT/US2014/034172
申请日：2014-04-15
申请人： EMPIRE TECHNOLOGY DEVELOPMENT LLC
发明人： MA, Yanjun , KAN, Edwin
IPC分类号： G11C7/06 , G11C7/14
CPC分类号： G11C16/26 , G11C7/08 , G11C7/1006 , G11C11/54 , G11C11/56 , G11C11/5621 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C13/0061 , G11C16/0408 , G11C16/0483 , G11C16/24 , G11C16/32 , G11C2211/5648
摘要： Technologies are generally provided for methods and circuitry to rank a large number of cells in a timeframe of about one sense cycle. In some examples, an architecture may be implemented to rank memory cells such as volatile memories, non-volatile memories, and other types of data storage devices, where there may not be an equivalent to threshold voltage. In other examples, an arbitrary group of circuits, such as in neural networks where there may not be an equivalent control gate to set the timing resolution, may be ranked. Relative sense timing may be used to rank the cells having different current carrying abilities. A ramped gate voltage may be used to control the timing resolution and to reduce contention between close separate cells. Digital logic may be used to latch and/or record the rank information.
摘要翻译：通常提供技术用于在大约一个感测周期的时间范围内对大量单元进行排序的方法和电路。在一些示例中，可以实施一种架构来对诸如易失性存储器，非易失性存储器和其他类型的数据存储设备之类的存储器单元进行排序，其中可能没有等效于阈值电压。在其他示例中，可以对任意组的电路进行排序，诸如在神经网络中，其中可能不存在用于设置定时分辨率的等效控制门。可以使用相对感测定时对具有不同载流能力的单元进行排序。可以使用斜坡栅极电压来控制时序分辨率并减少关闭分开的单元之间的竞争。数字逻辑可用于锁存和/或记录秩信息。

6. 发明申请

WO2014175877A1 REPRESENTING DATA USING A GROUP OF MULTILEVEL MEMORY CELLS 审中-公开
标题翻译：使用多组记忆细胞表示数据
公开(公告)号：WO2014175877A1
公开(公告)日：2014-10-30
申请号：PCT/US2013/037971
申请日：2013-04-24
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
发明人： YOON, Doe Hyun , CHANG, Jichuan , MURALIMANOHAR, Naveen , SCHREIBER, Robert , JOUPPI, Norman Paul
IPC分类号： G11C13/00 , G11C16/34 , G11C29/00 , G06F11/00
CPC分类号： G11C11/5678 , G06F11/073 , G06F11/0793 , G06F11/1004 , G06F11/1072 , G11C11/56 , G11C13/0004 , G11C13/0069 , G11C29/42 , G11C29/52 , G11C29/70 , G11C29/76 , G11C2211/5647
摘要： A memory device includes a group or block of k-level memory cells, where k > 2, and where each of the k-level memory cells has k programmable states represented by respective resistance levels.
摘要翻译：存储器件包括k级存储器单元的组或块，其中k≥2，并且其中每个k级存储器单元具有由各个电阻电平表示的k个可编程状态。

7. 发明申请

WO2014130586A1 COMPENSATION SCHEME FOR NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器的补偿方案
公开(公告)号：WO2014130586A1
公开(公告)日：2014-08-28
申请号：PCT/US2014/017217
申请日：2014-02-19
申请人： SANDISK 3D LLC
发明人： CHEN, Yingchang , KALRA, Pankaj , GORLA, Chandrasekhar
IPC分类号： G11C13/00
CPC分类号： G11C7/12 , G11C7/00 , G11C11/56 , G11C11/5678 , G11C13/00 , G11C13/0004 , G11C13/0023 , G11C13/0038 , G11C13/0069 , G11C2013/0076
摘要： Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.
摘要翻译：描述了在存储器阵列中的存储器单元的读取和/或写入期间执行并行电压和电流补偿的方法。在一些实施例中，补偿可以包括基于与存储器单元相关联的存储器阵列区域，位线层和存储器单元方向来调整施加到存储器单元的位线电压和/或位线参考电流。补偿可以包括根据存储器单元特定特性来调整每个存储器单元上的位线电压和/或位线参考电流。在一些实施例中，用于读取和/或写入存储器单元的读/写电路可以根据存储器单元是否被表征为存储单元来选择要施加到存储器单元的多个位线电压选项中的位线电压强，弱或典型的记忆体。

8. 发明申请

WO2014100749A3 A MULTI-LEVEL MEMORY ARRAY HAVING RESISTIVE ELEMENTS FOR MULTI-BIT DATA STORAGE 审中-公开
标题翻译：具有用于多位数据存储的有效元件的多级存储器阵列
公开(公告)号：WO2014100749A3
公开(公告)日：2014-08-14
申请号：PCT/US2013077276
申请日：2013-12-20
申请人： TOSHIBA KK , SANDISK 3D LLC , INTERMOLECULAR INC
发明人： PRAMANIK DIPANKAR , LAZOVSKY DAVID , MINVIELLE TIM , YAMAGUCHI TAKESHI
IPC分类号： H01L47/00 , G11C11/00
CPC分类号： G11C11/56 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/12 , G11C7/22 , G11C11/5685 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2213/32 , G11C2213/33 , G11C2213/34 , G11C2213/72 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L45/145 , H01L45/1608
摘要： A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device. In one configuration, by connecting each memory cell or device with at least one resistor array, a resistive switching layer found in the resistive switching memory element of the connected memory device is capable of being at multiple resistance states for storing multiple bits of digital information. During device programming operations, when a desired series combination of the resistive elements within the resistor array is selected, the resistive switching layer in the connected memory device can be in a desired resistance state.
摘要翻译：提供一种用于多位数据存储的电阻器阵列，不需要增加存储器芯片的尺寸或缩小存储器芯片内包含的存储器单元的特征尺寸。电阻器阵列包含多个分立的电阻元件，以不同的串联组合选择性地连接到至少一个存储器单元或存储器装置。在一种配置中，通过将每个存储器单元或器件与至少一个电阻器阵列连接，在所连接的存储器器件的电阻切换存储器元件中找到的电阻切换层能够处于多个电阻状态以存储多位数字信息。在器件编程操作期间，当选择电阻器阵列内的电阻元件的期望的串联组合时，所连接的存储器器件中的电阻切换层可处于期望的电阻状态。

9. 发明申请

WO2014110331A1 THREE OR MORE RESISTIVE STATE RANDOM ACCESS MEMORY CELL 审中-公开
标题翻译：三个或更多电阻状态随机存取存储器单元
公开(公告)号：WO2014110331A1
公开(公告)日：2014-07-17
申请号：PCT/US2014/010986
申请日：2014-01-10
申请人： INTERMOLECULAR, INC. , KABUSHIKI KAISHA TOSHIBA , SANDISK 3D LLC
发明人： HASHIM, Imran , CLARKE, Ryan C. , LU, Nan , MINVIELLE, Tim , YAMAGUCHI, Takeshi
IPC分类号： G11C13/00
CPC分类号： H01L45/146 , G11C11/56 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C2213/32 , G11C2213/71 , G11C2213/77 , H01L45/08 , H01L45/1233 , H01L45/1253
摘要： Provided are resistive random access memory (ReRAM) cells, each having three or more resistive states and being capable of storing multiple bits of data, as well as methods of fabricating and operating such ReRAM cells. Such ReRAM cells or, more specifically, their resistive switching layer have wide range of resistive states and are capable of being very conductive (e.g., about 1 kOhm) in one state and very resistive (e.g., about 1MOhm) in another state. In some embodiments, a resistance ratio between resistive states may be between 10 and 1,000 even up to 10,000. The resistive switching layers also allow establishing stable and distinct intermediate resistive states that may be assigned different data values. These layers may be configured to switching between their resistive states using fewer programming pulses than conventional systems by using specific materials, switching pluses, and resistive state threshold.
摘要翻译：提供了电阻随机存取存储器（ReRAM）单元，每个单元具有三个或更多个电阻状态，并且能够存储多个数据位，以及制造和操作这样的ReRAM单元的方法。这样的ReRAM单元，或者更具体地说，它们的电阻式开关层具有宽范围的电阻状态，并且在一种状态下能够非常导电（例如，大约1kOhm），并且在另一种状态下具有很强的电阻（例如约1MOhm）。在一些实施例中，电阻状态之间的电阻比可以在10和1,000之间甚至高达10,000。电阻式开关层还允许建立可分配不同数据值的稳定和不同的中间电阻状态。这些层可以被配置为使用比常规系统更少的编程脉冲在其电阻状态之间切换，通过使用特定的材料，开关和电阻状态阈值。

10. 发明申请

WO2013101050A1 MULTI-LEVEL MEMORY WITH DIRECT ACCESS 审中-公开
标题翻译：具有直接访问的多级记忆
公开(公告)号：WO2013101050A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067824
申请日：2011-12-29
申请人： INTEL CORPORATION , FANNING, Blaise , QAWAMI, Shekoufeh , TETRICK, Raymond S. , HADY, Frank T.
发明人： FANNING, Blaise , QAWAMI, Shekoufeh , TETRICK, Raymond S. , HADY, Frank T.
IPC分类号： G06F12/00 , G11C13/02 , G11C16/00
CPC分类号： G06F3/0644 , G06F3/0604 , G06F3/0631 , G06F3/0679 , G06F3/0688 , G06F12/023 , G06F12/0238 , G06F12/0246 , G06F12/08 , G06F12/10 , G06F12/1009 , G06F2212/2024 , G06F2212/205 , G06F2212/7201 , G06F2212/7204 , G11C7/1006 , G11C11/56 , G11C16/00 , Y02D10/13
摘要： Embodiments of a method, device, and system for implementing multi-level memory with direct access are disclosed. In one embodiment, the method includes designating an amount of a non-volatile random access memory (NVRAM) in a computer system to be utilized as a memory alternative for a dynamic random access memory (DRAM). The method continues by designating a second amount of the NVRAM to be utilized as a storage alternative for a mass storage device. Then the method re-designates at least a first portion of the first amount of NVRAM from the memory alternative designation to the storage alternative designation during operation of the computer system. Finally, the method re-designates at least a first portion of the second amount of NVRAM from the storage alternative designation to the memory alternative designation during operation of the computer system.
摘要翻译：公开了用于实现具有直接访问的多级存储器的方法，设备和系统的实施例。在一个实施例中，该方法包括指定要用作动态随机存取存储器（DRAM）的存储器备选方案的计算机系统中的非易失性随机存取存储器（NVRAM）的量。该方法通过指定要用作大容量存储设备的存储备用的第二数量的NVRAM来继续。然后，该方法在计算机系统的操作期间将存储器备选指定中的第一数量的NVRAM的至少第一部分重新指定为存储备选指定。最后，该方法在计算机系统的操作期间将第二数量的NVRAM的至少第一部分从存储替代指定重新指定到存储器备选指定。

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