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1. 发明申请

WO2017074589A1 SYSTEMS AND METHODS TO COMPENSATE FOR THRESHOLD VOLTAGE SHIFTS 审中-公开
标题翻译：用于补偿阈值电压偏移的系统和方法
公开(公告)号：WO2017074589A1
公开(公告)日：2017-05-04
申请号：PCT/US2016/051810
申请日：2016-09-15
申请人： SANDISK TECHNOLOGIES LLC
发明人： SHARON, Eran , ALROD, Idan , DUTTA, Deepanshu
IPC分类号： G11C7/04 , G11C16/26 , G11C16/34 , G11C11/56
CPC分类号： G11C16/3404 , G06F11/1068 , G11C7/04 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C16/3418 , G11C16/3436 , G11C16/3459 , G11C16/349 , G11C29/52
摘要： A data storage device includes a memory including multiple storage elements. The data storage device also includes circuitry configured to determine, for a particular storage element of the multiple storage elements, an indicator associated with a threshold voltage temperature dependence (TVTD) of the particular storage element.
摘要翻译：数据存储设备包括包含多个存储元件的存储器。数据存储设备还包括被配置为针对多个存储元件中的特定存储元件确定与特定存储元件的阈值电压温度依赖性（TVTD）相关联的指示符的电路。

2. 发明申请

WO2017014860A1 PROCESSING SHAPED DATA 审中-公开
标题翻译：处理形状数据
公开(公告)号：WO2017014860A1
公开(公告)日：2017-01-26
申请号：PCT/US2016/037035
申请日：2016-06-10
申请人： SANDISK TECHNOLOGIES LLC
发明人： ACHTENBERG, Stella , SHARON, Eran
IPC分类号： G06F11/10
CPC分类号： G06F3/0644 , G06F3/0614 , G06F3/0679 , G06F11/1012 , G11C11/5621 , G11C16/3459 , G11C16/349
摘要： Systems and methods of processing shaped data to include selectively performing a modification operation. The modification operation may be performed in response to determining that shaped data satisfies one or more shaping adjustment criteria. Shaping of data may be discontinued to at least a portion of a memory based on a health metric for the portion satisfying a threshold.
摘要翻译：处理形状数据的系统和方法包括选择性地执行修改操作。可以响应于确定成形数据满足一个或多个成形调整标准来执行修改操作。基于满足阈值的部分的健康度量，数据的整形可以停止到存储器的至少一部分。

3. 发明申请

WO2016130193A1 REDUCED CURRENT PROGRAM VERIFY IN NON-VOLATILE MEMORY 审中-公开
标题翻译：减少非易失性存储器中的当前程序验证
公开(公告)号：WO2016130193A1
公开(公告)日：2016-08-18
申请号：PCT/US2015/062626
申请日：2015-11-25
申请人： SanDisk Technologies LLC
发明人： LAI, Chun-Hung , LEE, Shih-Chung
IPC分类号： G11C16/34
CPC分类号： G11C16/3459 , G11C11/5642 , G11C11/5671 , G11C16/0475 , G11C16/0483 , G11C16/3413 , G11C16/3427 , G11C2211/5621
摘要： Reducing peak current and/or power consumption during verify of a non-volatile memory is disclosed. During a program verify, only memory cells in a first physical segment of the selected word line are verified during an initial program loop; memory cells in a different physical segment of the word line are locked out and not verified. The locked out memory cells may be slower to program. During a later program loop, memory cells in all physical segments are program verified. Locked out strings do not conduct a significant current during verify, thus reducing current/power consumption.
摘要翻译：公开了在验证非易失性存储器期间降低峰值电流和/或功率消耗。在程序验证期间，在初始程序循环期间仅验证所选字线的第一物理段中的存储单元; 字线的不同物理段中的存储单元被锁定并未被验证。锁定的存储单元可能较慢编程。在稍后的程序循环中，所有物理段中的存储单元都被程序验证。锁定字符串在验证期间不会导致显着的电流，从而降低电流/功耗。

4. 发明申请

WO2016053544A1 MODIFYING PROGRAM PULSES BASED ON INTER-PULSE PERIOD TO REDUCE PROGRAM NOISE 审中-公开
标题翻译：基于脉冲周期修改程序脉冲以减少程序噪声
公开(公告)号：WO2016053544A1
公开(公告)日：2016-04-07
申请号：PCT/US2015/047808
申请日：2015-08-31
申请人： SANDISK TECHNOLOGIES INC.
发明人： DONG, Yingda , PANG, Liang , YUAN, Jiahui
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0466 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： Techniques are provided for more accurately programming memory cells by reducing program noise caused by charge loss in a programming pass in which the number of verify tests varies in different program loops. In an nth program loop, at least one programming characteristic is modified based on the number (N) of data states which were subject to verify tests in the n-1st program loop. For example, a reduced step size or pulse duration, or an elevated bit line voltage (Vbl) can be used. The reduction in the step size or pulse duration, or the increase in Vbl, is proportional to N. The modification of the at least one programming characteristic results in a slowdown of the programming of the memory cells so that program noise is reduced.
摘要翻译：提供了通过减少在不同程序循环中验证测试数量变化的编程通过中的电荷损失引起的程序噪声来提供更精确地编程存储器单元的技术。在第n个程序循环中，基于在第n-1程序循环中进行验证测试的数据状态数（N）来修改至少一个编程特性。例如，可以使用减小的步长或脉冲持续时间，或升高的位线电压（Vbl）。步长或脉冲持续时间的减小或Vbl的增加与N成比例。至少一个编程特性的修改导致存储器单元的编程减慢，从而减少编程噪声。

5. 发明申请

WO2016048846A1 SELF-TIMED SLC NAND PIPELINE AND CONCURRENT PROGRAM WITHOUT VERIFICATION 审中-公开
标题翻译：自定义SLC NAND管道和并行程序，无需验证
公开(公告)号：WO2016048846A1
公开(公告)日：2016-03-31
申请号：PCT/US2015/051100
申请日：2015-09-18
申请人： APLUS FLASH TECHNOLOGY, INC
发明人： LEE, Peter, Wung
IPC分类号： G11C16/34
CPC分类号： G11C16/10 , G11C16/0408 , G11C16/0466 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/32 , G11C16/3459
摘要： A hierarchical-GBL/LBL NAND array with a plurality of LG and MG groups in either orthogonal BL/CSL scheme or parallel BL/SL scheme including a plurality of block-decoders with a shared self-timed delay control circuit and a plurality of fully-shielding dynamic CACHE registers made of 2 local broken metal lines within the array and DRAM-like SA is provided. Each DCR capacitor is flexibly expandable by connecting multiple C LG s made by the local broken metal lines of the LGs to form a C MG of a larger MG. Based on the NAND array, multiple randomly selected WLs in multiple random blocks within multiple random LGs within one MG can be selected on basis of one WL per block per LG for performing an ABL pipeline and concurrent SLC program without verification, and on basis of one WL per block per MG for performing an ABL-like or HBL pipeline and concurrent SLC read.
摘要翻译：具有正交BL / CSL方案中的多个LG和MG组的分层GBL / LBL NAND阵列或并行BL / SL方案，包括具有共享自定时延迟控制电路的多个块解码器和多个完全提供了由阵列中的2个本地断开金属线构成的动态CACHE寄存器，并且提供类DRAM。每个DCR电容器通过连接由LG的本地破碎金属线制成的多个CLG来形成更大的MG的CMG，可以灵活地扩展。基于NAND阵列，可以基于每个LG的每个块的一个WL来选择在一个MG内的多个随机LG内的多个随机块中的多个随机选择的WL，用于执行ABL流水线和并行SLC程序而不进行验证，并且基于一个每GB的每个块的WL用于执行ABL类型或HBL流水线并行SLC读取。

6. 发明申请

WO2016028717A1 VSL-BASED VT-COMPENSATION AND ANALOG PROGRAM SCHEME FOR NAND ARRAY WITHOUT CSL 审中-公开
标题翻译：基于VSL的VT补偿和不具有CSL的NAND阵列的模拟程序方案
公开(公告)号：WO2016028717A1
公开(公告)日：2016-02-25
申请号：PCT/US2015/045580
申请日：2015-08-17
申请人： APLUS FLASH TECHNOLOGY, INC
发明人： PETER, Wung, Lee
IPC分类号： G11C8/14 , G11C11/40 , G11C16/04
CPC分类号： G11C11/5635 , G11C7/18 , G11C11/5642 , G11C11/5671 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/3427 , G11C16/3459 , G11C2207/2245 , G11C2211/5641
摘要： A YUKAI NAND array comprising multiple strings of all TLC and mixed TLC+SLC memory cells associated with hierarchical global/local bit lines (GBL/LBL) and each string being associated with one LBL and having adjacent LBL as a dedicated local source line (LSL) with full BL-shielding without wasting extra silicon area and without a common source line to connect all strings. Each of the LBLs is interleavingly associated with either an Odd or Even string selected via one pair of dummy cells inserted in each string and is used as one on-chip PCACHE register with full BL-shielding to perform concurrent ABL, AnP and Alt-WL program under multi-passes program schemes with LBL program voltage compensations and half-BL Odd/Even program-verify and read operations with individual V SL -based Vt-compensation to mitigate high WL-WL and BL-BL coupling effects.
摘要翻译： YUKAI NAND阵列包括与分层全局/局部位线（GBL / LBL）相关联的所有TLC和混合TLC + SLC存储器单元的多个串，每个串与一个LBL相关联并且具有相邻的LBL作为专用本地源极线（LSL ）具有完全的BL屏蔽，而不浪费额外的硅面积，没有通用的源极线连接所有的串。每个LBL与通过插入每个串中的一对虚拟单元选择的奇数或偶数字符串进行交织关联，并且用作具有完全BL屏蔽的一个片上PCACHE寄存器，以执行并行ABL，AnP和Alt-WL 在具有LBL程序电压补偿和半BL奇偶校验和读取操作的多通程序方案下使用单独的基于VSL的Vt补偿来减轻WL-WL和BL-BL耦合效应。

7. 发明申请

WO2016010829A1 REPROGRAMMING MEMORY WITH SINGLE PROGRAM PULSE PER DATA STATE 审中-公开
标题翻译：具有每个数据状态的单程序脉冲的重现存储器
公开(公告)号：WO2016010829A1
公开(公告)日：2016-01-21
申请号：PCT/US2015/039829
申请日：2015-07-09
申请人： SANDISK TECHNOLOGIES INC.
发明人： PANG, Liang , DONG, Yingda
IPC分类号： G11C11/56 , G11C16/10 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3459 , G11C2211/5621 , H01L27/1157 , H01L27/11582
摘要： Techniques are provided for programming memory cells while reducing the effects of detrapping which cause a downshift in the threshold voltage distribution. Detrapping is particularly problematic for charge-trapping memory cells such as in a 3D stacked non-volatile memory device. After completion of a full programming pass, a verify test is performed to identify cells for which reprogramming is warranted. The reprogramming includes a single program pulse for each target data state, where each program pulse is longer than in the full programming pass. The pulse widths can be optimized based on factors such as a programming speed or a threshold voltage distribution width from the full programming pass.
摘要翻译：提供了用于对存储器单元进行编程的技术，同时减少了导致阈值电压分布中的降档的去饱和效应。解扣对于诸如在3D堆叠的非易失性存储器件中的电荷捕获存储器单元是特别有问题的。完成完整的编程通行后，执行验证测试以识别需要重新编程的单元格。重编程包括用于每个目标数据状态的单个编程脉冲，其中每个编程脉冲比在完整编程遍期间更长。脉冲宽度可以根据编程速度或来自完整编程遍的阈值电压分布宽度等因素进行优化。

8. 发明申请

WO2015134702A1 COMPENSATING SOURCE SIDE RESISTANCE VERSUS WORD LINE 审中-公开
标题翻译：补偿源电阻VERSUS字线
公开(公告)号：WO2015134702A1
公开(公告)日：2015-09-11
申请号：PCT/US2015/018875
申请日：2015-03-05
申请人： SANDISK TECHNOLOGIES INC.
发明人： TSENG, Huai-Yuan , LEE, Dana , LEE, Shih-Chung , DUTTA, Deepanshu , HAZEGHI, Arash
IPC分类号： G11C16/04
CPC分类号： G11C16/28 , G11C16/0483 , G11C16/3459
摘要： A method and non-volatile storage system are provided in which the voltage applied to the source end of a NAND string depends on the location of the non-volatile storage element that is selected for sensing. This may be done without body-biasing the NAND string. Having the magnitude of the voltage applied to the source end of a NAND string depend on the location of the selected memory cell (without any body biasing) helps to mitigate failures that are dependent on which word line is selected during a sensing operation of one embodiment. Additionally, the magnitude of a read pass voltage may depend on either the source line voltage or the location of the selected memory cell.
摘要翻译：提供了一种方法和非易失性存储系统，其中施加到NAND串的源极的电压取决于被选择用于感测的非易失性存储元件的位置。这可以在不对NAND串进行体偏置的情况下完成。施加到NAND串的源极的电压的大小取决于所选择的存储器单元的位置（没有任何主体偏置）有助于减轻依赖于在一个实施例的感测操作期间选择哪个字线的故障。另外，读通道电压的幅度可以取决于源极线电压或所选存储器单元的位置。

9. 发明申请

WO2015127713A1 一种非易失性存储器的擦除方法和装置审中-公开
公开(公告)号：WO2015127713A1
公开(公告)日：2015-09-03
申请号：PCT/CN2014/076147
申请日：2014-04-24
申请人：北京兆易创新科技股份有限公司
发明人：胡洪 , 王林凯
IPC分类号： G11C16/14
CPC分类号： G11C16/3459 , G11C16/107 , G11C16/14 , G11C16/16 , G11C16/28 , G11C16/3436 , G11C16/3477
摘要：申请一种非易失性存储器的擦除方法和装置，以解决目前的擦除操作造成不必要的时间开销，过程较为复杂的问题。其中，方法包括：在接收到擦除指令后，对所述擦除指令对应的目标擦除区域执行预读校验；若所述预读校验通过，则对所述目标擦除区域执行擦除操作；若所述预读校验未通过，则对所述目标擦除区域执行预编程校验，并在所述预编程校验通过后，对所述目标擦除区域执行擦除操作。本申请可以保证在擦除操作之前目标擦除区域处于全擦除状态的情况下，不再执行不必要的预编程校验过程，节省擦除时间，擦除过程更加简单。

10. 发明申请

WO2015065828A1 WORD LINE COUPLING FOR DEEP PROGRAM-VERIFY, ERASE-VERIFY AND READ 审中-公开
标题翻译： WORD LINE COUPLING FOR DEEP PROGRAM-VERIFY，ERASE-VERIFY AND READ
公开(公告)号：WO2015065828A1
公开(公告)日：2015-05-07
申请号：PCT/US2014/062125
申请日：2014-10-24
申请人： SANDISK TECHNOLOGIES INC.
发明人： WAN, Jun , PAN, Feng , LEI, Bo
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/3427 , G11C16/3445 , G11C16/3459
摘要： In a non-volatile storage system, a reduced voltage is provided on a selected word line during a sensing operation, using down coupling. Voltages of one or more adjacent word lines of a selected word line are driven down while a voltage of the selected word line is floated. Capacitive coupling from the one or more adjacent word lines to the selected word line reduces the voltage of the selected word line. The capacitive coupling can be provided during a read, a program-verify test or an erase-verify test. The erase-verify test can be performed on cells of even-numbered word lines while capacitive coupling is provided by odd-numbered word lines, or on cells of odd-numbered word lines while capacitive coupling is provided by even-numbered word lines. Voltages of non-adjacent word lines can be provided at fixed, pass voltage levels.
摘要翻译：在非易失性存储系统中，使用向下耦合，在感测操作期间在所选字线上提供降低的电压。所选字线的一个或多个相邻字线的电压在选定字线的电压浮动的同时被驱动。从所述一个或多个相邻字线到所选字线的电容耦合降低了所选字线的电压。可以在读取，程序验证测试或擦除验证测试期间提供电容耦合。在偶数字线提供电容耦合的情况下，可以对偶数字线的单元执行擦除验证测试，或者在偶数字线提供电容耦合的情况下，对奇数字线提供电容耦合，或在奇数字线的单元上进行擦除验证测试。可以以固定的通过电压电平提供非相邻字线的电压。

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