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1. 发明申请

WO2018232089A1 EXTENT-BASED DATA LOCATION TABLE MANAGEMENT 审中-公开
公开(公告)号：WO2018232089A1
公开(公告)日：2018-12-20
申请号：PCT/US2018/037497
申请日：2018-06-14
申请人： BURLYWOOD, LLC
发明人： HABBINGA, Erik , EARHART, Tod Roland , KOCH, Nathan , PRUETT, David Christopher , SLATTERY, John
IPC分类号： G06F3/06
CPC分类号： G06F3/0644 , G06F3/0608 , G06F3/061 , G06F3/0629 , G06F3/0631 , G06F3/0671 , G06F3/0679 , G06F12/0292
摘要： A storage controller (130) is provided. The storage controller includes a host interface (121), a media interface (125), and a processing system (122) coupled with the host interface and the media interface. The processing system is configured to configured to maintain a translation table (124) that relates logical addressing to physical blocks of the one or more storage media (150) using at least an extents-based scheme in the translation table to relate the logical addressing to the physical blocks, wherein the extents-based scheme comprises a starting location combined with span length of a sequential portion of data stored on the one or more storage media, and the processing system also configured to handle storage operations of the storage drive in accordance with the translation table.

2. 发明申请

WO2018063719A1 SUPPORTING OVERSUBSCRIPTION OF GUEST ENCLAVE MEMORY PAGES 审中-公开
标题翻译：支持访客留言记录页的过度记录
公开(公告)号：WO2018063719A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/049431
申请日：2017-08-30
申请人： INTEL CORPORATION
发明人： LESLIE-HURD, Rebekah M. , MCKEEN, Francis X. , ROZAS, Carlos V. , NEIGER, Gilbert , MALLICK, Asit K. , ANATI, Ittai , ALEXANDROVICH, Ilya , SHANBHOGUE, Vedvyas , CHAKRABARTI, Somnath
IPC分类号： G06F21/53 , G06F9/455
CPC分类号： G06F3/0631 , G06F3/0604 , G06F3/064 , G06F3/0664 , G06F3/0665 , G06F3/0673 , G06F9/45558 , G06F2009/45583
摘要： Implementations of the disclosure provide for supporting oversubscription of guest enclave memory pages. In one implementation, a processing device comprising a memory controller unit to access a secure enclave and a processor core, operatively coupled to the memory controller unit. The processing device is to identify a target memory page in memory. The target memory page is associated with a secure enclave of a virtual machine (VM). A data structure comprising context information corresponding to the target memory page is received. A state of the target memory page is determined based on the received data structure. The state indicating whether the target memory page is associated with at least one of: a child memory page or a parent memory page of the VM. Thereupon, an instruction to evict the target memory page from the secure enclave is generated based on the determined state.
摘要翻译：本公开的实施方式提供支持访客飞地存储器页面的超额预订。在一个实现中，处理设备包括用于访问安全区域的存储器控制器单元和可操作地耦合到存储器控制器单元的处理器核心。处理设备将识别存储器中的目标存储器页面。目标内存页面与虚拟机（VM）的安全区域相关联。接收包括对应于目标存储器页面的上下文信息的数据结构。目标存储器页面的状态基于接收到的数据结构来确定。指示目标存储器页面是否与VM的子存储器页面或父存储器页面中的至少一个相关联的状态。于是，基于确定的状态产生从安全区域驱逐目标存储器页面的指令。

3. 发明申请

WO2018052551A1 MANAGING DATA FLOW IN HETEROGENEOUS COMPUTING 审中-公开
标题翻译：管理非均匀计算中的数据流
公开(公告)号：WO2018052551A1
公开(公告)日：2018-03-22
申请号：PCT/US2017/044601
申请日：2017-07-31
申请人： QUALCOMM INCORPORATED
发明人： ZHAO, Han , RAMAN, Arun , NATARAJAN, Aravind
IPC分类号： G06F9/52 , G06F9/54 , H04N21/44
CPC分类号： G06F3/0613 , G06F3/0631 , G06F3/0656 , G06F3/0685 , G06F9/52 , G06F9/544 , G06F12/0811 , G06F12/084 , G06F12/0855 , G06F2212/283 , G06F2212/314
摘要： Embodiments include computing devices, apparatus, and methods implemented by the apparatus for implementing data flow management on a computing device. Embodiment methods may include initializing a buffer partition of a first memory of a first heterogeneous processing device for an output of execution of a first iteration of a first operation by the first heterogeneous processing device on which a first iteration of a second operation assigned for execution by a second heterogeneous processing device depends. Embodiment methods may include identifying a memory management operation for transmitting the output by the first heterogeneous processing device from the buffer partition as an input to the second heterogeneous processing device. Embodiment methods may include allocating a second memory for storing data for an iteration executed by a third heterogeneous processing device to minimize a number of memory management operations for the second allocated memory.
摘要翻译：实施例包括由用于在计算设备上实现数据流管理的装置实现的计算设备，装置和方法。实施例方法可以包括初始化第一异构处理设备的第一存储器的缓冲器分区以执行由第一异构处理设备执行第一操作的第一次迭代的输出，第一异质处理设备在第一异质处理设备上执行第二次操作的第一次迭代，第二异构处理设备依赖于。实施例方法可以包括识别用于由第一异构处理设备从缓冲分区发送输出作为到第二异构处理设备的输入的存储器管理操作。实施例方法可包括分配第二存储器以存储由第三异构处理设备执行的迭代的数据，以最小化第二分配存储器的存储器管理操作的数量。

4. 发明申请

WO2017176256A1 UNMAP TO INITIALIZE SECTORS 审中-公开
标题翻译：发展部门初始化部门
公开(公告)号：WO2017176256A1
公开(公告)日：2017-10-12
申请号：PCT/US2016/026018
申请日：2016-04-05
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： NAZARI, Siamak , EVANS, Thomas David , HINDI, Faris , HARBAUGH, Daniel Aaron , AFKHAM, Anahita
IPC分类号： G06F3/06
CPC分类号： G06F12/0253 , G06F3/061 , G06F3/0616 , G06F3/0631 , G06F3/0632 , G06F3/0638 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F2212/7201 , G06F2212/7209
摘要： Examples disclosed herein relate to unmapping sectors of a solid-state drive to initialize the sectors. The sectors include a data portion and a protection portion. In one example, when an unmapped sector is read, the solid-state drive can return a pre-set value for the sector, where the pre-set value includes a known fixed value to represent the protection portion. In one example, a subset of the sectors is unmapped to initialize the subset. In one example, when read, a storage controller can recognize the known fixed value.
摘要翻译：这里公开的示例涉及解映射固态驱动器的扇区以初始化扇区。扇区包括数据部分和保护部分。在一个示例中，当读取未映射的扇区时，固态驱动器可以返回该扇区的预设值，其中该预设值包括已知的固定值以表示保护部分。在一个示例中，扇区的子集未被映射以初始化该子集。在一个例子中，当读取时，存储控制器可以识别已知的固定值。

5. 发明申请

WO2017165327A1 MEMORY SHARING FOR WORKING DATA USING RDMA 审中-公开
标题翻译：使用RDMA进行工作数据的内存共享
公开(公告)号：WO2017165327A1
公开(公告)日：2017-09-28
申请号：PCT/US2017/023273
申请日：2017-03-21
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： DAS, Sudipto , LI, Feng , SYAMALA, Manoj A. , NARASAYYA, Vivek R.
IPC分类号： G06F9/50 , G06F9/54
CPC分类号： G06F15/17331 , G06F3/061 , G06F3/0631 , G06F3/0653 , G06F3/067 , G06F9/5016 , G06F9/54 , G06F12/023 , G06F2209/509 , G06F2212/1016 , G06F2212/163 , G06F2212/254 , G06F2212/263 , G06F2212/264
摘要： A server system may include a cluster of multiple computers that are networked for high-speed data communications. Each of the computers has a remote direct memory access (RDMA) network interface to allow high-speed memory sharing between computers. A relational database engine of each computer is configured to utilize a hierarchy of memory for temporary storage of working data, including in order of decreasing access speed (a) local main memory, (b) remote memory accessed via RDMS, and (c) mass storage. The database engine uses the local main memory for working data, and additionally uses the RDMA accessible memory for working data when the local main memory becomes depleted. The server system may include a memory broker to which individual computers report their available or unused memory, and which leases shared memory to requesting computers.
摘要翻译：服务器系统可以包括为了高速数据通信而联网的多个计算机的集群。每台计算机都有一个远程直接内存访问（RDMA）网络接口，以允许在计算机之间共享高速内存。每台计算机的关系数据库引擎被配置为利用存储器层次结构临时存储工作数据，包括按照降低访问速度的顺序（a）本地主存储器，（b）通过RDMS访问的远程存储器，以及（c）存储。数据库引擎使用本地主内存作为工作数据，并在本地主内存耗尽时使用RDMA可访问的内存作为工作数据。服务器系统可以包括内存代理，各个计算机向其报告其可用或未使用的内存，并将共享内存租赁给请求的计算机。

6. 发明申请

WO2017138938A1 NOTIFICATIONS IN STORAGE ARRAYS 审中-公开
标题翻译：存储阵列中的通知
公开(公告)号：WO2017138938A1
公开(公告)日：2017-08-17
申请号：PCT/US2016/017434
申请日：2016-02-11
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： AGARWAL, Vivek , MOHAN, Rupin T. , PUTTAGUNTA, Krishna
IPC分类号： G06F3/06 , G06F13/42
CPC分类号： G06F3/0605 , G06F3/0631 , G06F3/0689
摘要： An example system that includes a storage system controller to control a storage array. The storage system controller is to generate, in response to a logical unit change in the storage array, an in-band state change notification that includes in its payload an application-level-rescan-required notification.
摘要翻译：
一个包含存储系统控制器以控制存储阵列的示例系统。存储系统控制器响应于存储阵列中的逻辑单元改变而生成带内状态改变通知，该通知在其有效载荷中包括需要应用级重新扫描的通知。

7. 发明申请

WO2017131828A1 PLACING WORKLOADS IN A MULTI-ARRAY SYSTEM 审中-公开
标题翻译：在多阵列系统中布置工作负载
公开(公告)号：WO2017131828A1
公开(公告)日：2017-08-03
申请号：PCT/US2016/059789
申请日：2016-10-31
申请人： PURE STORAGE, INC.
发明人： BOROWIEC, Benjamin , NOONAN, Terrence
IPC分类号： G06F3/06
CPC分类号： G06F9/5016 , G06F3/0604 , G06F3/0631 , G06F3/0653 , G06F3/067
摘要： Placing workloads in a multi-array system comprising a plurality of storage arrays, including: determining, for each of a plurality of storage arrays, a current system activity level trend of the storage array; receiving a performance profile of a workload to be executed on one of the storage arrays; generating, for each of the plurality of storage arrays in dependence upon the current system activity level trend of the storage array and the performance profile of the workload, a projected system activity level trend for the storage array; identifying, in dependence upon the projected system activity level trend for each of the plurality of storage arrays, an optimal storage array for receiving the workload; and placing the workload on the optimal storage array.
摘要翻译：将工作负载放置在包括多个存储阵列的多阵列系统中，包括：为多个存储阵列中的每一个确定存储阵列的当前系统活动级别趋势; 接收要在所述存储阵列之一上执行的工作负载的性能简档; 根据存储阵列的当前系统活动级别趋势和工作负载的性能简档，为多个存储阵列中的每一个生成存储阵列的投影系统活动级别趋势; 根据所述多个存储阵列中的每个存储阵列的所预测的系统活动水平趋势来识别用于接收所述工作量的最佳存储阵列; 并将工作负载放在最佳的存储阵列上。

8. 发明申请

WO2017117265A1 STORAGE SYSTEM INTERFACE 审中-公开
标题翻译：存储系统接口
公开(公告)号：WO2017117265A1
公开(公告)日：2017-07-06
申请号：PCT/US2016/068961
申请日：2016-12-28
申请人： NETAPP, INC.
发明人： McGIVERIN, Brian, Joseph , MORRISSEY, Christopher, Michael , SARISKY, Daniel, Andrew , LOLAYEKAR, Santosh, C.
IPC分类号： G06F3/06
CPC分类号： G06F3/0604 , G06F3/0631 , G06F3/0644 , G06F3/0653 , G06F3/067 , G06F9/00
摘要： A request to generate a storage system model is received. The storage system model represents at least a portion of a storage system. In response to receiving the request, a storage system interface configuration is loaded. The storage system interface configuration comprises an attribute of an entity model. The attribute corresponds to an attribute of a storage system entity of the storage system. Further in response to receiving the request, the entity model is identified as representing the storage system entity. In response to identifying the entity model as representing the storage system entity, the entity model is instantiated.
摘要翻译：
接收到生成存储系统模型的请求。存储系统模型表示存储系统的至少一部分。响应接收请求，加载存储系统接口配置。存储系统接口配置包含实体模型的属性。该属性对应于存储系统的存储系统实体的属性。此外，响应于接收到请求，实体模型被识别为表示存储系统实体。响应于将实体模型标识为表示存储系统实体，实体模型被实例化。

9. 发明申请

WO2017100041A1 PROCESSOR WITH AN EXPANDABLE INSTRUCTION SET ARCHITECTURE FOR DYNAMICALLY CONFIGURING EXECUTION RESOURCES 审中-公开
标题翻译：处理器具有可扩展的指令集体系结构，用于动态配置执行资源
公开(公告)号：WO2017100041A1
公开(公告)日：2017-06-15
申请号：PCT/US2016/064042
申请日：2016-11-29
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD. , HENRY, G., Glenn
发明人： HENRY, G., Glenn , HOOKER, Rodney, E. , PARKS, Terry , REED, Douglas, R.
IPC分类号： G06F15/00
CPC分类号： G06F9/3016 , G06F3/0604 , G06F3/0631 , G06F3/0673 , G06F8/41 , G06F8/443 , G06F8/447 , G06F9/22 , G06F9/28 , G06F9/30 , G06F9/3001 , G06F9/30043 , G06F9/3017 , G06F9/30174 , G06F9/30181 , G06F9/30185 , G06F9/30196 , G06F9/3836
摘要： A processor with an expandable instruction set architecture for dynamically configuring execution resources. The processor includes a programmable execution unit (PEU) that may be programmed to perform a user-defined function in response to a user-defined instruction (UDI). The PEU includes programmable logic elements and programmable interconnectors that are collectively programmed to perform at least one processing operation. A UDI loader is responsive to a UDI load instruction that specifies a UDI and a location of programming information that is used to program the PEU. The PEU may be programmed for one or more UDIs for one or more processes. An instruction table stores each UDI and corresponding information to identify the UDI and possibly to reprogram the PEU if necessary. A UDI handler consults the instruction table to identify a received UDI and to send corresponding information to the PEU to execute the corresponding user-defined function.
摘要翻译：
具有可扩展指令集体系结构的处理器，用于动态配置执行资源。处理器包括可编程执行单元（PEU），其可被编程为响应于用户定义的指令（UDI）执行用户定义的功能。 PEU包括可编程逻辑元件和可编程互连器，这些可编程互连器被共同编程为执行至少一个处理操作。 UDI加载器响应于UDI加载指令，该UDI加载指令指定用于编程PEU的UDI和编程信息的位置。 PEU可以针对一个或多个进程被编程用于一个或多个UDI。指令表存储每个UDI和相应的信息以识别UDI，并且如果需要可能重新编程PEU。 UDI处理程序查询指令表以识别接收到的UDI并向PEU发送相应的信息以执行相应的用户定义的功能。

10. 发明申请

WO2017052946A1 USER MODE HEAP SWAPPING 审中-公开
标题翻译：用户模式HEAP SWAPPING
公开(公告)号：WO2017052946A1
公开(公告)日：2017-03-30
申请号：PCT/US2016/048512
申请日：2016-08-25
申请人： MCAFEE, INC.
发明人： WOODWARD, Carl D. , SAMBANDAM, Venkata Ramanan , RUBAKHA, Dmitri
IPC分类号： G06F9/54 , G06F12/14 , G06F12/08
CPC分类号： G06F3/0659 , G06F3/0623 , G06F3/0631 , G06F3/064 , G06F3/0647 , G06F3/0656 , G06F3/0673 , G06F12/023 , G06F12/08 , G06F12/1408 , G06F12/1491 , G06F21/53 , G06F21/57 , G06F21/74 , G06F2212/1016 , G06F2212/1052 , G06F2212/152 , H04L9/3234
摘要： In an example, there is disclosed a computing apparatus, including a processor, including a trusted execution instruction set; a memory having an enclave portion, wherein the enclave is accessible only via the trusted execution instruction set; a swap file; and a memory management engine operable to: allocate a buffer within the enclave; receive a scope directive to indicate that the buffer is in scope; and protect the buffer from swapping to the swap file while the buffer is in scope. There is further disclosed an method of providing a memory management engine, and one or more computer-readable storage mediums having stored thereon executable instructions for providing the memory management engine.
摘要翻译：在一个示例中，公开了一种包括处理器的计算装置，包括可信执行指令集; 具有飞地部分的存储器，其中所述飞地仅能通过所述可信执行指令集来访问; 一个交换文件以及可操作用于：在所述飞地内分配缓冲器的存储器管理引擎; 接收范围指令以指示缓冲区在范围内; 并在缓冲区范围内保护缓冲区免受交换到交换文件。还公开了一种提供存储器管理引擎和一个或多个计算机可读存储介质的方法，其中存储有用于提供存储器管理引擎的可执行指令。

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