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1. 发明申请

WO2019032455A1 DATA BIT INVERSION TRACKING IN CACHE MEMORY TO REDUCE DATA BITS WRITTEN FOR WRITE OPERATIONS 审中-公开
公开(公告)号：WO2019032455A1
公开(公告)日：2019-02-14
申请号：PCT/US2018/045379
申请日：2018-08-06
申请人： QUALCOMM INCORPORATED
发明人： SHIN, Hyunsuk , KIM, Jung Pill , KIM, Sungryul
IPC分类号： G06F12/0804 , G06F12/0891 , G11C7/10 , G11C11/4063
CPC分类号： G11C11/1673 , G06F11/1012 , G06F11/1048 , G06F12/0895 , G06F13/4204 , G06F2212/6046 , G11C7/1006 , G11C11/1655 , G11C11/1675 , G11C11/4063 , G11C13/0069 , G11C15/00 , G11C15/02 , G11C15/046 , G11C29/50 , G11C2013/0076 , G11C2029/0411 , H03M13/2906
摘要： Data bit inversion tracking in cache memory to reduce data bits written for write operations is disclosed. In one aspect, a cache memory including a cache controller and a cache array is provided. The cache array includes one or more cache entries, each of which includes a cache data field and a bit change track field. The cache controller compares a current cache data word to a new data word to be written and stores a bit track change word representing the difference (i.e., inverted bits) between the current cache data word and the new data word in the bit change track field. By using the bit track change word stored in the bit change track field to determine whether fewer bit writes are required to write data in an inverted or a non-inverted form, power consumption can be reduced for write operations through reduced bit write operations.

2. 发明申请

WO2016133869A1 SETTING OF REFERENCE VOLTAGE FOR DATA SENSING IN FERROELECTRIC MEMORIES 审中-公开
标题翻译：在电磁记忆体中进行数据传感的参考电压设定
公开(公告)号：WO2016133869A1
公开(公告)日：2016-08-25
申请号：PCT/US2016/018011
申请日：2016-02-16
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： ZHOU, Carl, Z. , REMACK, Keith, A. , RODRIGUEZ, John, A.
IPC分类号： G11C11/22
CPC分类号： G11C11/221 , G11C11/2273 , G11C11/2275 , G11C29/028 , G11C29/50 , G11C29/50016
摘要： Described examples include a method of setting the reference voltage for sensing data states in integrated circuits including ferroelectric random access memory (FRAM) cells of the one-transistor-one capacitor (1T-1C) type. In an electrical test operation, some or all of the FRAM cells are programmed to a particular polarization state (32). A "shmoo" of the reference voltage for sensing the data state is performed (36), at one or more worst case electrical or environmental conditions for that data state (34), to determine a reference voltage limit at which the weakest cell fails to return the correct data when read (36). A configuration register is then written with a reference voltage based on this reference voltage limit (40), such as at the limit plus/minus a tolerance.
摘要翻译：所描述的示例包括设置用于感测数据状态的参考电压的方法，该集成电路包括单晶体管一电容器（1T-1C）类型的铁电随机存取存储器（FRAM）单元。在电测试操作中，部分或全部FRAM单元被编程为特定的偏振状态（32）。在用于该数据状态（34）的一个或多个最坏情况的电气或环境条件下（36）执行用于感测数据状态的参考电压的“shmoo”（34），以确定最弱电池不能使用的参考电压极限读取时返回正确的数据（36）。然后，以基于该参考电压限制（40）的参考电压写入配置寄存器，例如在极限加上/减去公差。

3. 发明申请

WO2016122627A1 DETERMINING A CURRENT IN A MEMORY ELEMENT OF A CROSSBAR ARRAY 审中-公开
标题翻译：确定十字架阵列的记忆元素中的电流
公开(公告)号：WO2016122627A1
公开(公告)日：2016-08-04
申请号：PCT/US2015/013877
申请日：2015-01-30
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： MURALIMANOHAR, Naveen , BALASUBRAMONIAN, Rajeev , FOLTIN, Martin
IPC分类号： G11C13/00 , G11C5/06
CPC分类号： G11C13/003 , G11C13/0033 , G11C13/004 , G11C13/0069 , G11C29/50 , G11C2013/0054 , G11C2013/0057 , G11C2029/5006 , G11C2213/72 , G11C2213/76
摘要： A method of determining a current in a memory element of a crossbar array is described. In the method, a number of pre-access operations are initiated. Each pre-access operation includes discarding a previously stored sneak current, determining a new sneak current for the crossbar array, discarding a previously stored sneak current, and storing the new sneak current. In the method, in response to a received access command, an access voltage is applied to a target memory element of the crossbar array and an element current for the target memory element is determined based on an access current and a stored sneak current.
摘要翻译：描述了确定交叉开关阵列的存储元件中的电流的方法。在该方法中，启动了许多预访问操作。每个预访问操作包括丢弃先前存储的潜行电流，确定交叉开关阵列的新潜行电流，丢弃先前存储的潜行电流并存储新的潜行电流。在该方法中，响应于接收到的访问命令，将访问电压施加到交叉开关阵列的目标存储器元件，并且基于存取电流和存储的潜行电流来确定目标存储器元件的元件电流。

4. 发明申请

WO2016014731A1 YUKAI VSL-BASED VT-COMPENSATION FOR NAND MEMORY 审中-公开
标题翻译： YUKAI基于VSL的NAND存储器的VT补偿
公开(公告)号：WO2016014731A1
公开(公告)日：2016-01-28
申请号：PCT/US2015/041636
申请日：2015-07-22
申请人： APLUS FLASH TECHNOLOGY, INC.
发明人： LEE, Peter, Wung
IPC分类号： G11C8/14 , G11C11/40 , G11C16/04
CPC分类号： G11C11/5635 , G11C7/14 , G11C7/18 , G11C11/56 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/14 , G11C16/24 , G11C16/26 , G11C16/3445 , G11C16/3459 , G11C29/50 , G11C2029/5002
摘要： A YUKAI NAND array comprising multiple strings associated with hierarchical global/local bit lines (GBL/LBL) and each string being associated with one LBL and having adjacent LBL as a dedicated local source line (LSL) without a common source line to connect all strings. Each of the LBLs is interleavingly associated with either an Odd or Even string selected via one pair of dummy cells inserted in each string and is used as one on-chip PCACHE register with full BL-shielding without wasting extra silicon area to allow batch- based multiple concurrent MLC All-BL, All-Vtn-Program and Alternative-WL program, Odd/Even read and verify operations with options of providing individual and common VSL-based Vt-compensation and VLBL compensations to mitigate high WL-WL and BL-BL coupling effects. Bias conditions in each string are provided to correctly sense highly-negative erase-verify voltage, multiple negative program-verify voltages and without VDS punch-through, breakdown and body-effect in both boundary and non-boundary WLs cells.
摘要翻译：包含与分级全局/局部位线（GBL / LBL）相关联的多个串的YUKAI NAND阵列，每个串与一个LBL相关联，并且具有相邻的LBL作为专用本地源线（LSL），而没有公共源线连接所有字符串。每个LBL与通过插入每个串中的一对虚拟单元选择的奇数或偶数字符串进行交织关联，并且被用作具有完全BL屏蔽的一个片上PCACHE寄存器，而不浪费额外的硅面积以允许基于批次多个并发的MLC全BL，全Vtn程序和替代WL程序，奇/偶读取和验证操作，具有提供单独和常见的基于VSL的Vt补偿和VLBL补偿的选项，以减轻高WL-WL和BL- BL耦合效应。提供每个串中的偏置条件以正确检测边界和非边界WL单元中的高负值擦除验证电压，多个负编程验证电压以及VDS穿透，击穿和体效应。

5. 发明申请

WO2014205398A1 ENERGY ANALYSIS FOR DIFFERENTIAL POWER ANALYSIS RESISTANCE 审中-公开
标题翻译：不同功率分析电阻的能量分析
公开(公告)号：WO2014205398A1
公开(公告)日：2014-12-24
申请号：PCT/US2014/043493
申请日：2014-06-20
申请人： CRYPTOGRAPHY RESEARCH, INC.
发明人： WACHS, Megan Anneke , LAN, Hai , LEISERSON, Andrew John , INKENBRANDT, Joseph William , SCHMITT, Ralf Michael
IPC分类号： H04L9/00
CPC分类号： G06F17/5036 , G01R27/02 , G06F17/50 , G06F17/5022 , G11C29/50 , H04L9/003
摘要： A first and second set of simulation information of a circuit design may be received. Energy consumption values associated with signals may be calculated for each of the first and second sets of simulation information of the circuit design. The energy consumption values associated with the transitions of the plurality of signals for each time point of a plurality of time points may be aggregated based on when each of the transitions of the signals occurs for each of the first and second sets of simulation information. Furthermore, a possible Differential Power Analysis (DPA) leak may be identified at one of the time points based on a difference in aggregated energy consumption values between the first and second sets of simulation information.
摘要翻译：可以接收电路设计的第一和第二组仿真信息。可以针对电路设计的第一组和第二组模拟信息中的每一个来计算与信号相关联的能量消耗值。可以基于对于第一和第二组模拟信息中的每一个发生信号的每个转换何时聚合与多个时间点中的每个时间点的多个信号的转变相关联的能量消耗值。此外，可以基于第一组和第二组模拟信息之间的聚合能量消耗值的差异在一个时间点上识别可能的差分功率分析（DPA）泄漏。

6. 发明申请

WO2013148544A1 MEMORY WITH REDUNDANT SENSE AMPLIFIER 审中-公开
标题翻译：具有冗余感测放大器的存储器
公开(公告)号：WO2013148544A1
公开(公告)日：2013-10-03
申请号：PCT/US2013/033648
申请日：2013-03-25
申请人： APPLE INC.
发明人： SENINGEN, Michael R. , RUNAS, Michael E.
IPC分类号： G11C29/12 , G11C29/50
CPC分类号： G11C11/418 , G11C7/06 , G11C7/1051 , G11C29/1201 , G11C29/50 , G11C29/50016 , G11C2029/1204 , G11C2029/5002
摘要： Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level of the first sense amplifier may be higher than the gain level of the second sense amplifier. The output circuit may include a multiplexer and the multiplexer may be operable to controllably select one of the outputs of the first and second sense amplifiers and pass the value of the selected sense amplifier. The output circuit may include a node that couples the outputs of the first and second sense amplifiers and the outputs of the first and second sense amplifiers may be able to be set to a high impedance state.
摘要翻译：公开了一种存储器的实施例，其可以在读取弱数据存储单元时降低读取错误的可能性。存储器可以包括多个数据存储单元，列多路复用器，第一读出放大器和第二读出放大器以及输出电路。第一读出放大器的增益电平可以高于第二读出放大器的增益电平。输出电路可以包括多路复用器，并且多路复用器可以可操作地可控地选择第一和第二读出放大器的输出之一并传递所选择的读出放大器的值。输出电路可以包括耦合第一和第二读出放大器的输出的节点，并且第一和第二读出放大器的输出可以被设置为高阻抗状态。

7. 发明申请

WO2013113426A1 DEVICE AND METHOD TO PERFORM A PARALLEL MEMORY TEST 审中-公开
标题翻译：执行并行存储器测试的设备和方法
公开(公告)号：WO2013113426A1
公开(公告)日：2013-08-08
申请号：PCT/EP2012/073966
申请日：2012-11-29
申请人： INSIDE SECURE
发明人： HICKEY, Graeme , KINCAID, Stuart
IPC分类号： G11C29/26
CPC分类号： G11C29/26 , G11C29/50 , G11C2029/2602
摘要： The invention relates to a semiconductor device (DV1) comprising N memory modules (MEM 0 _ MEM N-1 ), N being greater than or equal to three, each module comprising an array of memory cells arranged in rows and columns, a write circuit (WCT) coupled to each module and configured to write data (ID) in the memory cells, a read circuit (RCT) coupled to each module and configured to supply output data (OD 0 _ OD N-1 ) from the memory cells, a module selection circuit (MDEC) configured to individually select one memory module (MEM 0 _ MEM N-1 ) in a regular operation mode, and to collectively select two or more of the modules in a parallel mode, and a comparator circuit (CMP) coupled to the N modules and configured to compare, in the parallel mode, the output data supplied by the N modules.
摘要翻译：本发明涉及包括N个存储器模块（MEM0_MEMN-1），N个大于或等于3个的半导体器件（DV1），每个模块包括以行和列布置的存储器单元的阵列，写入电路（WCT）耦合到每个模块并且被配置为在存储器单元中写入数据（ID）;耦合到每个模块并被配置为从存储器单元提供输出数据（OD0_ODN-1）的读取电路（RCT），模块选择电路（MDEC ），其被配置为在常规操作模式中单独选择一个存储器模块（MEM0_MEMN-1），并且以并行模式共同选择两个或更多个模块;以及比较器电路（CMP），耦合到所述N个模块并被配置为在并行模式下，比较由N个模块提供的输出数据。

8. 发明申请

WO2013070424A1 A METHOD OF TESTING DATA RETENTION OF A NON-VOLATILE MEMORY CELL HAVING A FLOATING GATE 审中-公开
标题翻译：测量具有浮动门的非易失性存储单元的数据保持方法
公开(公告)号：WO2013070424A1
公开(公告)日：2013-05-16
申请号：PCT/US2012/061386
申请日：2012-10-22
申请人： SILICON STORAGE TECHNOLOGY, INC. , MARKOV, Viktor , YOO, Jong-won , BANSAL, Satish , KOTOV, Alexander
发明人： MARKOV, Viktor , YOO, Jong-won , BANSAL, Satish , KOTOV, Alexander
IPC分类号： H01L21/02
CPC分类号： G11C29/50 , G11C16/00 , G11C16/349 , G11C29/06 , G11C29/50004 , G11C29/50016
摘要： A method of decreasing the test time to determine data retention of a memory cell having a floating gate for the storage of charges thereon to determine if the memory cell has a leakage current from the floating gate. The memory cell is characterized by the leakage current having a rate of leakage which is dependent upon the absolute value of the voltage of the floating gate. The memory cell is further characterized by a first erase voltage and a first programming voltage applied during normal operation, and a first read current detected during normal operation. The method applies a voltage greater than the first erase voltage to over erase the floating gate. The memory cell including the floating gate is subject to a single high temperature bake. The memory cell is then tested for data retention of the floating gate based on the single high temperature bake.
摘要翻译：一种减少测试时间以确定具有用于存储电荷的浮动栅极的存储单元的数据保持的方法，以确定存储单元是否具有来自浮动栅极的漏电流。存储单元的特征在于泄漏电流具有取决于浮动栅极的电压的绝对值的泄漏速率。存储单元的特征还在于在正常操作期间施加的第一擦除电压和第一编程电压以及在正常操作期间检测到的第一读取电流。该方法施加大于第一擦除电压的电压以过度擦除浮动栅极。包括浮动栅极的存储单元经受单次高温烘烤。然后基于单个高温烘烤来测试存储器单元的浮动栅极的数据保持。

9. 发明申请

WO2012089334A3 METHOD AND SYSTEM FOR CONTROLLING LOSS OF RELIABILITY OF NON-VOLATILE MEMORY 审中-公开
标题翻译：用于控制非易失性存储器可靠性损失的方法和系统
公开(公告)号：WO2012089334A3
公开(公告)日：2012-08-23
申请号：PCT/EP2011006555
申请日：2011-12-23
申请人： ST MICROELECTRONICS NV , VENEROSO AMEDEO , VARONE FRANCESCO , VASTANO PASQUALE , DI STASIO VITANTONIO
发明人： VENEROSO AMEDEO , VARONE FRANCESCO , VASTANO PASQUALE , DI STASIO VITANTONIO
IPC分类号： G11C29/50 , G06F11/00 , G06F11/07 , G07F7/08 , G11C16/34 , H04W24/00
CPC分类号： G06F3/0614 , G06F11/008 , G06F12/0246 , G07F7/082 , G11C16/04 , G11C29/50 , G11C29/50016 , G11C2029/0409 , G11C2029/5002
摘要： The present invention relates a method for controlling a loss of reliability of a non-volatile memory (NVM) included in an Integrated Circuit Card (ICC). The method comprises the steps of -determining whether the NVM is reliable or not at the Operative System (OS) side of said ICC, and -generating an event associated with the reliability of the NVM at the OS side for an application of said ICC, if the NVM is determined to be unreliable.
摘要翻译：本发明涉及一种用于控制集成电路卡（ICC）中包括的非易失性存储器（NVM）的可靠性损失的方法。该方法包括以下步骤：在所述ICC的操作系统（OS）侧确定NVM是否可靠，并且产生与OS侧的NVM的可靠性有关的用于所述ICC的应用的事件，如果NVM被确定为不可靠。

10. 发明申请

WO2010096096A1 MEMORY MODULE INCLUDING ENVIRONMENTAL OPTIMIZATION 审中-公开
标题翻译：包含环境优化的记忆模块
公开(公告)号：WO2010096096A1
公开(公告)日：2010-08-26
申请号：PCT/US2009/057875
申请日：2009-09-22
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , LEE, Teddy , CALHOUN, Michael, B. , CARR, Sean , VU, Dan
发明人： LEE, Teddy , CALHOUN, Michael, B. , CARR, Sean , VU, Dan
IPC分类号： G11C11/4093
CPC分类号： G11C5/04 , G11C5/005 , G11C29/50 , G11C2029/0409 , G11C2029/4402 , G11C2029/5002
摘要： A memory apparatus (100) enables operation which is adapted to environmental conditions. The memory apparatus (100) includes a memory module (102) that can store and incorporate environment-dependent optimal operating parameters. The memory module (102) comprises a plurality of volatile memory devices (104) and one or more non-volatile memory devices (106) that store a plurality of environment-dependent device parameters for a device selected from the plurality of volatile memory devices (104). The stored parameters enable the selected device to function optimally in multiple environmental conditions.
摘要翻译：存储装置（100）使能适应环境条件的操作。存储装置（100）包括存储模块（102），其可以存储和结合与环境相关的最佳操作参数。存储器模块（102）包括多个易失性存储器设备（104）和一个或多个非易失性存储器设备（106），其存储用于从多个易失性存储器设备中选择的设备的多个环境相关设备参数（ 104）。存储的参数使所选设备能够在多种环境条件下最佳地运行。

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