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1. 发明申请

WO2016172636A1 Dual Function Hybrid Memory Cell 审中-公开
标题翻译：双功能混合存储单元
公开(公告)号：WO2016172636A1
公开(公告)日：2016-10-27
申请号：PCT/US2016/029059
申请日：2016-04-22
申请人： NEO SEMICONDUCTOR, INC.
发明人： HSU, Fu-Chang
IPC分类号： H01L29/792 , H01L21/28 , G11C11/56 , G11C16/02
CPC分类号： G11C16/0475 , G11C7/1015 , G11C11/401 , G11C16/0466 , G11C16/10 , G11C2211/4016 , H01L21/28282 , H01L27/1211 , H01L29/4234 , H01L29/66833 , H01L29/785 , H01L29/792
摘要： A dual function hybrid memory cell is disclosed. In one aspect, the memory cell includes a substrate, a bottom charge-trapping region formed on the substrate, a top charge-trapping region formed on the bottom charge-trapping region, and a gate layer formed on the top charge trapping region. In another aspect, a method for programming a memory cell having a substrate, a bottom charge-trapping layer, a top charge-trapping layer, and a gate layer is disclosed. The method includes biasing a channel region of the substrate, applying a first voltage differential between the gate layer and the channel region, injecting charge into the bottom charge-trapping layer from the channel region based on the first voltage differential. The method also includes applying a second voltage differential between the gate layer and the channel region and injecting charge from the bottom charge-trapping layer into the top charge-trapping layer based on the second voltage differential.
摘要翻译：公开了一种双功能混合存储器单元。一方面，存储单元包括基板，形成在基板上的底部电荷俘获区域，形成在底部电荷俘获区域上的顶部电荷俘获区域和形成在顶部电荷俘获区域上的栅极层。另一方面，公开了一种用于编程具有衬底，底部电荷俘获层，顶部电荷俘获层和栅极层的存储器单元的方法。该方法包括偏置衬底的沟道区域，在栅极层和沟道区域之间施加第一电压差，基于第一电压差将电荷从沟道区域注入底部电荷俘获层。该方法还包括在栅极层和沟道区域之间施加第二电压差，并且基于第二电压差将电荷从底部电荷俘获层注入顶部电荷俘获层。

2. 发明申请

WO01075897A3 SYNCHRONOUS FLASH MEMORY 审中-公开
标题翻译：同步闪存
公开(公告)号：WO01075897A3
公开(公告)日：2002-05-30
申请号：PCT/US2001/010372
申请日：2001-03-30
IPC分类号： G11C16/02 , G06F12/00 , G06F12/02 , G06F13/16 , G06F13/42 , G11C7/10 , G11C8/18 , G11C16/06 , G11C16/10 , G11C16/26
CPC分类号： G11C7/106 , G06F13/1615 , G06F13/1668 , G06F13/1694 , G06F13/4243 , G11C7/10 , G11C7/1015 , G11C7/1039 , G11C7/1045 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C8/18 , G11C16/10 , G11C16/26 , G11C2207/105 , G11C2207/2281 , G11C2207/229 , G11C2216/22
摘要： A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The synchronous non-volatile memory device has external interconnects arranged in a manner that corresponds to interconnects of a synchronous dynamic random access memory device. The synchronous dynamic random access memory device. The synchronous flash memory device, however, comprises a reset connection, and a Vccp power supply connection correspond to first and second no-connect (NC) interconnect pins of the synchronous dynamic random access memory. In one embodiment, the synchronous non-volatile memory device has a command interface comprising a write enable connection (WE#) to receive a write enable signal, a column address strobe connection (CAS#) to receive a write enable signal, a column address strobe connection (RAS#) to receive a row address strobe signal, and a chip select connection (CS#) to receive a chip select signal.
摘要翻译：计算机系统包括存储器控制器和经由主存储器总线耦合到存储器控制器的同步非易失性存储器件。同步非易失性存储器件具有以对应于同步动态随机存取存储器件的互连的方式布置的外部互连。同步动态随机存取存储器件。然而，同步闪速存储器件包括复位连接，并且Vccp电源连接对应于同步动态随机存取存储器的第一和第二非连接（NC）互连引脚。在一个实施例中，同步非易失性存储器件具有命令接口，其包括用于接收写使能信号的写使能连接（WE＃），用于接收写使能信号的列地址选通连接（CAS＃），列地址选通连接（RAS＃）以接收行地址选通信号，以及芯片选择连接（CS＃）以接收芯片选择信号。

3. 发明申请

WO00074058A1 STORAGE, STORAGE METHOD, AND DATA PROCESSING SYSTEM 审中-公开
标题翻译：存储，存储方法和数据处理系统
公开(公告)号：WO00074058A1
公开(公告)日：2000-12-07
申请号：PCT/JP1999/002841
申请日：1999-05-28
IPC分类号： G06F12/02 , G11C7/06 , G11C7/10 , G11C7/00 , G06F12/06
CPC分类号： G11C7/1012 , G06F12/02 , G11C7/06 , G11C7/1006 , G11C7/1015
摘要： A storage in which n-bits are a basic read unit. Data whose logical bit positions are 0*8+k, 1*8+k, 2*8+k, 3*8+k,..., m*8+k (where k and m are natural numbers and satisfy the inequalities 0
摘要翻译： n位是基本读取单元的存储器。其逻辑位位置为0 * 8 + k，1 * 8 + k，2 * 8 + k，3 * 8 + k，...，m * 8 + k的数据（其中k和m为自然数，满足在存储单元阵列中彼此靠近的存储单元中存储不等式0

4. 发明申请

WO9836587A2 QUEUING STRUCTURE AND METHOD FOR PRIORITIZATION OF FRAMES IN A NETWORK SWITCH 审中-公开
标题翻译：用于网络交换机框架优化的排队结构和方法
公开(公告)号：WO9836587A2
公开(公告)日：1998-08-20
申请号：PCT/US9802357
申请日：1998-02-06
申请人： ADVANCED MICRO DEVICES INC
发明人： ERIMLI BAHADIR , CRAYFORD IAN , EGBERT CHANDAN
IPC分类号： G06F5/06 , G06F12/12 , G11C7/10 , G11C11/412 , H04L12/18 , H04L12/24 , H04L12/46 , H04L12/56 , H04L29/06 , H04Q3/545 , H04Q3/64
CPC分类号： H04L69/26 , G06F5/06 , G06F12/128 , G11C7/1015 , G11C11/412 , H04L12/1877 , H04L12/1881 , H04L12/4641 , H04L12/4645 , H04L12/467 , H04L41/0213 , H04L47/50 , H04L47/6215 , H04L49/103 , H04L49/205 , H04L49/255 , H04L49/30 , H04L49/3009 , H04L49/3027 , H04L49/351 , H04L49/354 , H04L49/90 , H04L49/901 , H04L49/9073 , H04L49/9078 , H04Q3/54591 , H04Q2213/1316 , H04Q2213/13162
摘要： A method and arrangement for queuing data in a prioritized manner have a queue with a single queue write side in which data entries are input to the queue. The queue also has a plurality of queue read sides, with each read side having a different priority level. An entry exiting from the queue write side is examined to determine the priority level of the entry, and then placed into the queue read side with the matching priority level as the entry. The queue read sides form the output of the queue, and are polled and emptied so that the higher priority queues are emptied completely before emptying lower priority queues.
摘要翻译：以优先排序方式对数据进行排队的方法和装置具有一个具有单个队列写入端的队列，其中将数据条目输入队列。队列还具有多个队列读取侧，每个读取侧具有不同的优先级。检查从队列写入端退出的条目以确定条目的优先级，然后将其作为条目以匹配的优先级等级放入队列读取端。队列读取端形成队列的输出，并被轮询和清空，以便在排空较低优先级队列之前，将优先级队列完全清空。

5. 发明申请

WO2017044338A1 SYSTEMS, METHODS, AND DEVICES FOR PARALLEL READ AND WRITE OPERATIONS 审中-公开
标题翻译：用于并行读取和写入操作的系统，方法和设备
公开(公告)号：WO2017044338A1
公开(公告)日：2017-03-16
申请号：PCT/US2016/049286
申请日：2016-08-29
申请人： CYPRESS SEMICONDUCTOR CORPORATION
发明人： AGRAWAL, Vineet , BETTMAN, Roger , LESHNER, Samuel
IPC分类号： G06F12/02 , G11C11/21 , G11C11/34 , G11C16/02 , G11C16/04
CPC分类号： G11C7/18 , G06F12/023 , G06F2212/1044 , G11C5/147 , G11C7/06 , G11C7/1015 , G11C7/12 , G11C7/22 , G11C2207/2209 , G11C2207/2281 , G11C2207/229
摘要： Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line.. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to selectively couple the local bit line to the sense amplifier. The devices may also include a second device coupled to the local bit line and an electrical ground. The second device may be configured to selectively couple the local bit line to the electrical ground.
摘要翻译：这里公开了用于并行读写操作的系统，方法和装置。设备可以包括耦合到本地位线的第一传输设备和与存储器阵列的存储器单元相关联的全局位线。第一传输设备可以被配置为选择性地将全局位线耦合到本地位线。设备还可以包括耦合到本地位线的第一设备和读出放大器。第一器件可以被配置为选择性地将局部位线耦合到读出放大器。该装置还可以包括耦合到本地位线和电接地的第二装置。第二装置可以被配置为选择性地将局部位线耦合到电接地。

6. 发明申请

WO2011127563A1 MEMORY PROGRAMMING USING VARIABLE DATA WIDTH 审中-公开
标题翻译：使用可变数据宽度进行存储器编程
公开(公告)号：WO2011127563A1
公开(公告)日：2011-10-20
申请号：PCT/CA2011/000383
申请日：2011-04-11
申请人： MOSAID TECHNOLOGIES INCORPORATED , PYEON, Hong Beom
发明人： PYEON, Hong Beom
IPC分类号： G11C7/00 , G11C13/00
CPC分类号： G11C7/1015 , G11C7/1006 , G11C13/0004 , G11C13/0069 , G11C2013/0085 , G11C2013/0088
摘要： A memory system comprises a memory including a plurality of bits arranged as one or more words. Each bit in each word is capable of being programmed either to a particular logical state or to another logical state. A variable data width controller is in communication with the memory. The variable data width controller comprises an adder to determine a programming number of bits in a word to be programmed into a memory. Each bit to be programmed is in the particular logical state. A partitioning block divides the word in to two or more sub-words when the programming number exceeds a maximum number. A switch is in communication with the partitioning block. The switch sequentially provides one or more write pulses. Each write pulse enables a separate communication path between the memory and one of the word and the sub-words.
摘要翻译：存储器系统包括存储器，该存储器包括排列成一个或多个单词的多个位。每个单词中的每个位都能够被编程到特定的逻辑状态或另一个逻辑状态。可变数据宽度控制器与存储器通信。可变数据宽度控制器包括加法器，用于确定要编程到存储器中的一个字中的位的编程位数。要编程的每个位处于特定的逻辑状态。当编程号码超过最大数量时，划分块将字分成两个或多个子字。开关与分区块通信。开关依次提供一个或多个写入脉冲。每个写入脉冲使得存储器与字和子字中的一个之间的单独通信路径成为可能。

7. 发明申请

WO01075895A3 ELIMINATION OF PRECHARGE OPERATION IN SYNCHRONOUS FLASH MEMORY 审中-公开
标题翻译：消除同步闪存中的预处理操作
公开(公告)号：WO01075895A3
公开(公告)日：2002-03-21
申请号：PCT/US2001/010038
申请日：2001-03-30
IPC分类号： G11C16/02 , G06F13/16 , G06F13/42 , G11C7/10 , G11C8/18 , G11C16/10 , G11C16/26 , G11C16/32
CPC分类号： G11C7/106 , G06F13/1615 , G06F13/1668 , G06F13/1694 , G06F13/4243 , G11C7/10 , G11C7/1015 , G11C7/1039 , G11C7/1045 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C8/18 , G11C16/10 , G11C16/26 , G11C16/32 , G11C2207/105 , G11C2207/2281 , G11C2207/229 , G11C2216/22
摘要： A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. In one embodiment, the synchronous memory device comprises an array of memory cells arranged in rows and columns. A clock connection is provided to receive an externally provided clock signal. The memory does not require a precharge time period during a time period between the first and second externally provided active commands.
摘要翻译：同步闪速存储器包括非易失性存储器单元阵列。存储器件具有与SDRAM兼容的封装配置。在一个实施例中，同步存储器件包括以行和列排列的存储单元阵列。提供时钟连接以接收外部提供的时钟信号。存储器在第一和第二外部提供的有效命令之间的时间段期间不需要预充电时间段。

8. 发明申请

WO98036358A1 METHOD AND APPARATUS FOR MAINTAINING A TIME ORDER BY PHYSICAL ORDERING IN A MEMORY 审中-公开
标题翻译：通过物理订单在记忆中维护时间订单的方法和装置
公开(公告)号：WO98036358A1
公开(公告)日：1998-08-20
申请号：PCT/US1998/001687
申请日：1998-01-30
IPC分类号： G06F5/06 , G06F12/08 , G06F12/12 , G11C7/10 , H04L12/18 , H04L12/24 , H04L12/46 , H04L12/861 , H04L12/879 , H04L12/931 , H04L12/933 , H04L12/935 , H04L12/937 , H04L29/06 , H04Q3/545
CPC分类号： H04L49/9047 , G06F5/06 , G06F12/0864 , G06F12/128 , G11C7/1015 , H04L12/1863 , H04L41/0213 , H04L49/103 , H04L49/205 , H04L49/255 , H04L49/30 , H04L49/3009 , H04L49/3027 , H04L49/351 , H04L49/354 , H04L49/45 , H04L49/90 , H04L49/901 , H04L69/26 , H04Q3/54591 , H04Q2213/1316 , H04Q2213/13162
摘要： A method and arrangement for maintaining a time order of entries in a memory determines a row in which the entry will be stored, the memory being logically divided into rows and columns. The columns are arranged sequentially in each row from the newest to the oldest. Once the row in which the entry will be stored is determined, the entry is stored in that row in the column (or entry location) that is the newest column. The entry that was previously in the newest column is shifted to the next older column, and the entry that was previously in the next older column is shifted to the next most older column, etc. If a row is completely filled prior to the writing of a new entry, then the entry in the oldest column is removed from the memory and the other entries shifted.
摘要翻译：用于维护存储器中条目的时间顺序的方法和装置确定了将存储该条目的行，该存储器在逻辑上被划分成行和列。这些列按照从最新到最旧的顺序排列。一旦确定了条目将被存储的行，该条目将被存储在作为最新列的列（或入口位置）中的该行中。先前在最新列中的条目将转移到下一个较旧的列，并且先前在下一个较旧列中的条目将转移到下一个较旧的列等。如果在写入之前完整填写了一行一个新条目，则最旧列中的条目将从内存中删除，其他条目移动。

9. 发明申请

WO1997003445A1 BLOCK WRITE FOR MEMORY COMPONENTS 审中-公开
标题翻译：内存组件的块写
公开(公告)号：WO1997003445A1
公开(公告)日：1997-01-30
申请号：PCT/US1996011436
申请日：1996-07-08
申请人： RAMBUS, INC.
发明人： RAMBUS, INC. , WARE, Frederick, Abbott , BARTH, Richard, Maurice , HAMPEL, Craig , DILLON, John, Bradly , GARRETT, Billy, W.
IPC分类号： G11C07/00
CPC分类号： G11C7/1015
摘要： Circuitry for performing a memory block write is described. The memory block includes b block words, each block word having t block bytes. Each block byte has s bits of memory. Each block byte is associated with at least two associated mask value bits. A constant register has at least s x t bits of memory arranged as t constant bytes, each constant byte storing a constant value, each constant byte associated with one block of every block word. The block write circuitry includes control circuitry for selecting one of a normal write function and a block write function in accordance with a block write signal. When the block write function is selected, the control circuitry stores the associated constant value in every nonmasked block byte substantially simultaneously in accordance with a value of the associated mask value bits.
摘要翻译：描述用于执行存储器块写入的电路。存储块包括b个块字，每个块字具有t个块字节。每个块字节都有s位存储器。每个块字节与至少两个关联的掩码值位相关联。一个常数寄存器至少有一个s x t位的存储器被排列成t个恒定字节，每个恒定字节存储一个恒定值，每个恒定字节与每个块字的一个块相关联。块写入电路包括用于根据块写入信号选择正常写入功能和块写入功能之一的控制电路。当选择块写入功能时，控制电路根据相关联的掩码值位的值基本上同时地存储每个非屏蔽块字节中的关联常数值。

10. 发明申请

WO2017092193A1 COMPUTER MEMORY MANAGEMENT METHOD AND SYSTEM 审中-公开
标题翻译：计算机存储器管理方法和系统
公开(公告)号：WO2017092193A1
公开(公告)日：2017-06-08
申请号：PCT/CN2016/076493
申请日：2016-03-16
申请人： HUAWEI TECHNOLOGIES CO., LTD.
发明人： WANG, Zixiong
IPC分类号： G06F12/00
CPC分类号： G06F3/0619 , G06F3/065 , G06F3/067 , G06F9/5016 , G06F13/16 , G11C7/1015
摘要： The computer can include a memory system having a plurality of memory cells readable and writable by the processing unit and including a least a first group of memory cells of a same speed grade. A plurality of copy regions each having a corresponding portion of the memory cells of the first group, and a distinct combination of copy unit and copy factor, the copy unit corresponding to a given amount of memory cells. The processing unit can be configured to obtain an indication to copy a data structure stored in the memory system; associate the data structure to one of the copy regions based on the corresponding combination of copy unit and copy factor; copy the data structure to the associated copy region in a number of copies equal to the corresponding copy factor;and successively access different ones of the copies of the data structure.
摘要翻译：该计算机可以包括存储器系统，该存储器系统具有可由处理单元读取和写入的多个存储器单元并且包括具有相同速度等级的至少第一组存储器单元。多个复制区域，每个复制区域具有第一组的存储器单元的对应部分以及复制单元和复制因子的不同组合，复制单元对应于给定量的存储器单元。处理单元可以被配置为获得复制存储在存储器系统中的数据结构的指示; 基于复制单元和复制因子的对应组合将数据结构关联到复制区域中的一个; 将数据结构以等于对应复制因子的多个副本复制到关联的复制区域;以及连续访问数据结构的不同副本。

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