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1. 发明申请

WO2017074581A1 NON-VOLATILE MEMORY SYSTEM WITH MULTI-WRITE DIRECTION MEMORY UNITS 审中-公开
标题翻译：具有多个写方向存储器单元的非易失性存储器系统
公开(公告)号：WO2017074581A1
公开(公告)日：2017-05-04
申请号：PCT/US2016/051597
申请日：2016-09-14
申请人： SANDISK TECHNOLOGIES LLC
发明人： BARAN, Ivan , LEE, Aaron , KOCHAR, Mrinal , PALITYKA, Mikhail , EA, Dennis , NG, Yew, Yin , BHALERAO, Abhijeet
IPC分类号： G11C16/34 , G11C16/10 , G11C16/08 , G11C16/24
CPC分类号： G11C16/14 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/3427 , G11C16/349 , G11C16/3495 , G11C2211/5648
摘要： Non-volatile memory systems with mufti-write direction memory units are disclosed in one implementation an apparatus comprises a non-volatile memory and a controller in communication with the non-volatile memory. The controller is configured to select an empty memory block of the non-volatile memory for the storage of data; examine an identifier associated with the memory block to determine a write direction for the storage of data; and write data to the memory block beginning: with an initial word fine of the memory block or a last word: Um of the memory block dependent on the write direction. The controller is further configured to erase the memory unit and, in response to erasing the memory unit, modify the identifier to change the write direction for a subsequent write of data to the memory block.
摘要翻译：在一个实施方式中公开了具有多写方向存储器单元的非易失性存储器系统，该装置包括非易失性存储器和与该非易失性存储器通信的控制器。控制器被配置为选择非易失性存储器的空存储块用于存储数据; 检查与存储器块相关联的标识符以确定用于存储数据的写入方向; 并且将数据写入存储器块开始：具有取决于写入方向的存储器块的最初单词罚款或最后一个字：存储器块的Um。控制器还被配置为擦除存储器单元，并且响应于擦除存储器单元而修改标识符以改变写入方向以用于随后将数据写入存储器块。

2. 发明申请

WO2016203631A1 フラッシュメモリデバイス审中-公开
标题翻译：闪存存储器件
公开(公告)号：WO2016203631A1
公开(公告)日：2016-12-22
申请号：PCT/JP2015/067685
申请日：2015-06-19
申请人：株式会社日立製作所
发明人：狹間　洋平 , 小川　純司 , 二瀬　健太
IPC分类号： G11C16/06 , G06F12/16
CPC分类号： G11C16/26 , G06F3/067 , G06F3/0688 , G06F11/1048 , G06F11/1068 , G06F11/1076 , G06F12/16 , G11C11/5642 , G11C16/349 , G11C2211/5648
摘要：フラッシュメモリコントローラは、フラッシュメモリチップからのリードのためのパラメータ値を指定するリードオプション、の実行順序を示すリードパターンを保持する。フラッシュメモリコントローラは、リードコマンドに従ってフラッシュメモリチップからリードしたデータのエラー訂正を実行する。フラッシュメモリコントローラは、エラー訂正によってリードしたデータの全てのエラーを訂正できない場合、リードパターンが示す次のリードオプションをフラッシュメモリチップに指定して、フラッシュメモリチップからデータをリードする。
摘要翻译：本发明的闪速存储器控制器保持指示从闪速存储器芯片读取的参数值的读选项的执行顺序的读模式。闪存控制器响应于读取命令对从闪速存储器芯片读取的数据执行错误校正。如果读取的数据的所有错误都无法通过纠错进行纠正，则闪存控制器为闪存芯片指定由读取模式指示的下一个读取选项，并从闪存芯片读取数据。

3. 发明申请

WO2016004388A1 CIRCUITRY FOR FERROELECTRIC FET-BASED DYNAMIC RANDOM ACCESS MEMORY AND NON-VOLATILE MEMORY 审中-公开
标题翻译：用于基于电磁场的动态随机存取存储器和非易失性存储器的电路
公开(公告)号：WO2016004388A1
公开(公告)日：2016-01-07
申请号：PCT/US2015/039109
申请日：2015-07-02
申请人： YALE UNIVERSITY
发明人： SUN, Xiao , MA, Tso-Ping
IPC分类号： G11C11/22
CPC分类号： G11C11/2275 , G11C11/223 , G11C11/2277 , G11C11/5657 , G11C29/023 , G11C29/028 , G11C29/52 , G11C2029/0409 , G11C2029/0411 , G11C2211/5648
摘要： Exemplary embodiments of the present disclosure are directed to circuitry for effective operation of Ferroelectric-gated FET (FeFET) memories. Exemplary embodiment of the present disclosure includes circuits and/or circuit blocks to facilitate memory refresh, error checking and correcting (ECC), reading and sensing memory cells, program and erase operations, and other control and periphery operations for FeFET memory cell arrays.
摘要翻译：本公开的示例性实施例涉及用于铁电栅极FET（FeFET）存储器的有效操作的电路。本公开的示例性实施例包括用于促进存储器刷新，错误检查和校正（ECC），读取和感测存储器单元，编程和擦除操作以及用于FeFET存储器单元阵列的其他控制和外围操作的电路和/或电路块。

4. 发明申请

WO2012156889A1 SPARSE PROGRAMMING OF ANALOG MEMORY CELLS 审中-公开
标题翻译：模拟记忆细胞的稀疏编程
公开(公告)号：WO2012156889A1
公开(公告)日：2012-11-22
申请号：PCT/IB2012/052375
申请日：2012-05-13
申请人： APPLE INC. , GURGI, Eyal
发明人： GURGI, Eyal
IPC分类号： G11C16/04 , G06F12/02
CPC分类号： G11C11/56 , G11C11/5628 , G11C16/3418 , G11C16/3427 , G11C27/005 , G11C2211/5641 , G11C2211/5648
摘要： A method for data storage in a memory (24) including an array (28) of analog memory cells (32), includes selecting a group of the memory cells such that each memory cell in the group has one or more neighbor memory cells in the array that are excluded from the group. Data is stored in the group of the memory cells while excluding the neighbor memory cells from programming as long as the data is stored in the group of the memory cells.
摘要翻译：一种用于在包括模拟存储器单元（32）的阵列（28）的存储器（24）中的数据存储的方法，包括：选择一组存储器单元，使得组中的每个存储器单元具有一个或多个相邻存储器单元从组中排除的数组。只要数据存储在存储单元的组中，数据就被存储在存储单元的组中，同时排除相邻存储单元的编程。

5. 发明申请

WO2012075826A1 METHOD AND MEMORY CONTROLLER FOR READING DATA STORED IN FLASH MEMORY BY REFERRING TO BINARY DIGIT DISTRIBUTION CHARACTERISTICS OF BIT SEQUENCES READ FROM FLASH MEMORY 审中-公开
标题翻译：用于读取存储在闪存中的数据的方法和存储器控制器通过引用从闪存存储器读取的位数的二进制数字分配特性
公开(公告)号：WO2012075826A1
公开(公告)日：2012-06-14
申请号：PCT/CN2011/078194
申请日：2011-08-10
申请人： SILICON MOTION INC. , YANG, Tsung-Chieh
发明人： YANG, Tsung-Chieh
IPC分类号： G11C7/00 , G11C16/00
CPC分类号： G11C16/26 , G06F3/0619 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F11/1068 , G06F11/1072 , G11C11/5642 , G11C16/0475 , G11C16/0483 , G11C16/3427 , G11C29/52 , G11C2211/5644 , G11C2211/5648 , H03M13/152
摘要： An exemplary method for reading data stored in a flash memory includes: controlling the flash memory to perform a plurality of read operations upon each of a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from each of the memory cells as one of the bit sequences by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.
摘要翻译：用于读取存储在闪速存储器中的数据的示例性方法包括：控制闪存以对包括在闪速存储器中的多个存储器单元中的每一个进行多个读取操作; 分别从存储单元读取多个位序列，其中读出操作通过利用不同的控制栅极电压设置从每个存储器单元中读出作为比特序列之一的预定位顺序的位; 以及根据比特序列的二进制数字分配特性来确定存储器单元的读出信息。

6. 发明申请

WO2011150177A1 METHODS AND DEVICES TO REDUCE OUTER CODE FAILURE RATE VARIABILITY 审中-公开
标题翻译：减少外部代码失败率变化的方法和设备
公开(公告)号：WO2011150177A1
公开(公告)日：2011-12-01
申请号：PCT/US2011/038093
申请日：2011-05-26
申请人： SEAGATE TECHNOLOGY LLC
发明人： RUB, Bernie, Bernardo
IPC分类号： G06F11/10 , G11C11/56
CPC分类号： G06F11/10 , G06F11/1012 , G06F11/1076 , G11C7/1006 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/3427 , G11C29/00 , G11C2211/5648 , G11C2216/14
摘要： The variability of outer code failure rate of memory pages of a solid state memory device can be reduced by selectively grouping the pages included in the outer code words. The data in the page groups are encoded into outer code words which are stored in the memory device. Encoding the data of the page groups and storing the encoded data includes intermittently accumulating an outer code parity as the pages are sequentially stored in the memory device according to a particular order. The pages can be randomly selected for the page groups or can be grouped based on predicted or measured failure rate information. In a memory device having multi-level memory cells, predicting the failure rate of a page can be based on whether the page is a most significant bit (MSB) page or a least significant bit (LSB) page.
摘要翻译：可以通过选择性地对包含在外部码字中的页面进行分组来减少固态存储器件的存储器页面的外部代码故障率的变化。页组中的数据被编码为存储在存储器件中的外码字。编码页组的数据并存储编码数据包括根据特定顺序随着页顺序存储在存储装置中而间歇地累积外码奇偶校验。这些页面可以随机选择页面组，也可以根据预测或测量的故障率信息进行分组。在具有多级存储器单元的存储器件中，可以基于页是最高有效位（MSB）页还是最低有效位（LSB）页来预测页的故障率。

7. 发明申请

WO2011075594A1 NON-VOLATILE MEMORY WITH MULTI-GEAR CONTROL USING ON-CHIP FOLDING OF DATA 审中-公开
标题翻译：使用片上数据折叠的多种控制的非易失性存储器
公开(公告)号：WO2011075594A1
公开(公告)日：2011-06-23
申请号：PCT/US2010/060844
申请日：2010-12-16
申请人： SANDISK CORPORATION , HUANG, Jianmin , AVILA, Chris , GAVENS, Lee M. , SPROUSE, Steven T. , GOROBETS, Sergey Anatolievich , HUTCHISON, Neil David
发明人： HUANG, Jianmin , AVILA, Chris , GAVENS, Lee M. , SPROUSE, Steven T. , GOROBETS, Sergey Anatolievich , HUTCHISON, Neil David
IPC分类号： G11C16/10 , G11C11/56
CPC分类号： G06F3/0608 , G06F3/0611 , G06F3/064 , G06F3/0679 , G06F12/0246 , G06F2212/7202 , G06F2212/7203 , G11C7/1042 , G11C11/5621 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C2211/5641 , G11C2211/5648
摘要： A memory system and methods of its operation are presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. The memory system receives data from the host and performs a binary write operation of the received data to the first section of the non-volatile memory circuit. The memory system subsequently folds portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes reading the portions of the data from the first section rewriting it into the second section of the non-volatile memory using a multi-state programming operation. The controller determines to operate the memory system according to one of multiple modes. The modes include a first mode, where the binary write operations to the first section of the memory are interleaved with folding operations at a first rate, and a second mode, where the number of folding operations relative to the number of the binary write operations to the first section of the memory are performed at a higher than in the first mode. The memory system then operates according to determined mode. The memory system may also include a third mode, where folding operations are background operations executed when the memory system is not receiving data from the host.
摘要翻译：介绍了一种存储系统及其操作方法。存储器系统包括控制器和非易失性存储器电路，其中非易失性存储器电路具有数据以二进制格式存储的第一部分和第二部分，其中数据以多状态格式存储。存储器系统从主机接收数据，并且对所述非易失性存储器电路的第一部分执行所接收数据的二进制写操作。存储系统随后将数据的部分从非易失性存储器的第一部分折叠到非易失性存储器的第二部分，其中折叠操作包括从第一部分读取数据的部分，将数据重写成第二部分使用多状态编程操作的非易失性存储器的一部分。控制器根据多种模式之一确定操作存储器系统。这些模式包括第一模式，其中对存储器的第一部分的二进制写入操作以第一速率进行折叠操作和第二模式，其中相对于二进制写入操作的数量的折叠操作的数量存储器的第一部分在高于第一模式下执行。然后，存储器系统根据确定的模式进行操作。存储器系统还可以包括第三模式，其中折叠操作是当存储器系统未从主机接收数据时执行的背景操作。

8. 发明申请

WO2018026475A2 APPARATUS AND METHOD FOR ENDURANCE FRIENDLY PROGRAMMING USING LOWER VOLTAGE THRESHOLDS 审中-公开
标题翻译：使用较低电压阈值进行耐用性良好编程的装置和方法
公开(公告)号：WO2018026475A2
公开(公告)日：2018-02-08
申请号：PCT/US2017/041603
申请日：2017-07-11
申请人： INTEL CORPORATION
发明人： WU, Wei , ZOU, Yi , KHAN, Jawad B. , GUO, Xin
IPC分类号： G11C16/10 , G11C16/34 , G11C16/26
CPC分类号： G11C11/5628 , G06F3/0608 , G06F3/0661 , G06F3/0688 , G11C7/1006 , G11C11/5642 , G11C16/10 , G11C2211/5641 , G11C2211/5648
摘要： Provided are a method and apparatus for endurance friendly programming using lower voltage thresholds. A non-volatile memory has storage cells organized as pages programmed using a first number of threshold voltage levels. The storage cells are organized into storage cell groups to which data is written. Each storage cell group is programmed to store a first number of bits of information. A memory controller selects a second number of bits of information from pages less than the first number of bits of information. The memory controller programs the storage cells of the storage cell group using threshold voltage levels from a second number of threshold voltage levels, wherein the second number of threshold voltage levels is less than the first number of threshold voltage levels and comprises a lowest of the first number of threshold voltage levels.
摘要翻译：提供了一种使用较低电压阈值进行耐久性编程的方法和设备。非易失性存储器具有按照使用第一数量的阈值电压电平编程的页面组织的存储单元。存储单元被组织成写入数据的存储单元组。每个存储单元组被编程为存储第一数量的信息位。存储器控制器从小于第一数量的信息位的页中选择第二数量的信息位。存储器控制器使用来自第二数量的阈值电压电平的阈值电压电平对存储单元组的存储单元进行编程，其中第二数量的阈值电压电平小于第一数量的阈值电压电平并且包括第一阈值电压电平的数量。

9. 发明申请

WO2016057202A1 PROGRAMMING OF DRAIN SIDE WORD LINE TO REDUCE PROGRAM DISTURB AND CHARGE LOSS 审中-公开
标题翻译：排水侧边线编程减少程序干扰和充电损失
公开(公告)号：WO2016057202A1
公开(公告)日：2016-04-14
申请号：PCT/US2015/051275
申请日：2015-09-21
申请人： SANDISK TECHNOLOGIES INC.
发明人： YUAN, Jiahui , DONG, Yingda , LU, Ching-Huang , ZHAO, Wei
IPC分类号： G11C11/56 , G11C16/04 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/3427 , G11C16/3459 , G11C2211/5621 , G11C2211/5648
摘要： Techniques are provided for programming the memory cells of a drain-side edge word line of a set of word lines before programming memory cells of any other word line of the set. Pass voltages applied to the other word lines act as stress pulses which redistribute holes in the charge-trapping material of the memory cells of the other word lines to reduce short-term charge loss and downshifting of the threshold voltage. Additionally, one or more initial program voltages used for the drain-side edge word line are relatively low and also act as stress pulses. The memory cells of the drain-side edge word line are programmed to a narrower Vth window than the memory cells of the other word lines. This compensates for a higher level of program disturb of erased state memory cells of the drain-side edge word line due to reduced channel boosting.
摘要翻译：提供了在编程集合的任何其他字线的存储器单元之前对一组字线集合的漏极边缘字线的存储器单元进行编程的技术。施加到其它字线的通过电压作为应力脉冲，其重新分配其它字线的存储单元的电荷捕获材料中的空穴，以减少阈值电压的短期电荷损耗和降档。此外，用于漏极侧边缘字线的一个或多个初始编程电压相对较低并且还用作应力脉冲。漏极侧边缘字线的存储单元被编程到比其它字线的存储单元窄的Vth窗口。这由于减少的信道增强而补偿了漏极侧边缘字线的擦除状态存储单元的编程干扰的较高水平。

10. 发明申请

WO2016025167A1 MULTI-PULSE PROGRAMMING CYCLE OF NON-VOLATILE MEMORY FOR ENHANCED DE-TRAPPING 审中-公开
标题翻译：用于增强脱钩的非易失性存储器的多脉冲编程周期
公开(公告)号：WO2016025167A1
公开(公告)日：2016-02-18
申请号：PCT/US2015/042504
申请日：2015-07-28
申请人： SANDISK TECHNOLOGIES INC.
发明人： KOH, Yee Lih , KUO, Tien-Chien , MUI, Man Lung , LEE, Juan Carlos
IPC分类号： G11C11/56 , G11C16/34
CPC分类号： G11C11/5628 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/3427 , G11C16/3459 , G11C2211/5621 , G11C2211/5648
摘要： When writing a multi-state non-volatile memory, a de-trapping operation is included in the programming cycle. To reduce the performance penalty of including a de-trapping operation, the programming cycle of a single series of increasing pulses alternating with verify operations is replaced with a cycle including a pulse from each of two or more staircases, where each staircase is for a corresponding subset of the data states. After the multiple pulses, but before the following verify, a de-trapping operation is inserted in the programming cycle.
摘要翻译：在写入多状态非易失性存储器时，编程周期中包含解除捕获操作。为了降低包括解除捕获操作的性能损失，与验证操作交替的单个增加脉冲序列的编程周期被包括来自两个或多个楼梯中的每一个的脉冲的周期替换，其中每个阶梯用于相应的数据状态的子集。在多个脉冲之后，但在进行以下验证之前，在编程周期中插入解除捕获操作。

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