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1. 发明申请

WO2016105814A1 FAULT TOLERANT AUTOMATIC DUAL IN-LINE MEMORY MODULE REFRESH 审中-公开
标题翻译：故障自动双向在线存储器模块刷新
公开(公告)号：WO2016105814A1
公开(公告)日：2016-06-30
申请号：PCT/US2015/062555
申请日：2015-11-24
申请人： INTEL CORPORATION
发明人： JAYAKUMAR, Sarathy , KUMAR, Mohan J.
IPC分类号： G06F13/16 , G06F12/02
CPC分类号： G06F11/1441 , G06F1/30 , G06F1/3275 , G06F11/2015 , G06F12/0246 , G06F12/0638 , G06F12/0891 , G06F2212/205 , G06F2212/7208 , G06F2212/7209 , G11C5/04 , G11C5/148 , G11C7/20 , G11C14/0036 , G11C14/0045
摘要： Methods and apparatus to fault tolerant Automatic DIMM (Dual In-line Memory Module) Refresh or ADR are described. In an embodiment, a processor includes non-volatile memory to store data from one or more volatile buffers of the processor. The data from the one or more volatile buffers of the processor are stored into the non-volatile memory in response to occurrence of an event that is to lead to a system reset or shut down. Other embodiments are also disclosed and claimed.
摘要翻译：描述了容错自动DIMM（双列直插式内存模块）刷新或ADR的方法和装置。在一个实施例中，处理器包括用于存储来自处理器的一个或多个易失性缓冲器的数据的非易失性存储器。响应于导致系统复位或关闭的事件的发生，来自处理器的一个或多个易失性缓冲器的数据被存储到非易失性存储器中。还公开并要求保护其他实施例。

2. 发明申请

WO2015171461A1 INTERCONNECT SYSTEMS AND METHODS USING HYBRID MEMORY CUBE LINKS 审中-公开
标题翻译：互连系统和使用混合存储器链接的方法
公开(公告)号：WO2015171461A1
公开(公告)日：2015-11-12
申请号：PCT/US2015/028873
申请日：2015-05-01
申请人： MICRON TECHNOLOGY, INC.
发明人： LEIDEL, John D.
IPC分类号： G06F13/16 , G06F12/00
CPC分类号： G06F3/0607 , G06F3/0659 , G06F3/0685 , G06F13/1621 , G06F13/1657 , G06F13/1673 , G06F13/1684 , G06F13/40 , G06F13/4022 , G06F13/4234 , G06F2212/205 , G11C7/1075 , G11C21/00
摘要： System on a Chip (SoC) devices include two packetized memory busses for conveying local memory packets and system interconnect packets. In an in situ configuration of a data processing system two or more SoCs are coupled with one or more hybrid memory cubes (HMCs). The memory packets enable communication with local HMCs in a given SoC's memory domain. The system interconnect packets enable communication between SoCs and communication between memory domains. In a dedicated routing configuration each SoC in a system has its own memory domain to address local HMCs and a separate system interconnect domain to address HMC hubs, HMC memory devices, or other SoC devices connected in the system interconnect domain.
摘要翻译：片上系统（SoC）设备包括用于传送本地存储器分组和系统互连分组的两个分组化存储器总线。在数据处理系统的原位配置中，两个或更多个SoC与一个或多个混合存储立方体（HMC）耦合。存储器分组使得能够与给定SoC的存储器域中的本地HMC进行通信。系统互连分组使得SoC之间的通信和存储器域之间的通信成为可能。在专用路由配置中，系统中的每个SoC都有自己的内存域来寻址本地HMC和单独的系统互连域，以解决连接在系统互连域中的HMC集线器，HMC存储设备或其他SoC设备。

3. 发明申请

WO2015066489A2 EFFICIENT IMPLEMENTATIONS FOR MAPREDUCE SYSTEMS 审中-公开
标题翻译： MAPREDUCE系统的有效实现
公开(公告)号：WO2015066489A2
公开(公告)日：2015-05-07
申请号：PCT/US2014/063457
申请日：2014-10-31
申请人： COGNITIVE ELECTRONICS, INC.
发明人： FELCH, Andrew, C. , DOUGHERTY, Thomas, M.
IPC分类号： G06F9/50
CPC分类号： G06F17/30336 , G06F9/5066 , G06F12/0238 , G06F12/0638 , G06F12/1018 , G06F17/30091 , G06F17/30345 , G06F17/30477 , G06F2212/205
摘要： In a system configured to execute one or more MapReduce applications, data stored in a file system may be accessed. In some embodiments, in response to input data being written to the file system by an application other than the MapReduce application(s), one or more Map functions may be executed on the input data. In some embodiments, [key, value] pairs generated via a Map function may be stored in a storage system organized into divisions storing [key, value] pairs corresponding to different keys, in which a [key, value] pair corresponding to a key handled by a first Reducer and a [key, value] pair corresponding to a key handled by a second Reducer may both be stored in the same division. In some embodiments, mapped [key, value] pairs corresponding to keys handled by multiple Reducers may be sent together to a group of Reducers.
摘要翻译：在配置为执行一个或多个MapReduce应用程序的系统中，可以访问存储在文件系统中的数据。在一些实施例中，响应于除了MapReduce应用之外的应用将输入数据写入文件系统，可以在输入数据上执行一个或多个Map函数。在一些实施例中，可以将经由Map函数生成的[键，值]对存储在存储系统中，该存储系统被组织成存储与不同键对应的[键，值]对的分区，其中与键对应的[键，值]对由第一Reducer处理并且与由第二Reducer处理的密钥相对应的[key，value]对可以存储在同一个分区中。在一些实施例中，与由多个缩减器处理的键相对应的映射[键，值]对可一起发送到一组缩减器。

4. 发明申请

WO2013101053A1 NON-VOLATILE RAM DISK 审中-公开
标题翻译：非易失性RAM盘
公开(公告)号：WO2013101053A1
公开(公告)日：2013-07-04
申请号：PCT/US2011/067829
申请日：2011-12-29
申请人： INTEL CORPORATION , CROSSLAND, James B. , OPFERMAN, Toby , FANNING, Blaise
发明人： CROSSLAND, James B. , OPFERMAN, Toby , FANNING, Blaise
IPC分类号： G06F12/02 , G06F13/16 , G11C13/02
CPC分类号： G06F12/0638 , G06F12/023 , G06F12/0238 , G06F12/0866 , G06F2212/202 , G06F2212/2024 , G06F2212/205 , G11C7/1072 , G11C13/0004 , G11C14/0036 , G11C14/0045
摘要： A method and system are disclosed. In one embodiment the method includes allocating several memory locations within a phase change memory and switch (PCMS) memory to be utilized as a Random Access Memory (RAM) Disk. The RAM Disk is created for use by a software application running in a computer system. The method also includes mapping at least a portion of the allocated amount of PCMS memory to the software application address space. Finally, the method also grants the software application direct access to at least a portion of the allocated amount of the PCMS memory.
摘要翻译：公开了一种方法和系统。在一个实施例中，该方法包括在相变存储器和交换机（PCMS）存储器内分配若干存储器位置，以用作随机存取存储器（RAM）盘。 RAM磁盘创建为由计算机系统中运行的软件应用程序使用。该方法还包括将分配的PCMS存储器的至少一部分映射到软件应用地址空间。最后，该方法还允许软件应用直接访问PCMS存储器的分配量的至少一部分。

5. 发明申请

WO2013028827A1 METHODS AND SYSTEMS FOR MAPPING A PERIPHERAL FUNCTION ONTO A LEGACY MEMORY INTERFACE 审中-公开
标题翻译：将外部功能映射到记忆体界面的方法和系统
公开(公告)号：WO2013028827A1
公开(公告)日：2013-02-28
申请号：PCT/US2012/052000
申请日：2012-08-23
申请人： RAMBUS INC. , PEREGO, Richard, E. , LINSTADT, John, Eric , BATRA, Pradeep , BROOKS, John, Welsford , WOO, Steven , LAI, Lawrence
发明人： PEREGO, Richard, E. , LINSTADT, John, Eric , BATRA, Pradeep , BROOKS, John, Welsford , WOO, Steven , LAI, Lawrence
IPC分类号： G06F13/14 , G06F13/16 , G11C7/10
CPC分类号： G06F3/061 , G06F3/0629 , G06F3/0685 , G06F12/00 , G06F12/0246 , G06F12/0638 , G06F12/10 , G06F13/385 , G06F13/4239 , G06F2212/2022 , G06F2212/205 , G06F2212/251 , G06F2212/7201 , G06F2212/7206 , G11C7/1072 , G11C14/0018 , Y02D10/14 , Y02D10/151
摘要： A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.
摘要翻译：存储器系统包括将命令和地址传送到主存储器模块的CPU。该模块包括缓冲电路，用于中继CPU和主存储器之间的命令和数据。存储器模块还包括嵌入式处理器，其共享对主存储器的访问以支持外围功能，例如图形处理，以改善整体系统性能。缓冲电路有助于CPU和外围处理器之间的指令和数据通信，以最小化或消除修改CPU的需要，从而减少采用具有集成处理能力的主存储器模块的实际障碍。

6. 发明申请

WO2010033365A1 AGGREGATION OF WRITE TRAFFIC TO A DATA STORE 审中-公开
标题翻译：将数据存储的写入流量集中到数据存储
公开(公告)号：WO2010033365A1
公开(公告)日：2010-03-25
申请号：PCT/US2009/055198
申请日：2009-08-27
申请人： MICROSOFT CORPORATION
发明人： CONG, Shi , BRENDER, Scott , MEHRA, Karan , MOSS, Darren G. , TIPTON, William R. , VERMA, Surendra
IPC分类号： G06F9/06 , G06F12/00
CPC分类号： G06F12/121 , G06F3/0611 , G06F3/0656 , G06F3/0673 , G06F11/1435 , G06F11/1471 , G06F12/0638 , G06F2212/2022 , G06F2212/205 , G06F2212/221 , G06F2212/2228 , G11C7/1006
摘要： A method and a processing device are provided for sequentially aggregating data to a write log included in a volume of a random-access medium. When data of a received write request is determined to be suitable for sequentially aggregating to a write log, the data may be written to the write log and a remapping tree, for mapping originally intended destinations on the random-access medium to one or more corresponding entries in the write log, may be maintained and updated. At time periods, a checkpoint may be written to the write log. The checkpoint may include information describing entries of the write log. One or more of the checkpoints may be used to recover the write log, at least partially, after a dirty shutdown. Entries of the write log may be drained to respective originally intended destinations upon an occurrence of one of a number of conditions.
摘要翻译：提供了一种方法和处理装置，用于将数据顺序地聚合到包括在随机存取介质的卷中的写入日志。当接收到的写入请求的数据被确定为适合于顺序聚合到写入日志时，数据可被写入写入日志和重新映射树，用于将随机访问介质上的原始目的地映射到一个或多个对应的写入日志中的条目可以被维护和更新。在时间段，检查点可能被写入写日志。检查点可以包括描述写入日志的条目的信息。一个或多个检查点可用于在脏关闭后至少部分恢复写入日志。在发生多个条件之一时，写入日志的条目可以被排放到相应的原始目的地。

7. 发明申请

WO2009052527A1 MANAGING MEMORY SYSTEMS CONTAINING COMPONENTS WITH ASYMMETRIC CHARACTERISTICS 审中-公开
标题翻译：管理包含具有不对称特性的组件的存储器系统
公开(公告)号：WO2009052527A1
公开(公告)日：2009-04-23
申请号：PCT/US2008/080559
申请日：2008-10-20
申请人： VIRIDENT SYSTEMS, INC. , OKIN, Kenneth A. , KARAMCHETI, Vijay
发明人： OKIN, Kenneth A. , KARAMCHETI, Vijay
IPC分类号： G11C11/00
CPC分类号： G06F12/02 , G06F11/1658 , G06F11/20 , G06F12/0246 , G06F12/06 , G06F12/08 , G06F12/10 , G06F2212/1032 , G06F2212/205 , G06F2212/7201 , G06F2212/7202 , G11C16/3418 , G11C16/3427
摘要： A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC.
摘要翻译：存储器控制器（MC）与重映射表相关联以允许访问包括非对称存储器的存储器系统中的内容。 MC从系统的内存管理单元（MMU）指定的物理地址接收来自中央处理单元（CPU）的内存读取或输入/输出（I / O）写入请求。 CPU使用MMU来管理CPU的内存操作，方法是将与CPU指令相关的虚拟地址转换为表示系统内存或I / O位置的物理地址。用于非对称存储器的MC配置为将MMU指定的物理地址作为附加类型的虚拟地址进行处理，在由MMU指定的物理地址与该地址与MC关联的物理存储器地址之间创建抽象层

8. 发明申请

WO2009052525A1 MANAGING MEMORY SYSTEMS CONTAINING COMPONENTS WITH ASYMMETRIC CHARACTERISTICS 审中-公开
标题翻译：管理包含不对称特性的组件的存储系统
公开(公告)号：WO2009052525A1
公开(公告)日：2009-04-23
申请号：PCT/US2008/080557
申请日：2008-10-20
申请人： VIRIDENT SYSTEMS, INC. , OKIN, Kenneth A. , KARAMCHETI, Vijay
发明人： OKIN, Kenneth A. , KARAMCHETI, Vijay
IPC分类号： G11C11/00
CPC分类号： G06F12/02 , G06F11/1658 , G06F11/20 , G06F12/0246 , G06F12/06 , G06F12/08 , G06F12/10 , G06F2212/1032 , G06F2212/205 , G06F2212/7201 , G06F2212/7202 , G11C16/3418 , G11C16/3427
摘要： A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC.
摘要翻译：存储器控制器（MC）与重映射表相关联，以使得能够访问包括非对称存储器的存储器系统中的内容。 MC从系统的存储器管理单元（MMU）指定的物理地址从中央处理单元（CPU）接收对存储器读取或输入/输出（I / O）写入的请求。通过将与CPU指令相关联的虚拟地址转换为表示系统内存或I / O位置的物理地址，CPU使用MMU来管理CPU的存储器操作。用于非对称存储器的MC被配置为处理MMU指定的物理地址作为附加类型的虚拟地址，在MMU指定的物理地址与该地址由MC关联的物理存储器地址之间创建一个抽象层。

9. 发明申请

WO2008055271A2 SEAMLESS APPLICATION ACCESS TO HYBRID MAIN MEMORY 审中-公开
标题翻译：无缝应用访问混合主存储器
公开(公告)号：WO2008055271A2
公开(公告)日：2008-05-08
申请号：PCT/US2007/083669
申请日：2007-11-05
申请人： VIRIDENT SYSTEMS, INC. , KARAMCHETI, Vijay , OKIN, Kenneth A. , GANAPATHY, Kumar , SINGHAI, Ashish , PAREKH, Rajesh
发明人： KARAMCHETI, Vijay , OKIN, Kenneth A. , GANAPATHY, Kumar , SINGHAI, Ashish , PAREKH, Rajesh
IPC分类号： G06F12/00
CPC分类号： G06F12/1009 , G06F3/0604 , G06F3/0628 , G06F3/0638 , G06F3/064 , G06F3/0646 , G06F3/0647 , G06F3/068 , G06F3/0685 , G06F9/5016 , G06F12/0207 , G06F12/0223 , G06F12/0292 , G06F12/08 , G06F12/10 , G06F12/121 , G06F12/1475 , G06F13/1657 , G06F13/1694 , G06F2212/205 , G06F2212/657 , Y02D10/13 , Y02D10/14 , Y02D10/22
摘要： A command from an application is received to access a data structure associated with one or more virtual addresses mapped to main memory. A first subset of the virtual addresses for the data structure having constituent addresses that are mapped to the symmetric memory components and a second subset of the virtual addresses for the data structure having constituent addresses that are mapped to the asymmetric memory components are identified. Data associated with the virtual address from the first physical addresses and data associated with the virtual addresses from the second physical addresses are accessed. The data associated with the symmetric and asymmetric memory components is accessed by the application without providing the application with an indication of whether the data is accessed within the symmetric memory component or the asymmetric memory component.
摘要翻译：接收来自应用程序的命令以访问与映射到主存储器的一个或多个虚拟地址相关联的数据结构。识别具有映射到对称存储器组件的组成地址的数据结构的虚拟地址的第一子集以及具有映射到非对称存储器组件的组成地址的数据结构的虚拟地址的第二子集。访问与来自第一物理地址的虚拟地址相关联的数据和与来自第二物理地址的虚拟地址相关联的数据。与对称和非对称存储器组件相关联的数据被应用程序访问，而不向应用程序提供在对称存储器组件或非对称存储器组件内是否访问数据的指示。

10. 发明申请

WO2008055270A2 WRITING TO ASYMMETRIC MEMORY 审中-公开
标题翻译：写入非对称记忆
公开(公告)号：WO2008055270A2
公开(公告)日：2008-05-08
申请号：PCT/US2007/083668
申请日：2007-11-05
申请人： VIRIDENT SYSTEMS, INC. , KARAMCHETI, Vijay , OKIN, Kenneth, A. , GANAPATHY, Kumar , SINGHAI, Ashish , PAREKH, Rajesh
发明人： KARAMCHETI, Vijay , OKIN, Kenneth, A. , GANAPATHY, Kumar , SINGHAI, Ashish , PAREKH, Rajesh
IPC分类号： G06F12/00
CPC分类号： G06F12/1009 , G06F3/0604 , G06F3/0628 , G06F3/0638 , G06F3/064 , G06F3/0646 , G06F3/0647 , G06F3/068 , G06F3/0685 , G06F9/5016 , G06F12/0207 , G06F12/0223 , G06F12/0292 , G06F12/08 , G06F12/10 , G06F12/121 , G06F12/1475 , G06F13/1657 , G06F13/1694 , G06F2212/205 , G06F2212/657 , Y02D10/13 , Y02D10/14 , Y02D10/22
摘要： A memory controller writes to a virtual address associated with data residing within an asymmetric memory component of main memory that is within a computer system and that has a symmetric memory component, while preserving proximate other data residing within the asymmetric memory component. The symmetric memory component within the main memory of the computer system is configured to enable random access write operations in which an address within a block of the symmetric memory component is written without affecting the availability of other addresses within the block of the symmetric memory component during the writing of that address. The asymmetric memory component is configured to enable block write operations in which writing to an address within a region of the asymmetric memory component affects the availability of other addresses within the region of the asymmetric memory component during the block write operations involving the address.
摘要翻译：存储器控制器写入与驻留在计算机系统内的主存储器的不对称存储器组件内并且具有对称存储器组件的数据相关联的虚拟地址，同时保留驻留在不对称内存组件。计算机系统的主存储器中的对称存储器组件被配置为启用随机存取写入操作，其中写入对称存储器组件的块内的地址而不影响对称存储器组件的块期间其他地址的可用性该地址的写作。非对称存储器组件被配置为启用块写入操作，其中在涉及地址的块写入操作期间，写入到非对称存储器组件的区域内的地址影响非对称存储器组件的区域内的其他地址的可用性。 p>

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