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1. 发明申请

WO2019133243A1 DRIFT MITIGATION WITH EMBEDDED REFRESH 审中-公开
公开(公告)号：WO2019133243A1
公开(公告)日：2019-07-04
申请号：PCT/US2018/064928
申请日：2018-12-11
申请人： MICRON TECHNOLOGY, INC.
发明人： TORTORELLI, Innocenzo , PIROVANO, Agostino , REDAELLI, Andrea , PELLIZZER, Fabio , WANG, Hongmei
IPC分类号： G11C13/00
CPC分类号： G11C29/00 , G11C13/00 , G11C13/0004 , G11C13/0033 , G11C13/004 , G11C29/52 , G11C2013/0052 , G11C2213/71 , H01L27/2409 , H01L27/2427 , H01L27/2463 , H01L27/2481 , H01L45/06 , H01L45/08 , H01L45/1233 , H01L45/142 , H01L45/143 , H01L45/144
摘要： Methods, systems, and devices for drift mitigation with embedded refresh are described. A memory cell may be written to and read from using write and read voltages, respectively, that are of different polarities. For example, a memory cell may be written to by applying a first write voltage and may be subsequently read from by applying a first read voltage of a first polarity. At least one additional (e.g., a second) read voltage-a setback voltage-of a second polarity may be utilized to return the memory cell to its original state. Thus the setback voltage may mitigate a shift in the voltage distribution of the cell caused by the first read voltage.

2. 发明申请

WO2017196423A1 USING NON-VOLATILE MEMORY BAD BLOCKS 审中-公开
标题翻译：使用非易失性存储器坏块
公开(公告)号：WO2017196423A1
公开(公告)日：2017-11-16
申请号：PCT/US2017/018548
申请日：2017-02-19
申请人： SANDISK TECHNOLOGIES LLC
发明人： SHEPARD, Zachary , SEHGAL, Rohit
IPC分类号： G11C29/00 , G11C29/42 , G11C29/44 , G06F11/10 , G11C16/34 , G11C29/04
CPC分类号： G11C29/76 , G06F11/1048 , G11C16/06 , G11C16/349 , G11C29/42 , G11C29/4401 , G11C29/52 , G11C29/88 , G11C2029/0409 , G11C2029/4402
摘要： A system for using bad blocks in a memory system is proposed. The system includes accessing an identification of a plurality of bad blocks and corresponding error codes which, for example, were generated during a manufacturing test and stored on the memory integrated circuit. The system determines which blocks of the plurality of bad blocks to test for being still usable and which blocks of the plurality of bad blocks not to test for being still usable based on corresponding error codes. For each bad block that should be tested, a test from a plurality of tests is chosen based on the corresponding error code in order to determine if the bad block is still usable. Those blocks determined to be still usable are subsequently used to store non- mission critical information.
摘要翻译：提出了一种在存储器系统中使用坏块的系统。该系统包括访问例如在制造测试期间产生并存储在存储器集成电路上的多个坏块的标识和相应的错误代码。系统根据相应的错误代码确定要测试的多个坏块中的哪些块仍然可用，以及确定多个坏块中的哪些块不被测试为仍然可用。对于每个应该测试的坏块，根据相应的错误代码选择来自多个测试的测试，以便确定坏块是否仍然可用。被确定为仍然可用的那些块随后被用于存储非关键任务信息。

3. 发明申请

WO2017192201A1 MULTI-DIE DATA STORAGE DEVICE WITH IN-MEMORY PARITY CIRCUITRY 审中-公开
标题翻译：具有存储器奇偶校验电路的多模数据存储设备
公开(公告)号：WO2017192201A1
公开(公告)日：2017-11-09
申请号：PCT/US2017/019817
申请日：2017-02-28
申请人： SANDISK TECHNOLOGIES LLC
发明人： HSU, Hua-Ling Cynthia , MANOHAR, Abhijeet , DUTTA, Deepanshu
IPC分类号： G06F11/10
CPC分类号： G06F11/1072 , G06F3/0619 , G06F3/064 , G06F3/0647 , G06F3/0688 , G06F11/108 , G11C29/52
摘要： A data storage device includes a first memory die having memory cells and a first transfer data latch. The data storage device also includes a second memory die having second memory cells and a second transfer data latch. A bus is coupled to the first memory die and the second memory die. The data storage device also includes a controller coupled to the bus. The controller is configured to cause the first transfer data latch and the second transfer data latch to store first data responsive to sending the first data to the first memory die for programming of the first data to a first word line of the first memory cells.
摘要翻译：数据存储装置包括具有存储器单元和第一传输数据锁存器的第一存储器裸片。数据存储装置还包括具有第二存储器单元和第二传输数据锁存器的第二存储器裸片。总线耦合到第一存储器裸片和第二存储器裸片。数据存储设备还包括耦合到总线的控制器。控制器被配置为响应于将第一数据发送到第一存储器管芯而使第一传输数据锁存器和第二传输数据锁存器存储第一数据，以将第一数据编程到第一存储器单元的第一字线。 / p>

4. 发明申请

WO2017160488A1 ERROR CORRECTION CODE PROCESSING AND DATA SHAPING 审中-公开
标题翻译：错误纠正码处理和数据整形
公开(公告)号：WO2017160488A1
公开(公告)日：2017-09-21
申请号：PCT/US2017/019456
申请日：2017-02-24
申请人： SANDISK TECHNOLOGIES LLC
发明人： ALROD, Idan , SHARON, Eran , NAVON, Ariel
IPC分类号： G06F11/10
CPC分类号： G06F3/0604 , G06F3/064 , G06F3/0679 , G06F11/1012 , G06F11/1068 , G06F2212/40 , G06F2212/401 , G06F2212/403 , G11C16/34 , G11C16/3418 , G11C16/349 , G11C16/3495 , G11C29/52 , G11C2211/5647
摘要： A device includes a memory and a controller including a data shaping engine. The data shaping engine is configured to apply a mapping to input data that includes one or more m-tuples of bits to generate transformed data. The transformed data includes one or more n-tuples of bits, and n is greater than m. A relationship of a gray coding of m-tuples to a gray coding of n-tuples is indicated by the mapping. The input data includes a first number of bit values that represent a particular logical state, and the transformed data includes a second number of bit values that represent the particular logical state, the second number of bit values being less than the first number of bit values.
摘要翻译：一种设备包括存储器和包括数据整形引擎的控制器。数据整形引擎被配置为将映射应用于包括一个或多个m位元组的元素的输入数据以生成变换后的数据。经变换的数据包括一个或多个比特的n元组，并且n大于m。通过映射指示m元组的灰度编码与n元组的灰度编码之间的关系。输入数据包括表示特定逻辑状态的第一数量的比特值，并且变换后的数据包括表示特定逻辑状态的第二数量的比特值，比特值的第二数量小于第一比特值数量

5. 发明申请

WO2017087076A1 SEPARATE LINK AND ARRAY ERROR CORRECTION IN A MEMORY SYSTEM 审中-公开
标题翻译：存储器系统中的单独链路和阵列错误校正
公开(公告)号：WO2017087076A1
公开(公告)日：2017-05-26
申请号：PCT/US2016/054175
申请日：2016-09-28
申请人： QUALCOMM INCORPORATED
发明人： SUH, Jungwon , WEST, David Ian
IPC分类号： G06F11/10
CPC分类号： G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1048 , G11C29/52
摘要： A memory device may include link error correction code (ECC) decoder and correction circuitry. The ECC decoder and correction circuitry may be arranged in a write path and configured for link error detection and correction of write data received over a data link. The memory device may also include memory ECC encoder circuitry. The memory ECC encoder circuitry may be arranged in the write path and configured for memory protection of the write data during storage in a memory array.
摘要翻译：存储器件可以包括链接错误校正码（ECC）解码器和校正电路。 ECC解码器和校正电路可以被布置在写入路径中并且被配置用于通过数据链路接收的写入数据的链路错误检测和校正。存储器装置还可以包括存储器ECC编码器电路。存储器ECC编码器电路可以被布置在写入路径中并且被配置用于在存储在存储器阵列期间的写入数据的存储器保护。

6. 发明申请

WO2017087075A1 PROTECTING AN ECC LOCATION WHEN TRANSMITTING CORRECTION DATA ACROSS A MEMORY LINK 审中-公开
标题翻译：在存储器链路上传输校正数据时保护ECC位置
公开(公告)号：WO2017087075A1
公开(公告)日：2017-05-26
申请号：PCT/US2016/054162
申请日：2016-09-28
申请人： QUALCOMM INCORPORATED
发明人： WEST, David Ian , SUH, Jungwon
IPC分类号： G06F11/10
CPC分类号： G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F11/1048 , G11C29/52
摘要： A memory sub-system may include a memory controller having error correction code (ECC) encoder/decoder logic. The memory controller may be configured to embed link ECC parity bits in unused data mask bits and/or in a mask write data during a mask write operation. The memory controller may also be configured to protect at least a location of the link ECC parity bits during the mask write operation.
摘要翻译：存储器子系统可以包括具有纠错码（ECC）编码器/解码器逻辑的存储器控制器。存储器控制器可以被配置为在掩码写入操作期间将链接ECC奇偶校验位嵌入到未使用的数据掩码位中和/或掩码写入数据中。存储器控制器还可以被配置为在掩码写入操作期间至少保护链接ECC奇偶校验位的位置。

7. 发明申请

WO2017058523A1 DATA STORAGE DEVICE WITH A MEMORY DIE THAT INCLUDES AN INTERLEAVER 审中-公开
标题翻译：具有包含交互器的存储器的数据存储设备
公开(公告)号：WO2017058523A1
公开(公告)日：2017-04-06
申请号：PCT/US2016/051807
申请日：2016-09-15
申请人： SANDISK TECHNOLOGIES LLC
发明人： SHARON, Eran , NAVON, Ariel , CHU, Alexander Tsang-nam , TSAI, Wanfang , ALROD, Idan
IPC分类号： G06F3/06 , G06F11/10
CPC分类号： G06F11/1072 , G06F3/0611 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F3/0688 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/26 , G11C29/52 , H03M13/2792
摘要： A data storage device includes a set of latches, read/write circuitry, a memory, and an interleaver. The set of latches is configured to receive data. The read/write circuitry is coupled to the set of latches. The memory is coupled to the read/write circuitry. The interleaver is configured to interleave the data and to cause the read/write circuitry to program the interleaved data to the memory. The set of latches, the read/write circuitry, the memory, and the interleaver are integrated within a common die.
摘要翻译：数据存储设备包括一组锁存器，读/写电路，存储器和交织器。锁存器组被配置为接收数据。读/写电路耦合到该组锁存器。存储器耦合到读/写电路。交织器被配置为交织数据并使得读/写电路将交织的数据编程到存储器。锁存器组，读/写电路，存储器和交织器集成在公共管芯内。

8. 发明申请

WO2017058111A1 METHOD OF ERROR DETECTION IN A TOGGLE ELECTRIC FIELD MAGNETIC RANDOM ACCESS MEMORY (TEF-RAM) DEVICE AND TEF-RAM DEVICE 审中-公开
标题翻译：手动电磁场随机存取存储器（TEF-RAM）器件和TEF-RAM器件中的错误检测方法
公开(公告)号：WO2017058111A1
公开(公告)日：2017-04-06
申请号：PCT/SG2016/050476
申请日：2016-09-27
申请人： AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
发明人： LI, Fei , LUA, Sunny Yan Hwee
IPC分类号： G11C29/04 , G11C11/16 , H01L27/24
CPC分类号： G11C29/04 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C29/52 , H01L27/222
摘要： There is provided a method of error detection in a toggle electric field magnetic random access memory (TEF-RAM) device. The method includes performing a first read operation on a memory cell of the TEF-RAM device to obtain a first read output of the memory cell, performing a first write operation on the memory cell after the first read operation, performing a second read operation on the memory cell after the first write operation to obtain a second read output of the memory cell, and determining whether an error exists with the memory cell based on the first read output and the second read output. There is also provided an error detection module and a TEF-RAM device having the error detection module.
摘要翻译：提供了一种在切换电场磁随机存取存储器（TEF-RAM）装置中的错误检测方法。该方法包括对TEF-RAM设备的存储单元执行第一读取操作以获得存储单元的第一读取输出，在第一次读取操作之后对存储器单元执行第一次写入操作，对第一次读取操作执行第二次读取操作所述存储单元在所述第一写入操作之后获得所述存储单元的第二读取输出，以及基于所述第一读取输出和所述第二读取输出来确定是否存在与所述存储单元的错误。还提供了具有错误检测模块的错误检测模块和TEF-RAM装置。

9. 发明申请

WO2017039949A1 MEMORY DEVICE ON-DIE ERROR CHECKING AND CORRECTING CODE 审中-公开
标题翻译：记忆体设备错误检查和修正代码
公开(公告)号：WO2017039949A1
公开(公告)日：2017-03-09
申请号：PCT/US2016/045643
申请日：2016-08-04
申请人： INTEL CORPORATION
发明人： HALBERT, John B , BAINS, Kuljit S
IPC分类号： G06F11/10
CPC分类号： G06F11/1048 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1068 , G11C11/401 , G11C29/42 , G11C29/52 , H03M13/095 , H03M13/6566
摘要： In a system where a memory device performs on-die ECC, the ECC operates on N-bit data words as two (N/2)-bit segments, with a code matrix having a corresponding N codes that can be operated on as a first portion of (N/2) codes and a second portion of (N/2) codes to compute first and second error checks for first and second (N/2)-bit segments of the data word, respectively. In the code matrix, a bitwise XOR of any two codes in the first portion of the code matrix or any two codes in the second portion of the code matrix results in a code that is either not in the code matrix or is in the other portion of the code matrix. Thus, a miscorrected double bit error in one portion causes a bit to be toggled in the other portion instead of creating a triple bit error.
摘要翻译：在存储器件执行管芯ECC的系统中，ECC对N位数据字进行二（N / 2）位段的操作，其中码矩阵具有对应的N个代码，可以作为第一（N / 2）码的一部分和（N / 2）码的第二部分，分别计算数据字的第一和第二（N / 2）位段的第一和第二错误检查。在代码矩阵中，代码矩阵的第一部分中的任何两个代码的按位XOR或代码矩阵的第二部分中的任何两个代码产生不在代码矩阵中的代码，或者在另一部分中的代码矩阵。因此，一个部分中的错误的双位错误导致在另一部分中切换位而不是产生三位错误。

10. 发明申请

WO2017027094A1 SOFT BIT TECHNIQUES FOR READING A DATA STORAGE DEVICE 审中-公开
标题翻译：用于读取数据存储设备的软比特技术
公开(公告)号：WO2017027094A1
公开(公告)日：2017-02-16
申请号：PCT/US2016/036912
申请日：2016-06-10
申请人： SANDISK TECHNOLOGIES LLC
发明人： SHARON, Eran , NAVON, Ariel , ALROD, Idan , BAZARSKY, Alexander
IPC分类号： G11C11/56 , G11C16/28
CPC分类号： G06F11/1048 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1068 , G11C11/5642 , G11C16/28 , G11C29/52
摘要： A data storage device includes a memory, a first module, and a second module. The first module is configured to sense data stored at the memory to generate a first set of soft bits having a first number of bits. The second module is configured to perform an operation using the first set of soft bits to generate a second set of soft bits having a second number of bits that is less than the first number of bits. In an illustrative implementation, the second set of soft bits is used in connection with a three-stage decoding process to decode a set of hard bits that represents the data.
摘要翻译：数据存储装置包括存储器，第一模块和第二模块。第一模块被配置为感测存储在存储器中的数据，以产生具有第一位数的第一组软比特。第二模块被配置为使用第一组软比特来执行操作，以产生具有小于第一比特数的第二比特数的第二组软比特。在说明性实现中，第二组软比特与三级解码过程结合使用，以对表示数据的一组硬比特进行解码。

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