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1. 发明申请

WO2017172287A2 READ DELIVERY FOR MEMORY SUBSYSTEM WITH NARROW BANDWIDTH REPEATER CHANNEL 审中-公开
标题翻译：使用窄带重复频道读取存储子系统的传送
公开(公告)号：WO2017172287A2
公开(公告)日：2017-10-05
申请号：PCT/US2017/021005
申请日：2017-03-06
申请人： INTEL CORPORATION
发明人： NALE, Bill , VOGT, Pete
IPC分类号： G06F13/40 , G06F13/16
CPC分类号： G06F13/16 , G06F3/061 , G06F3/0629 , G06F3/0631 , G06F3/0685 , G06F13/1678 , G06F13/4018 , G11C5/04 , G11C5/06 , G11C7/10
摘要： A system includes a repeater architecture for reads where memory connects to a host with one bandwidth, and repeats the channel with a lower bandwidth. A memory circuit includes a first group of read signal lines to couple point-to-point between a first group of memory devices and a host device. The memory circuit includes a second, smaller group of read signal lines to couple point-to-point between the first group and a second group of memory devices, to extend the memory channel to the second group. The memory circuit includes a repeater to share read bandwidth between the first and second groups of memory devices, with up to a portion of the bandwidth for reads to the second group of memory devices, and at least an amount equal to the bandwidth less the portion for reads to the first group of memory devices.
摘要翻译：系统包括用于读取的转发器架构，其中存储器使用一个带宽连接到主机，并以较低的带宽重复该通道。存储器电路包括第一组读取信号线，以在第一组存储器设备与主机设备之间点对点地耦合。存储器电路包括用于在第一组和第二组存储器件之间点对点地耦合的第二较小组读信号线，以将存储器通道扩展到第二组。存储器电路包括中继器，用于在第一和第二组存储器件之间共享读取带宽，其中至多一部分带宽用于读取第二组存储器件，并且至少等于带宽减去部分读取第一组内存设备。

2. 发明申请

WO2016137503A1 MEMORY MODULE VOLTAGE REGULATOR MODULE (VRM) 审中-公开
标题翻译：存储器模块电压调节器模块（VRM）
公开(公告)号：WO2016137503A1
公开(公告)日：2016-09-01
申请号：PCT/US2015/018054
申请日：2015-02-27
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： BACCHUS, Reza, M , BENEDICT, Melvin, K , CONTRERAS, Stephen, F , POPE, Eric, L , SIDES, Chi, K , HUANG, Chun-Pin
IPC分类号： G11C5/14
CPC分类号： G11C11/4074 , G11C5/04 , G11C5/06 , G11C5/10 , G11C5/14 , G11C5/147 , G11C11/401
摘要： An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. At least one stitching capacitor is to couple the first power plane to a second power plane.
摘要翻译：根据本公开的一个方面的示例性设备包括具有电压调节器模块（VRM）的存储器模块，用于接收输入功率并在第一电力平面向输出功率输送到存储器模块的组件。至少一个缝合电容器将第一电力平面耦合到第二电力平面。

3. 发明申请

WO2015191243A1 MEMORY MODULE 审中-公开
标题翻译：记忆模块
公开(公告)号：WO2015191243A1
公开(公告)日：2015-12-17
申请号：PCT/US2015/031324
申请日：2015-05-18
申请人： SANDISK TECHNOLOGIES INC.
发明人： D'ABREU, Manuel Antonio
IPC分类号： H01L25/0652 , G11C5/025
CPC分类号： H01L27/11551 , G11C5/025 , G11C5/04 , G11C5/06 , H01L23/3128 , H01L24/13 , H01L24/14 , H01L24/16 , H01L25/0652 , H01L25/18 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L2224/13025 , H01L2224/14181 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2924/15192 , H01L2924/15311 , H01L2924/157
摘要： A data storage device includes a memory die including a plurality of storage elements arranged in a three dimensional (3D) memory configuration and a controller die coupled to the memory die via a bus including a plurality of electrical contacts between adjacent surfaces of the memory die and the controller die. A method performed at the data storage device includes receiving, at the controller die, data to be stored at the memory die and generating a codeword representing the data. The codeword includes a particular number of bits. The method also includes sending signals from the controller die to the memory die via the plurality of electrical contacts. The plurality of electrical contacts includes at least as many electrical contacts as the particular number of bits of the codeword, and the signals representing the codeword are sent from the controller die to the memory die in parallel.
摘要翻译：数据存储装置包括：存储器管芯，其包括以三维（3D）存储器配置布置的多个存储元件;以及控制器裸片，其经由总线耦合到存储器管芯，该总线包括存储管芯的相邻表面之间的多个电触头，控制器死机。在数据存储装置中执行的方法包括在控制器管芯处接收要存储在存储管芯处的数据并产生表示数据的代码字。码字包括特定位数。该方法还包括经由多个电触点将信号从控制器管芯发送到存储器管芯。多个电触头包括与码字的特定位数至少相同的电触点，并且表示码字的信号被并行地从控制器管芯发送到存储器管芯。

4. 发明申请

WO2014130413A1 INTERCONNECTIONS FOR 3D MEMORY 审中-公开
标题翻译：三维存储器的互连
公开(公告)号：WO2014130413A1
公开(公告)日：2014-08-28
申请号：PCT/US2014/016791
申请日：2014-02-18
申请人： MICRON TECHNOLOGY, INC.
发明人： TANZAWA, Toru
IPC分类号： H01L27/115
CPC分类号： G11C5/063 , G11C5/02 , G11C5/06 , G11C7/12 , G11C7/222 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , H01L27/11524 , H01L27/11529 , H01L27/11551
摘要： Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.
摘要翻译：提供了用于3D存储器的互连的装置和方法。一个示例性设备可以包括包括多对材料的材料堆叠，每对材料包括在绝缘材料上形成的导电线。一叠材料具有在沿第一方向延伸的一个边缘处形成的阶梯结构。每个阶梯步骤包括一对材料之一。第一互连件耦合到阶梯级的导线，第一互连件在基本上垂直于楼梯台阶的第一表面的第二方向上延伸。

5. 发明申请

WO2014123778A1 SYSTEM AND METHOD OF PROGRAMMING A MEMORY CELL 审中-公开
标题翻译：编程存储器单元的系统和方法
公开(公告)号：WO2014123778A1
公开(公告)日：2014-08-14
申请号：PCT/US2014/014132
申请日：2014-01-31
申请人： QUALCOMM INCORPORATED
发明人： LI, Xia , YANG, Bin
IPC分类号： G11C17/16
CPC分类号： G11C17/18 , G06F17/5045 , G11C5/06 , G11C5/146 , G11C7/12 , G11C11/40 , G11C11/404 , G11C11/5692 , G11C16/04 , G11C17/16 , G11C2211/4016
摘要： A method includes selectively creating a first breakdown condition and a second breakdown condition at a semiconductor transistor structure. The first breakdown condition is between a source overlap region of the semiconductor transistor structure and a gate of the semiconductor transistor structure. The second breakdown condition is between a drain overlap region of the semiconductor transistor structure and the gate.
摘要翻译：一种方法包括在半导体晶体管结构中选择性地产生第一击穿条件和第二击穿条件。第一击穿条件在半导体晶体管结构的源极重叠区域和半导体晶体管结构的栅极之间。第二击穿条件在半导体晶体管结构的漏极重叠区域和栅极之间。

6. 发明申请

WO2013188654A1 3D MEMORY HAVING VERTICAL SWITCHES WITH SURROUND GATES AND METHOD THEREOF 审中-公开
标题翻译：具有环形门的垂直开关的3D存储器及其方法
公开(公告)号：WO2013188654A1
公开(公告)日：2013-12-19
申请号：PCT/US2013/045636
申请日：2013-06-13
申请人： SANDISK 3D LLC
发明人： CHEN, Yung-Tin , RADIGAN, Steven John , SCHEUERLEIN, Roy E. , CERNEA, Raul-Adrian
IPC分类号： H01L27/24 , G11C13/00
CPC分类号： H01L27/249 , G06F12/0238 , G11C5/025 , G11C5/06 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C2213/71 , H01L21/76877 , H01L27/1052 , H01L27/2454 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： A vertical switching layer of a 3D memory device serves to switch a set of vertical local bit lines to a corresponding set of global bit lines, the vertical switching layer being a 2D array of TFT channels of vertical thin-film transistors (TFTs) aligned to connect to an array of local bit lines, each TFT switching a local bit line to a corresponding global bit line. The TFTs in the array have a separation of lengths Lx and Ly along the x- and y-axis respectively such that a gate material layer forms a surround gate around each TFT in an x-y plane and has a thickness that merges to form a row select line along the x-axis while maintaining a separation of length Ls between individual row select lines. The surround gate improves the switching capacity of the TFTs.
摘要翻译： 3D存储器件的垂直切换层用于将一组垂直局部位线切换到相应的全局位线集合，垂直切换层是垂直薄膜晶体管（TFT）的TFT通道的2D阵列，其与连接到本地位线阵列，每个TFT将局部位线切换到相应的全局位线。阵列中的TFT分别具有沿着x轴和y轴的长度Lx和Ly的间隔，使得栅极材料层在xy平面内围绕每个TFT形成环绕栅，并且具有合并以形成行选择的厚度沿x轴线，同时保持单独行选择线之间的长度Ls的间隔。环绕栅极提高了TFT的开关容量。

7. 发明申请

WO2013188573A1 METHOD FOR FORMING STAIRCASE WORD LINES IN A 3D NON-VOLATILE MEMORY HAVING VERTICAL BIT LINES 审中-公开
标题翻译：在具有垂直位线的3D非易失性存储器中形成站点字线的方法
公开(公告)号：WO2013188573A1
公开(公告)日：2013-12-19
申请号：PCT/US2013/045481
申请日：2013-06-12
申请人： SANDISK 3D LLC
发明人： CHIEN, Henry , CERNEA, Raul-Adrian
IPC分类号： H01L27/24 , G11C13/00 , H01L21/768
CPC分类号： H01L27/249 , G06F12/0238 , G11C5/025 , G11C5/06 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C2213/71 , H01L21/76877 , H01L27/1052 , H01L27/2454 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： A 3D nonvolatile memory has memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes stacked in the z-direction over a semiconductor substrate. It has vertical local bit lines and a plurality of staircase word lines. Each staircase word line has a series of alternating segments and risers elongated respectively in the x-direction and z-direction traversing across the plurality of planes in the z-direction with a segment in each plane. Methods of forming a slab of multi-plane memory with staircase word lines include processes with one masking and with two maskings for forming each plane.
摘要翻译： 3D非易失性存储器具有以由具有x，y和z方向的直角坐标限定的三维图案布置的存储元件，并且在半导体衬底上沿z方向堆叠多个平行平面。它具有垂直的局部位线和多个阶梯字线。每个楼梯字线具有一系列交替的段和分别在x方向和z方向上伸长的一系列交替的段和沿着Z方向跨越多个平面的每个平面中的段。形成具有阶梯字线的多平面存储器的平板的方法包括具有一个掩模和用于形成每个平面的两个掩模的处理。

8. 发明申请

WO2013181603A2 INTER-CHIP MEMORY INTERFACE STRUCTURE 审中-公开
标题翻译：互联芯片内存接口结构
公开(公告)号：WO2013181603A2
公开(公告)日：2013-12-05
申请号：PCT/US2013/043714
申请日：2013-05-31
申请人： QUALCOMM INCORPORATED
发明人： SUH, Jungwon , CHUN, Dexter T.
IPC分类号： G11C5/04 , G06F13/16 , G06F13/42 , G11C5/06 , G11C7/10 , H01L27/00
CPC分类号： G11C5/06 , G11C5/04 , G11C5/063 , G11C7/02 , G11C7/222 , H01L25/0657 , H01L25/105 , H01L2224/16225 , H01L2224/48227 , H01L2225/0651 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311
摘要： In an embodiment, a stacked package-on-package system has a memory die (102; 104) and a logic die (106). The memory die comprises a first memory (306) and a second memory (308), each operated independently of the other, and each having an inter-chip interface (310; 312) electrically connected to the logic die. The logic die has two independent clock sources (318; 322), one to provide a first clock signal to the first memory, and the other clock source to provide a second clock signal to the second memory.
摘要翻译：在一个实施例中，堆叠封装的封装系统具有存储管芯（102; 104）和逻辑管芯（106）。存储器管芯包括第一存储器（306）和第二存储器（308），每个存储器（306）和第二存储器（308）独立于另一个独立地操作，并且每个具有电连接到逻辑管芯的芯片间接口（310; 312）。逻辑管芯具有两个独立的时钟源（318; 322），一个用于向第一存储器提供第一时钟信号，另一个时钟源提供第二时钟信号给第二存储器。

9. 发明申请

WO2013078294A2 LAYOUTS FOR MEMORY AND LOGIC CIRCUITS IN A SYSTEM-ON-CHIP 审中-公开
标题翻译：用于系统即插即用中的存储器和逻辑电路的布线
公开(公告)号：WO2013078294A2
公开(公告)日：2013-05-30
申请号：PCT/US2012/066236
申请日：2012-11-21
申请人： MARVELL WORLD TRADE LTD. , HOLT, Joseph , MADER, Roy , GREINER, Brandon , ANDERSON, Scott B.
发明人： HOLT, Joseph , MADER, Roy , GREINER, Brandon , ANDERSON, Scott B.
IPC分类号： G06F17/50 , H01L27/02
CPC分类号： G11C5/06 , G06F17/505 , G06F17/5072 , G11C5/02 , H01L27/0207 , H01L27/105
摘要： An integrated circuit including a plurality of memory circuits and a plurality of logic circuits. The plurality of memory circuits is arranged on a die along a plurality of rows and a plurality of columns. Each memory circuit includes a plurality of memory cells. The plurality of logic circuits is arranged on the die between the plurality of memory circuits along the plurality of rows and the plurality of columns. The plurality of logic circuits is configured to communicate with one or more of the memory circuits.
摘要翻译：一种集成电路，包括多个存储电路和多个逻辑电路。多个存储电路沿着多行和多列布置在管芯上。每个存储器电路包括多个存储单元。多个逻辑电路沿着多个行和多个列被布置在多个存储器电路之间的管芯上。多个逻辑电路被配置为与一个或多个存储器电路进行通信。

10. 发明申请

WO2013066342A1 STRUCTURE OF A SWITCHING DEVICE IN AN ARRAY 审中-公开
标题翻译：阵列中的切换装置的结构
公开(公告)号：WO2013066342A1
公开(公告)日：2013-05-10
申请号：PCT/US2011/059314
申请日：2011-11-04
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. , NICKEL, Janice H
发明人： NICKEL, Janice H
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： G11C5/025 , G11C5/02 , G11C5/06 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C2213/77 , H01L27/222 , H01L27/24 , H01L43/08 , H01L45/08 , H01L45/122 , H01L45/146
摘要： A switching device has a bottom conductor, a top conductor, and a device body formed between the top and bottom conductors. The device body has a switching layer that is switchable by means of current passed through the device body and between the top and bottom conductors. A lower via connects the bottom conductor to the device body. The width of the lower via is smaller than a width of the device body.
摘要翻译：开关装置具有底部导体，顶部导体和形成在顶部和底部导体之间的器件本体。器件本体具有开关层，其可以通过穿过器件本体的电流和顶部和底部导体之间的切换。下部通孔将底部导体连接到设备主体。下通孔的宽度小于设备主体的宽度。

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