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1. 发明申请

WO2016007372A1 SELECTIVE SENSE AMPLIFIER ENABLEMENT 审中-公开
标题翻译：选择性感应放大器启动
公开(公告)号：WO2016007372A1
公开(公告)日：2016-01-14
申请号：PCT/US2015/039006
申请日：2015-07-02
申请人： SANDISK TECHNOLOGIES INC.
发明人： D'ABREU, Manuel Antonio
IPC分类号： G11C7/08 , G11C8/10 , G11C8/12 , G11C13/00 , G11C16/08 , G11C16/26 , G11C16/28 , G11C7/10 , G11C7/14
CPC分类号： G11C16/28 , G11C7/08 , G11C7/1027 , G11C7/14 , G11C8/12 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C13/0028 , G11C13/004 , G11C16/08 , G11C16/26 , G11C2013/0054 , G11C2213/18 , G11C2213/71
摘要： A method includes, in a data storage device, receiving a read command to read a portion of a wordline of a memory. The method also includes determining a first and a last storage element of the wordline to identify a set of storage elements. The method includes determining a first set and a second set of sense amplifiers of multiple sense amplifiers coupled to the wordline. The first set of sense amplifiers is coupled to the set of storage elements and the second set of sense amplifiers is coupled to one or more storage elements of the wordline other than the first set of storage elements. The method includes reading data by applying a read voltage to the wordline and providing a sense enable signal to each sense amplifier of the first set of sense amplifiers while each sense amplifier of the second set of sense amplifiers is disabled.
摘要翻译：一种方法包括在数据存储装置中接收读取命令以读取存储器的字线的一部分。该方法还包括确定字线的第一和最后存储元件以识别一组存储元件。该方法包括确定耦合到字线的多个读出放大器的第一组和第二组读出放大器。第一组读出放大器被耦合到该组存储元件，并且第二组读出放大器被耦合到除第一组存储元件之外的字线的一个或多个存储元件。该方法包括：通过对字线施加读取电压并且将读出使能信号提供给第一组读出放大器的每个读出放大器，同时禁用第二组读出放大器的每个读出放大器来读取数据。

2. 发明申请

WO2013138115A1 STATISTICAL DISTRIBUTION BASED VARIABLE-BIT ERROR CORRECTION CODING 审中-公开
标题翻译：基于统计分布的可变位错误校正编码
公开(公告)号：WO2013138115A1
公开(公告)日：2013-09-19
申请号：PCT/US2013/029175
申请日：2013-03-05
申请人： SANDISK TECHNOLOGIES INC.
发明人： PANCHOLI, Deepak , D'ABREU, Manuel Antonio , NAIR, Radhakrishnan , SKALA, Stephen
IPC分类号： G06F11/10
CPC分类号： H03M7/4093 , G06F11/1012 , H03M7/40 , H03M7/4031 , H03M7/405 , H03M13/00 , H03M13/21 , H03M13/25 , H03M13/255 , H03M13/258 , H03M13/2927 , H03M13/35 , H03M13/6318 , H04N19/13 , H04N19/91
摘要： A method may be performed at a data storage device that includes a memory and a controller. The method includes providing user data to a variable-bit error correction coding (ECC) encoder. The ECC encoder generates a first set of parity bits. A first number of parity bits in the first set of parity bits is determined based on stored counts of read errors. The method also includes storing the user data and the first set of parity bits to a memory of the data storage device.
摘要翻译：可以在包括存储器和控制器的数据存储设备执行方法。该方法包括向可变比特纠错编码（ECC）编码器提供用户数据。 ECC编码器产生第一组奇偶校验位。第一组奇偶校验位中的奇偶校验位的第一数量是基于存储的读错误计数确定的。该方法还包括将用户数据和第一组奇偶校验位存储到数据存储设备的存储器。

3. 发明申请

WO2015171244A1 THREE DIMENSIONAL MEMORY DEVICE HAVING STACKED CONDUCTIVE CHANNELS 审中-公开
标题翻译：具有堆叠导电通道的三维存储器件
公开(公告)号：WO2015171244A1
公开(公告)日：2015-11-12
申请号：PCT/US2015/024940
申请日：2015-04-08
申请人： SANDISK TECHNOLOGIES INC.
发明人： D'ABREU, Manuel Antonio
IPC分类号： H01L27/115 , G11C11/56
CPC分类号： G11C16/0483 , G11C11/5671 , H01L21/02587 , H01L27/11551 , H01L27/1157 , H01L27/11578 , H01L27/11582
摘要： A method includes forming a first group of memory cells coupled to a first conductive channel. The first conductive channel is substantially perpendicular relative to a surface of a substrate. The method further includes forming a second group of memory cells coupled to a second conductive channel. The second conductive channel is electrically coupled to the first conductive channel and is substantially perpendicular relative to the surface of the substrate.
摘要翻译：一种方法包括形成耦合到第一导电沟道的第一组存储单元。第一导电通道相对于衬底的表面基本垂直。该方法还包括形成耦合到第二导电沟道的第二组存储器单元。第二导电通道电耦合到第一导电通道并且基本上相对于衬底的表面垂直。

4. 发明申请

WO2014092967A1 TRACKING READ ACCESSES TO REGIONS OF NON-VOLATILE MEMORY 审中-公开
标题翻译：跟踪非易失性存储区域的访问
公开(公告)号：WO2014092967A1
公开(公告)日：2014-06-19
申请号：PCT/US2013/071280
申请日：2013-11-21
申请人： SANDISK TECHNOLOGIES INC.
发明人： D'ABREU, Manuel Antonio , SKALA, Stephen
IPC分类号： G11C16/34
CPC分类号： G06F12/0246 , G11C16/3431 , G11C16/349
摘要： A data storage device includes a memory and a controller and may perform a method that includes updating, in the controller, a value of a particular counter of a set of counters in response to a read access to a particular region of the non-volatile memory that is tracked by the particular counter. Read accesses to a first region of the non-volatile memory are tracked by a first counter of the set of counters and read accesses to a second region of the non-volatile memory are tracked by a second counter of the set of counters. The method includes, in response to the value of the particular counter indicating that a count of read accesses to the particular region equals or exceeds a first threshold, initiating a remedial action to the particular region of the non-volatile memory.
摘要翻译：数据存储设备包括存储器和控制器，并且可以执行一种方法，该方法包括在控制器中响应于对非易失性存储器的特定区域的读访问来更新一组计数器的特定计数器的值由特定计数器跟踪。对非易失性存储器的第一区域的读取访问由该计数器集合的第一计数器跟踪，并且对该非易失性存储器的第二区域的读访问由该组计数器的第二计数器跟踪。该方法包括响应于特定计数器的值指示对特定区域的读取访问的计数等于或超过第一阈值，向非易失性存储器的特定区域发起补救动作。

5. 发明申请

WO2012109101A1 DATA RECOVERY USING ADDITIONAL ERROR CORRECTION CODING DATA 审中-公开
标题翻译：数据恢复使用附加错误修正编码数据
公开(公告)号：WO2012109101A1
公开(公告)日：2012-08-16
申请号：PCT/US2012/023735
申请日：2012-02-03
申请人： SANDISK TECHNOLOGIES INC. , D'ABREU, Manuel Antonio , SKALA, Stephen
发明人： D'ABREU, Manuel Antonio , SKALA, Stephen
IPC分类号： G06F11/10
CPC分类号： G06F11/10 , G06F11/1012
摘要： A method in a data storage device receiving data including a data block and main error correction coding (ECC) data for the data block. The data block includes a first sub-block of data and a second sub-block of data. The method also includes initiating an ECC operation to process the data block using the main ECC data. In response to the ECC operation indicating uncorrectable errors in the data block, first additional ECC data that is external to the data block is retrieved and a second ECC operation is initiated to process the first sub-block of data using the first additional ECC data.
摘要翻译：一种数据存储设备中的接收数据的方法，该数据包括用于数据块的数据块和主纠错编码（ECC）数据。数据块包括数据的第一子块和数据的第二子块。该方法还包括启动ECC操作以使用主ECC数据处理数据块。响应于指示数据块中的不可校正错误的ECC操作，检索在数据块外部的第一附加ECC数据，并且启动第二ECC操作以使用第一附加ECC数据来处理第一子数据块。

6. 发明申请

WO2016004317A1 ON-CHIP COPYING OF DATA BETWEEN NAND FLASH MEMORY AND RERAM OF A MEMORY DIE 审中-公开
标题翻译： NAND闪存存储器与存储器阵列之间的数据的片上复制
公开(公告)号：WO2016004317A1
公开(公告)日：2016-01-07
申请号：PCT/US2015/039000
申请日：2015-07-02
申请人： SANDISK TECHNOLOGIES INC.
发明人： HU, Xinde , GOROBETS, Sergey Anatolievich , D'ABREU, Manuel Antonio
IPC分类号： G11C7/10 , G11C8/16 , G11C11/00 , G11C13/00 , G06F12/08 , G11C16/10 , H01L27/115
CPC分类号： G11C13/0069 , G11C7/1006 , G11C7/1078 , G11C7/1087 , G11C8/16 , G11C11/005 , G11C13/0002 , G11C16/10 , G11C2213/71 , H01L27/115
摘要： A data storage device includes a memory die, where the memory die includes a NAND flash memory and a resistive random access memory (ReRAM). The memory die also includes an interface coupled to the ReRAM and the NAND flash memory. The interface is configured to support on-chip copying of data between the NAND flash memory and the ReRAM.
摘要翻译：数据存储装置包括存储器管芯，其中存储管芯包括NAND快闪存储器和电阻随机存取存储器（ReRAM）。存储器管芯还包括耦合到ReRAM和NAND闪存的接口。该接口被配置为支持NAND闪存和ReRAM之间的数据片上复制。

7. 发明申请

WO2015191245A1 THREE DIMENSIONAL (3D) DATA STORAGE DEVICE WITH ERROR DETECTION IN NON VOLATILE MEMORY AND ERROR CORRECTION IN MEMORY CONTROLLER 审中-公开
标题翻译：在非易失性存储器中具有错误检测的三维（3D）数据存储设备和存储器控制器中的错误校正
公开(公告)号：WO2015191245A1
公开(公告)日：2015-12-17
申请号：PCT/US2015/031340
申请日：2015-05-18
申请人： SANDISK TECHNOLOGIES INC.
发明人： D'ABREU, Manuel Antonio
IPC分类号： G06F11/10
CPC分类号： G06F11/076 , G06F11/0751 , G06F11/1048 , G06F11/1068
摘要： A method performed at a non-volatile memory of a data storage device includes determining, at error detection circuitry included in the non-volatile memory, an indication of a number of errors associated with a portion of the non-volatile memory. The method also includes providing the indication to a controller of the data storage device, where the controller includes error correction circuitry. The non-volatile memory has a 3D configuration that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate. The non-volatile memory includes circuitry associated with operation of the memory cells.
摘要翻译：在数据存储设备的非易失性存储器处执行的方法包括在非易失性存储器中包括的错误检测电路处确定与非易失性存储器的一部分相关联的错误数量的指示。该方法还包括向数据存储设备的控制器提供指示，其中控制器包括纠错电路。非易失性存储器具有在具有布置在硅衬底上方的有源区的存储器单元阵列的一个或多个物理层级中单体形成的3D配置。非易失性存储器包括与存储器单元的操作相关联的电路。

8. 发明申请

WO2015171314A1 ERROR CORRECTING CODE TECHNIQUES FOR A MEMORY HAVING A THREE-DIMENSIONAL MEMORY CONFIGURATION 审中-公开
标题翻译：具有三维存储器配置的存储器的错误校正代码技术
公开(公告)号：WO2015171314A1
公开(公告)日：2015-11-12
申请号：PCT/US2015/027075
申请日：2015-04-22
申请人： SANDISK TECHNOLOGIES INC.
发明人： D'ABREU, Manuel Antonio , HU, Xinde
IPC分类号： G06F11/10
CPC分类号： G06F11/1044 , G06F11/1048 , G06F11/1072 , G11C29/028 , G11C29/42 , G11C2029/0411
摘要： A data storage device includes a memory having a three-dimensional (3D) memory configuration. A method includes encoding first data to be stored at a first physical page. The first physical page is disposed within the memory at a first distance from a substrate of the memory, and the first data is encoded using a first encoding technique. The method further includes encoding second data to be stored at a second physical page. The second physical page is disposed within the memory at a second distance from the substrate that is greater than the first distance. The second data is encoded using a second encoding technique that is different than the first encoding technique.
摘要翻译：数据存储装置包括具有三维（3D）存储器配置的存储器。一种方法包括对要存储在第一物理页面上的第一数据进行编码。第一物理页面以与存储器的基板隔开的第一距离设置在存储器内，并且使用第一编码技术对第一数据进行编码。该方法还包括编码要存储在第二物理页面上的第二数据。第二物理页面被设置在距离基板的距离大于第一距离的第二距离的存储器内。使用与第一编码技术不同的第二编码技术对第二数据进行编码。

9. 发明申请

WO2013039696A1 DATA STORAGE DEVICE AND METHOD TO CORRECT BIT VALUES USING MULTIPLE READ VOLTAGES 审中-公开
标题翻译：数据存储设备和使用多个读取电压校正位值的方法
公开(公告)号：WO2013039696A1
公开(公告)日：2013-03-21
申请号：PCT/US2012/052889
申请日：2012-08-29
申请人： SANDISK TECHNOLOGIES INC. , D'ABREU, Manuel Antonio , SKALA, Stephen
发明人： D'ABREU, Manuel Antonio , SKALA, Stephen
IPC分类号： G06F11/10 , G11C16/34
CPC分类号： G06F11/1068 , G06F11/1048 , G11C29/52
摘要： A data storage device includes a memory including a plurality of storage elements. The memory is configured to read a group of the storage elements using a first read voltage to obtain a first plurality of bit values. A controller is coupled to the memory. The controller is configured to initiate a first error correction code (ECC) procedure on the first plurality of bit values. In response to the first ECC procedure determining that the first plurality of bit values is not correctable, the controller is further configured to instruct the memory to read the group of the storage elements using a second read voltage to obtain a second plurality of bit values, and to change one or more values of the first plurality of bit values to corresponding values of the second plurality of bit values to generate a first plurality of corrected bit values.
摘要翻译：数据存储装置包括具有多个存储元件的存储器。存储器被配置为使用第一读取电压读取一组存储元件以获得第一多个位值。控制器耦合到存储器。控制器被配置为针对第一多个位值启动第一纠错码（ECC）过程。响应于第一ECC程序确定第一多个比特值不可校正，控制器还被配置为指示存储器使用第二读取电压读取该组存储元件以获得第二多个比特值，并且将所述第一多个比特值中的一个或多个值改变为所述第二多个比特值的对应值，以生成第一多个校正比特值。

10. 发明申请

WO2012057995A1 HYBRID ERROR CORRECTION CODING TO ADDRESS UNCORRECTABLE ERRORS 审中-公开
标题翻译：混合错误校正编码来解决不正确的错误
公开(公告)号：WO2012057995A1
公开(公告)日：2012-05-03
申请号：PCT/US2011/055739
申请日：2011-10-11
申请人： SANDISK TECHNOLOGIES INC. , D'ABREU, Manuel Antonio , SKALA, Stephen
发明人： D'ABREU, Manuel Antonio , SKALA, Stephen
IPC分类号： G06F11/10
CPC分类号： G06F11/1012
摘要： A method in a memory device includes receiving data including a data block and main error correction coding (ECC) data for the data block. The data block includes a first sub-block of data and first ECC data corresponding to the first sub-block. An ECC operation is initiated to process the data block using the main ECC data. In response to the ECC operation indicating uncorrectable errors in the data, a first sub-block ECC operation is initiated to process the first sub-block of data using the first ECC data.
摘要翻译：存储装置中的方法包括接收数据块的数据块和主纠错编码（ECC）数据的数据。数据块包括数据的第一子块和对应于第一子块的第一ECC数据。启动ECC操作以使用主ECC数据来处理数据块。响应于指示数据中的不可校正错误的ECC操作，启动第一子块ECC操作以使用第一ECC数据处理第一子数据块。

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