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1. 发明申请

WO2016160274A1 EXTRACTING SELECTIVE INFORMATION FROM ON-DIE DRAM ECC 审中-公开
标题翻译：从芯片DRAM ECC提取选择信息
公开(公告)号：WO2016160274A1
公开(公告)日：2016-10-06
申请号：PCT/US2016/021142
申请日：2016-03-07
申请人： INTEL CORPORATION
发明人： DAS, Debaleena , NALE, Bill , BANES, Kuljit S , HALBERT, John B
IPC分类号： G06F11/10
CPC分类号： G06F11/1048 , G06F11/00 , G06F11/1008 , G06F11/1076 , G06F11/1084
摘要： Error correction in a memory subsystem includes a memory device generating internal check bits after performing internal error detection and correction, and providing the internal check bits to the memory controller. The memory device performs internal error detection to detect errors in read data in response to a read request from the memory controller. The memory device selectively performs internal error correction if an error is detected in the read data. The memory device generates check bits indicating an error vector for the read data after performing internal error detection and correction, and provides the check bits with the read data to the memory controller in response to the read request. The memory controller can apply the check bits for error correction external to the memory device.
摘要翻译：存储器子系统中的错误校正包括在执行内部错误检测和校正之后产生内部校验位的存储器件，以及向内存控制器提供内部校验位。存储器件执行内部错误检测以响应于来自存储器控制器的读取请求来检测读取数据中的错误。如果在读取的数据中检测到错误，则存储器件选择性地执行内部纠错。在执行内部错误检测和校正之后，存储器件产生指示读取数据的错误向量的校验位，并且响应于读取请求将校验位与读取的数据提供给存储器控制器。存储器控制器可以将校验位应用于存储器件外部的纠错。

2. 发明申请

WO2006028663A1 SIDE-BY-SIDE INVERTED MEMORY ADDRESS AND COMMAND BUSES 审中-公开
标题翻译：侧面反向存储器地址和命令总线
公开(公告)号：WO2006028663A1
公开(公告)日：2006-03-16
申请号：PCT/US2005/029020
申请日：2005-08-13
申请人： INTEL CORPORATION , DAVID, Howard , NALE, Bill
发明人： DAVID, Howard , NALE, Bill
IPC分类号： G06F13/40 , G06F13/16 , G06F13/42
CPC分类号： G06F13/4086 , G06F13/1684 , G06F13/4234 , Y02D10/14 , Y02D10/151
摘要： Generating a pair of buses, each coupled to a common terminating device, each having a set of address signal lines that are coupled to a separate memory device, and driving one set of address signal lines with an address driven with true logic states while driving the other set of address signal lines with the same address, but driven to opposing logic states, to achieve a greater balance between the quantity of signals across both buses that are driven to a high state versus those that are driven to a low state.
摘要翻译：产生一对总线，每对总线耦合到公共终端设备，每个总线具有一组地址信号线，其耦合到单独的存储器件，并且驱动一组地址信号线，其中驱动具有真实逻辑状态的地址，同时驱动具有相同地址的另一组地址信号线，但被驱动到相反的逻辑状态，以便在被驱动到高状态的两个总线与被驱动到低状态的总线之间的信号量之间实现更大的平衡。

3. 发明申请

WO2017192626A1 INTERNAL ERROR CHECKING AND CORRECTION (ECC) WITH EXTRA SYSTEM BITS 审中-公开
标题翻译：内部错误检查和纠正（ECC）与额外的系统位
公开(公告)号：WO2017192626A1
公开(公告)日：2017-11-09
申请号：PCT/US2017/030695
申请日：2017-05-02
申请人： INTEL CORPORATION
发明人： BAINS, Kuljit , NALE, Bill , AGARWAL, Rajat
IPC分类号： G11C29/42 , G06F11/10 , G11C11/409
摘要： A memory subsystem includes a data bus to couple a memory controller to one or more memory devices. The memory controller and one or more memory devices transfer data for memory access operations. The data transfer includes the transfer of data bits and associated check bits over a transfer cycle burst. The memory devices include internal error checking and correction (ECC) separate from the system ECC managed by the memory controller. With a 2N transfer cycle for 2^N data bits for a memory device, the memory devices can provide up to 2N memory locations for N+1 internal check bits, which can leave up to (2N minus (N+1)) extra bits to be used by the system for more robust ECC.
摘要翻译：存储器子系统包括数据总线以将存储器控制器耦合到一个或多个存储器设备。存储器控制器和一个或多个存储器设备传输用于存储器访问操作的数据。数据传输包括通过传输周期突发传输数据位和相关的校验位。存储器设备包括与由存储器控制器管理的系统ECC分开的内部错误检查和校正（ECC）。对于存储器件，2 ^ N个数据位的2N传输周期对于N + 1个内部校验位可以提供高达2N个存储器位置，这可以留下多达（2N减（N + 1））个额外位供系统使用，以获得更强大的ECC。

4. 发明申请

WO2016105852A1 SPECULATIVE READS IN BUFFERED MEMORY 审中-公开
标题翻译：缓冲存储器中的分析读数
公开(公告)号：WO2016105852A1
公开(公告)日：2016-06-30
申请号：PCT/US2015/062813
申请日：2015-11-26
申请人： INTEL CORPORATION
发明人： MORRIS, Brian, S. , NALE, Bill , BLANKENSHIP, Robert, G. , LIU, Yen-Cheng
IPC分类号： G06F13/16 , G06F12/08
CPC分类号： G06F12/0862 , G06F12/0835 , G06F12/0884 , G06F2212/1016 , G06F2212/507 , G06F2212/6026
摘要： A speculative read request is received from a host device over a buffered memory access link for data associated with a particular address. A read request is sent for the data to a memory device. The data is received from the memory device in response to the read request and the received data is sent to the host device as a response to a demand read request received subsequent to the speculative read request.
摘要翻译：通过用于与特定地址相关联的数据的缓冲存储器访问链路从主机设备接收推测读请求。发送读取请求以将数据发送到存储器设备。响应于读取请求从存储器装置接收数据，并且接收到的数据作为对在推测性读取请求之后接收的请求读取请求的响应被发送到主机设备。

5. 发明申请

WO2013048493A1 MEMORY CHANNEL THAT SUPPORTS NEAR MEMORY AND FAR MEMORY ACCESS 审中-公开
标题翻译：支持内存和内存访问的内存通道
公开(公告)号：WO2013048493A1
公开(公告)日：2013-04-04
申请号：PCT/US2011/054421
申请日：2011-09-30
申请人： INTEL CORPORATION , NALE, Bill , RAMANUJAN, Raj, K. , SWAMINATHAN, Muthukumar, P. , THOMAS, Tessil
发明人： NALE, Bill , RAMANUJAN, Raj, K. , SWAMINATHAN, Muthukumar, P. , THOMAS, Tessil
IPC分类号： G06F12/08 , G06F12/00 , G06F11/10 , G06F13/14 , G06F13/16
CPC分类号： G06F13/1694 , G06F9/467 , G06F11/1064 , G06F12/0238 , G06F12/0802 , G06F12/0804 , G06F12/0811 , G06F12/0868 , G06F12/0897 , G06F13/1668 , G06F13/4068 , G06F13/42 , G06F13/4234 , G06F2212/1008 , G06F2212/1016 , G06F2212/1044 , G06F2212/2024 , G06F2212/7203 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.
摘要翻译：一种包括存储器控制器电路的半导体芯片，其具有耦合到存储器通道的接口电路。存储器控制器包括在存储器通道上实现第一存储器通道协议的第一逻辑电路。第一存储器通道协议特定于第一易失性系统存储器技术。接口还包括在存储器通道上实现第二存储器通道协议的第二逻辑电路。第二存储器通道协议专用于第二非易失性系统存储器技术。第二个存储器通道协议是事务协议。

6. 发明申请

WO2017172287A2 READ DELIVERY FOR MEMORY SUBSYSTEM WITH NARROW BANDWIDTH REPEATER CHANNEL 审中-公开
标题翻译：使用窄带重复频道读取存储子系统的传送
公开(公告)号：WO2017172287A2
公开(公告)日：2017-10-05
申请号：PCT/US2017/021005
申请日：2017-03-06
申请人： INTEL CORPORATION
发明人： NALE, Bill , VOGT, Pete
IPC分类号： G06F13/40 , G06F13/16
CPC分类号： G06F13/16 , G06F3/061 , G06F3/0629 , G06F3/0631 , G06F3/0685 , G06F13/1678 , G06F13/4018 , G11C5/04 , G11C5/06 , G11C7/10
摘要： A system includes a repeater architecture for reads where memory connects to a host with one bandwidth, and repeats the channel with a lower bandwidth. A memory circuit includes a first group of read signal lines to couple point-to-point between a first group of memory devices and a host device. The memory circuit includes a second, smaller group of read signal lines to couple point-to-point between the first group and a second group of memory devices, to extend the memory channel to the second group. The memory circuit includes a repeater to share read bandwidth between the first and second groups of memory devices, with up to a portion of the bandwidth for reads to the second group of memory devices, and at least an amount equal to the bandwidth less the portion for reads to the first group of memory devices.
摘要翻译：系统包括用于读取的转发器架构，其中存储器使用一个带宽连接到主机，并以较低的带宽重复该通道。存储器电路包括第一组读取信号线，以在第一组存储器设备与主机设备之间点对点地耦合。存储器电路包括用于在第一组和第二组存储器件之间点对点地耦合的第二较小组读信号线，以将存储器通道扩展到第二组。存储器电路包括中继器，用于在第一和第二组存储器件之间共享读取带宽，其中至多一部分带宽用于读取第二组存储器件，并且至少等于带宽减去部分读取第一组内存设备。

7. 发明申请

WO2017172286A1 WRITE DELIVERY FOR MEMORY SUBSYSTEM WITH NARROW BANDWIDTH REPEATER CHANNEL 审中-公开
标题翻译：为带有窄带重复频道的记忆子系统写交货
公开(公告)号：WO2017172286A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/021004
申请日：2017-03-06
申请人： INTEL CORPORATION
发明人： NALE, Bill , VOGT, Pete
IPC分类号： G06F13/40 , G06F13/16
CPC分类号： H04W28/085 , H04B3/36 , H04W24/02
摘要： A system includes a repeater architecture for commands where memory connects to a host with one bandwidth, and repeats the channel with a lower bandwidth. A memory circuit includes a first group of command signal lines to couple point-to-point between a first group of memory devices and a host device. The memory circuit includes a second, smaller group of command signal lines to couple point-to-point between the first group and a second group of memory devices, to extend the memory channel to the second group. The memory circuit includes a repeater to share the command bandwidth between the first and second groups of memory devices, with up to a portion of the bandwidth for commands to the second group of memory devices, and at least an amount equal to the bandwidth less the portion for commands to the first group of memory devices.
摘要翻译：
系统包括一个中继器架构，用于存储器用一个带宽连接到主机的命令，并以较低的带宽重复该通道。存储器电路包括第一组命令信号线，以在第一组存储器装置与主机装置之间点对点地耦合。存储器电路包括第二较小组的命令信号线，以在第一组和第二组存储器设备之间点对点地耦合，以将存储器信道扩展到第二组。该存储器电路包括中继器，以共享第一和第二组存储器装置之间的命令带宽，其中多达一部分带宽用于命令到第二组存储器装置，并且至少等于带宽小于部分命令到第一组存储设备。

8. 发明申请

WO2017123327A1 TECHNIQUES TO ACCESS OR OPERATE A DUAL IN-LINE MEMORY MODULE VIA MULTIPLE DATA CHANNELS 审中-公开
标题翻译：通过多个数据通道访问或操作双列内存模块的技术
公开(公告)号：WO2017123327A1
公开(公告)日：2017-07-20
申请号：PCT/US2016/063106
申请日：2016-11-21
申请人： INTEL CORPORATION
发明人： COX, Christopher E. , BAINS, Kuljit S. , VERGIS, George , NALE, Bill , MCCALL, James A. , ZHAO, Chong J. , SAH, Suneeta , VOGT, Pete D. , GOLES, John R.
IPC分类号： G06F13/16
CPC分类号： G06F13/1673 , G06F13/4068 , G11C5/04 , G11C7/10 , G11C7/1045 , G11C11/4096 , G11C14/0009
摘要： Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.
摘要翻译：示例包括通过一个或多个数据通道访问或操作双列直插式内存模块（DIMM）的技术。在一些示例中，DIMM处或其上的存储器设备可以经由一个或多个数据通道来访问。所述一个或多个数据通道被布置成使得DIMM被配置为以包括两个数据通道的双通道模式操作或者以包括单个数据通道的单通道模式操作。

9. 发明申请

WO2016099813A1 ERROR HANDLING IN TRANSACTIONAL BUFFERED MEMORY 审中-公开
标题翻译：交易缓存中的错误处理
公开(公告)号：WO2016099813A1
公开(公告)日：2016-06-23
申请号：PCT/US2015/062071
申请日：2015-11-23
申请人： INTEL CORPORATION
发明人： MORRIS, Brian S. , NALE, Bill , BLANKENSHIP, Robert G. , HENDRICKSON, Eric L.
IPC分类号： G06F11/10 , G06F11/16 , G06F13/16 , G06F13/42 , G06F12/08
CPC分类号： G06F11/08 , G06F11/1625 , G06F11/1654 , G06F11/167 , G06F13/00 , H04L1/00 , H04L1/0061 , H04L1/0082 , H04L1/1838 , H04L2001/0097
摘要： Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.
摘要翻译：数据通过链路从内存缓冲设备发送到主机设备。确定数据中的错误。读取响应消除信号被发送到主机设备以向主机设备指示错误，其中在将数据从存储器缓冲设备发送到主机设备之后要发送读取响应消除信号。

10. 发明申请

WO2022256067A1 DOUBLE FETCH FOR LONG BURST LENGTH MEMORY DATA TRANSFER 审中-公开
公开(公告)号：WO2022256067A1
公开(公告)日：2022-12-08
申请号：PCT/US2022/020646
申请日：2022-03-16
申请人： INTEL CORPORATION
发明人： BAINS, Kuljit , NALE, Bill
IPC分类号： G06F3/06
摘要： For a memory device where a data fetch accesses N/2 data bits, and the memory device is to transfer N bits over a data burst of length M in response to a read command, the memory device accesses the same bank twice to access the N bits. Instead of accessing N/2 bits from two different banks, the memory device accesses a single bank twice. The memory device can control the timing of the data transfer to enable sending all N data bits to the memory controller for the read command. The memory device can send data as a first transfer of burst length M/2 of a first N/2 data bit portion and a second transfer of burst length M/2 of a second N/2 data bit portion.

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