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41. 发明申请

WO2008118824A2 SIGNALING CIRCUIT AND METHOD FOR INTEGRATED CIRCUIT DEVICES AND SYSTEMS 审中-公开
标题翻译：用于集成电路设备和系统的信号电路和方法
公开(公告)号：WO2008118824A2
公开(公告)日：2008-10-02
申请号：PCT/US2008/057943
申请日：2008-03-21
申请人： DSM SOLUTIONS, INC. , KAPOOR, Ashok, K.
发明人： KAPOOR, Ashok, K.
IPC分类号： G06F13/40 , H03K19/0175 , H01L21/331 , H01L21/8248 , H01L29/808
CPC分类号： H01L21/8248 , H01L27/0623 , H01L29/0692 , H01L29/0804 , H01L29/1004 , H01L29/66272 , H01L29/66901 , H01L29/732 , H01L29/808 , H03K5/2418 , H03K19/001 , H04L25/0264
摘要： Integrated circuit systems and semiconductor devices for generating, transmitting, receiving and manipulating clock and/or data signals. Semiconductor device including clock circuit having FETs and clock driver circuit having BJT. System and devices may include translator circuit translating signals with lower voltage swing into signals with higher voltage swing and circuit block operating at higher voltage swing. Wiring networks for communicating signals between individual circuits or system components. Integrated circuit device can include a BJT having first base electrode comprising semiconductor material doped to first conductivity type formed on and in contact with surface of semiconductor substrate and separated from emitter electrode by separation space. First base region can be formed in substrate below emitter electrode and include first portion of substrate doped to first conductivity type. Second base region can be formed in substrate below separation space and can include second portion of substrate doped to first conductivity type.
摘要翻译：用于生成，发送，接收和操纵时钟和/或数据信号的集成电路系统和半导体器件。包括具有FET的时钟电路和具有BJT的时钟驱动器电路的半导体器件。系统和设备可以包括转换器电路将具有较低电压摆幅的信号转换成具有较高电压摆幅的信号，并且在更高的电压摆幅下操作电路块。用于在各个电路或系统组件之间传送信号的接线网络。集成电路器件可以包括具有第一基极的BJT，该第一基极包括掺杂到第一导电类型的半导体材料，该半导体材料形成在半导体衬底的表面上并与半导体衬底的表面接触，并且通第一基区可以形成在发射极电极下方的衬底中，并且包括掺杂到第一导电类型的衬底的第一部分。第二基区可以形成在分离空间下方的衬底中，并且可以包括掺杂到第一导电类型的衬底的第二部分。

42. 发明申请

WO2007081528A2 ENVIRONMENTALLY ROBUST PASSIVATION STRUCTURES FOR HIGH-VOLTAGE SILICON CARBIDE SEMICONDUCTOR DEVICES 审中-公开
标题翻译：用于高电压碳化硅半导体器件的环境稳定的钝化结构
公开(公告)号：WO2007081528A2
公开(公告)日：2007-07-19
申请号：PCT/US2006048817
申请日：2006-12-21
申请人： CREE INC , WARD ALLAN , HENNING JASON PATRICK
发明人： WARD ALLAN , HENNING JASON PATRICK
IPC分类号： H01L29/24 , H01L21/04 , H01L21/314
CPC分类号： H01L21/3185 , H01L21/045 , H01L21/3145 , H01L21/318 , H01L29/1608 , H01L29/2003 , H01L29/24 , H01L29/405 , H01L29/6606 , H01L29/732 , H01L29/74 , H01L29/78 , H01L29/868 , H01L29/872
摘要： An improved termination structure for high field semiconductor devices in silicon carbide is disclosed. The termination structure includes a silicon carbide-based device for high-field operation, an active region in the device, an edge termination passivation for the active region, in which the edge termination passivation includes, an oxide layer on at least some of the silicon carbide portions of the device for satisfying surface states and lowering interface density, a non-stoichiometric layer of silicon nitride on the oxide layer for avoiding the incorporation of hydrogen and for reducing parasitic capacitance and minimizing trapping, and, a stoichiometric layer of silicon nitride on the nonstoichiometric layer for encapsulating the. nonstoichiometric layer and the oxide layer.
摘要翻译：公开了一种用于碳化硅中的高场半导体器件的改进的端接结构。端接结构包括用于高场操作的基于碳化硅的器件，器件中的有源区，用于有源区的边缘终止钝化，其中边缘终端钝化包括在至少一些硅上的氧化物层用于满足表面状态和降低界面密度的器件的碳化物部分，氧化物层上的非化学计量的氮化硅层，用于避免引入氢并减少寄生电容并最小化陷阱，以及化学计量的氮化硅层用于封装的非化学计量层。非化学计量层和氧化物层。

43. 发明申请

WO2006137401A1 ダイヤモンド半導体素子およびその製造方法审中-公开
标题翻译：金刚石半导体元件及其制造方法
公开(公告)号：WO2006137401A1
公开(公告)日：2006-12-28
申请号：PCT/JP2006/312334
申请日：2006-06-20
申请人：日本電信電話株式会社 , 嘉数誠 , 牧本俊樹 , 植田研二 , 山内喜晴
发明人：嘉数誠 , 牧本俊樹 , 植田研二 , 山内喜晴
IPC分类号： H01L21/338 , C23C16/27 , C30B29/04 , H01L21/331 , H01L29/73 , H01L29/812 , H01L33/00
CPC分类号： H01L21/324 , C23C16/274 , C23C16/278 , C30B25/105 , C30B29/04 , C30B33/02 , C30B33/06 , H01L21/02013 , H01L21/02027 , H01L21/02376 , H01L21/02433 , H01L21/02527 , H01L21/02579 , H01L21/02609 , H01L21/0262 , H01L21/0405 , H01L21/0415 , H01L29/045 , H01L29/1602 , H01L29/45 , H01L29/66037 , H01L29/66045 , H01L29/66742 , H01L29/66856 , H01L29/732 , H01L29/78 , H01L29/78684 , H01L29/812 , H01L33/0054 , H01L2924/0002 , H01L2924/00
摘要：　従来のダイヤモンド半導体素子においては、結晶欠陥密度が高く、ダイヤモンド特有の高熱伝道率、高絶縁破壊電界強度、高周波特性など物理特性を、トランジスタ特性に反映させることは出来なかった。ダイヤモンド基板の面方位を［００１］方向からわずかにずらすことにより、ダイヤモンド特有の結晶欠陥を大幅に減らすことが出来る。単結晶ダイヤモンド薄膜やチャンネルの面方位をわずかに［００１］方向からずらすことによっても、同等の効果が得られる。従来の面方位によって作成したトランジスタに比べて格段に高い相互コンダクタンスｇｍを得ることが出来る。
摘要翻译：在传统的半导体元件中，由于高晶体缺陷密度，金刚石的具体物理特性，即高导热率，高绝缘击穿场强和高频特性，不能反映在晶体管特性上。通过从[001]方向稍微移动金刚石衬底的平面取向，可以显着降低特定的金刚石晶体缺陷。也可以通过从[001]方向稍微移动单晶金刚石薄膜和沟道的平面取向来获得等效效果。可以获得与用常规平面取向制造的晶体管相比显着高的互导（gm）。

44. 发明申请

WO2006038305A1 半導体装置およびその製造方法审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2006038305A1
公开(公告)日：2006-04-13
申请号：PCT/JP2004/014894
申请日：2004-10-01
申请人：大見忠弘 , 森本明大
发明人：大見忠弘 , 森本明大
IPC分类号： H01L21/02
CPC分类号： H01L29/7813 , H01L21/84 , H01L27/12 , H01L29/045 , H01L29/41741 , H01L29/456 , H01L29/66734 , H01L29/732 , H01L29/7397 , H01L29/74 , H01L29/744 , H01L29/78603 , H01L2924/0002 , H05K1/053 , H01L2924/00
摘要：半導体装置用基板として、金属基板を用い、当該金属基板を第１の金属からなる金属基体と、該金属基体を覆う第２の金属からなる接続金属層とによって構成すると共に、接続金属層上に第１の金属の拡散を防止する拡散防止層を設けた構造を有する基板が得られる。
摘要翻译：作为半导体装置的基板，使用金属板，金属基板由金属基体和第二金属构成，金属基体由第一金属构成，金属层由用于覆盖金属基体的第二金属构成。该板具有其中在连接金属层上设置防止第一金属扩散的扩散防止层的结构。

45. 发明申请

WO2005072154A3 VERTICAL GATE CMOS WITH LITHOGRAPHY-INDEPENDENT GATE LENGTH 审中-公开
标题翻译：具有独立光栅长度的垂直栅极CMOS
公开(公告)号：WO2005072154A3
公开(公告)日：2005-12-08
申请号：PCT/US2005001313
申请日：2005-01-18
申请人： ATMEL CORP
发明人： LOJEK BOHUMIL
IPC分类号： H01L21/28 , H01L21/331 , H01L21/336 , H01L21/8238 , H01L29/423 , H01L29/732 , H01L29/78 , H01L29/786 , H01L27/10 , H01L29/73
CPC分类号： H01L29/78642 , H01L21/28123 , H01L21/823885 , H01L29/66287 , H01L29/66666 , H01L29/732 , H01L29/7827
摘要： Formation of elements of a vertical transistor is described, particularly, a gate (1905)- source (1901) - drain (1903) arrangement of a CMOS transistor. Vertical transistors are used frequently in the integrated circuit art. Accordingly, improved methods for their formation, which are not limited by constraints of photolithography, have great utility and importance. Those of skill in the art will appreciate that the techniques described may be used to fabricate other types of devices as well. For example, junctions of a bipolar transistor (as well as other device junction types) may be fabricated using the methods described herein.
摘要翻译：描述了垂直晶体管的元件的形成，特别是CMOS晶体管的栅极（1905） - 源极（1901） - 漏极（1903）布置。集成电路领域中常常使用垂直晶体管。因此，不受光刻限制的改进的形成方法具有很大的实用性和重要性。本领域技术人员将会理解，所描述的技术也可以用于制造其他类型的设备。例如，可以使用本文描述的方法来制造双极晶体管（以及其他器件结类型）的结。

46. 发明申请

WO2005024900A3 BIPOLAR TRANSISTOR HAVING RAISED EXTRINSIC BASE WITH SELECTABLE SELF-ALIGNMENT AND METHODS OF FORMING SAME 审中-公开
标题翻译：具有可选择的自对准的提升的超级基座的双极晶体管及其形成方法
公开(公告)号：WO2005024900A3
公开(公告)日：2005-06-09
申请号：PCT/US2004021345
申请日：2004-07-01
申请人： IBM , KHATER MARWAN H , DUNN JAMES S , HARAME DAVID L , JOSEPH ALVIN J , LIU QIZHI , PAGETTE FRANCOIS , ST ONGE STEPHEN A , STRICKER ANDREAS D
发明人： KHATER MARWAN H , DUNN JAMES S , HARAME DAVID L , JOSEPH ALVIN J , LIU QIZHI , PAGETTE FRANCOIS , ST ONGE STEPHEN A , STRICKER ANDREAS D
IPC分类号： H01L21/331 , H01L29/10 , H01L29/732 , H01L29/737 , H01L23/62
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter (106) is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer (102) of polysilicon or silicon on an intrinsic base (108). A dielectric landing pad (128) is then formed by lithography on the first extrinsic base layer (102). Next, a second extrinsic base layer (104) of polysilicon or silicon is formed on top of the dielectric landing pad (128) to finalize the raised extrinsic base total thickness. An emitter (106) opening is formed using lithography and RIE, where the second extrinsic base layer (104) is etched stopping on the dielectric landing pad (128). The degree of self-alignment between the emitter (106) and the raised extrinsic base is achieved by selecting the first extrinsic base layer (102) thickness, the dielectric landing pad (128) width, and the spacer width.
摘要翻译：公开了一种具有凸起的非本征基极和在本征基极和发射极（106）之间的可选自对准的双极晶体管。制造方法可以包括在内在基极（108）上形成多晶硅或硅的第一非本征基极层（102）的预定厚度。然后通过光刻在第一非本征基极层（102）上形成电介质着色焊盘（128）。接下来，在电介质着色焊盘（128）的顶部上形成多晶硅或硅的第二非本征基极层（104），以最终确定凸出的非本征基本总厚度。使用光刻和RIE形成发射器（106）开口，其中第二外部基极层（104）被蚀刻停止在电介质着色焊盘（128）上。通过选择第一非本征基极层（102）的厚度，电介质着陆焊盘（128）的宽度和间隔物宽度来实现发射极（106）和凸起的外在基极之间的自对准程度。

47. 发明申请

WO2005004201A3 BIPOLAR TRANSISTOR AND METHOD OF MAKING SAME 审中-公开
标题翻译：双极晶体管及其制造方法
公开(公告)号：WO2005004201A3
公开(公告)日：2005-05-12
申请号：PCT/US2004019906
申请日：2004-06-22
申请人： IBM , JOSEPH ALVIN J , LIU QIZHI
发明人： JOSEPH ALVIN J , LIU QIZHI
IPC分类号： H01L21/331 , H01L21/8249 , H01L27/06 , H01L29/10 , H01L29/732 , H01L21/8222 , H01L27/082
CPC分类号： H01L29/66287 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L29/732
摘要： A high fT and fmax bipolar transistor (100) includes an emitter (104), a base (120), and a collector (116). The emitter has a lower portion (108) and an upper portion (1.12) that extends beyond the lower portion. The base includes an intrinsic base (140) and an extrinsic base (144). The intrinsic base is located between the lower portion of the emitter and the collector. The extrinsic base extends from the lower portion of the emitter beyond the upper portion of the emitter and includes a continuous conductor (148) that extends from underneath the upper portion of the emitter and out from underneath the upper portion of the emitter. The continuous conductor provides a low electrical resistance path from a base contact (not shown) to the intrinsic base. The transistor may include a second conductor (152) that does not extend underneath the upper portion of the emitter, but which further reduces the electrical resistance through the extrinsic base.
摘要翻译：高fT和fmax双极晶体管（100）包括发射极（104），基极（120）和集电极（116）。发射器具有延伸超出下部的下部（108）和上部（1.12）。基底包括本征基（140）和外基（144）。本征基极位于发射极的下部和集电极之间。外部基极从发射器的下部延伸超过发射器的上部，并且包括从发射器的上部下方延伸并从发射器的上部下方延伸的连续导体（148）。连续导体提供从底部触点（未示出）到本征基极的低电阻路径。晶体管可以包括第二导体（152），其不延伸在发射极的上部下方，但是通过外部基极进一步减小电阻。

48. 发明申请

WO2003073468A2 SILICON CARBIDE BIPOLAR JUNCTION TRANSISTOR WITH OVERGROWN BASE REGION 审中-公开
标题翻译：具有超过基底区域的碳化硅双极晶体管晶体管
公开(公告)号：WO2003073468A2
公开(公告)日：2003-09-04
申请号：PCT/US2003/004873
申请日：2003-02-21
申请人： SEMISOUTH LABORATORIES, INC.
发明人： SANKIN, Igor , DUFRENE, Janna, B.
IPC分类号： H01L
CPC分类号： H01L29/66068 , H01L29/0619 , H01L29/0661 , H01L29/1004 , H01L29/1608 , H01L29/732
摘要： Silicon carbide bipolar junction transistors having an overgrown base layer are provided. The bipolar junction transistors can be made with a very thin (e.g., 0.3 µm or less) base layer while still possessing adequate peripheral base resistance values. Self aligning manufacturing techniques for making the silicon carbide bipolar junction transistors are also provided. Using these techniques, the spacing between emitter and base contacts on the device can be reduced. The silicon carbide bipolar junction transistors can also be provided with edge termination structures such as guard rings to increase the blocking capabilities of the device.
摘要翻译：提供具有过度生长的基底层的碳化硅双极结型晶体管。双极结晶体管可以由非常薄（例如，0.3微米或更小）的基底层制成，同时仍具有足够的周边基极电阻值。还提供了用于制造碳化硅双极结型晶体管的自对准制造技术。使用这些技术，可以减少器件上的发射极和基极触点之间的间距。碳化硅双极结晶体管还可以设置有边缘终端结构，例如保护环，以增加器件的阻塞能力。

49. 发明申请

WO02031884A1 NONPLANAR SEMICONDUCTOR DEVICES HAVING CLOSED REGION OF SPATIAL CHARGE 审中-公开
标题翻译：具有封闭空间充电区域的非波导半导体器件
公开(公告)号：WO02031884A1
公开(公告)日：2002-04-18
申请号：PCT/RU2001/000409
申请日：2001-10-11
IPC分类号： H01L29/732 , H01L29/74 , H01L29/864 , H01L47/02 , H01L29/72
CPC分类号： H01L47/026 , H01L29/732 , H01L29/74 , H01L29/864
摘要： The invention relates to the electronic technology, in particular to design and a production of nonplanar semiconductor devices having a closed region of a spatial charge and can be used in the electronic industry for circuits amplifying, generating and transforming electromagnetic oscillations into other type of oscillations. Said invention makes it possible to produce the semiconductor devices having the higher reliability at nominal values of operating currents and voltages, exclude the edge effect and reduce the level of the electrothermal and thermo-electromagnetic degradation. The formation of the closed region of the spatial charge is demonstrated with the aid of the following nonplanar semiconductor devices: a bipolar transistors, a thyristor, an avalanche diode, a Gunn diode and variants thereof.
摘要翻译：本发明涉及电子技术，特别涉及设计和制造具有空间电荷闭合区域的非平面半导体器件，并可用于电子工业中用于放大，产生和转换电磁振荡到其它类型的振荡中的电路。所述发明使得可以在工作电流和电压的额定值下制造具有较高可靠性的半导体器件，排除边缘效应并降低电热和热电磁降解的水平。借助于以下非平面半导体器件来证明空间电荷的闭合区域的形成：双极晶体管，晶闸管，雪崩二极管，耿氏二极管及其变体。

50. 发明申请

WO02011212A1 W/WC/TAC OHMIC AND RECTIFYING CONTACTS ON SIC 审中-公开
标题翻译： W / WC / TAC OHMIC和SIC上的修复联系人
公开(公告)号：WO02011212A1
公开(公告)日：2002-02-07
申请号：PCT/US2001/041400
申请日：2001-07-24
IPC分类号： H01L21/04 , H01L23/49 , H01L29/24 , H01L29/45 , H01L29/47 , H01L29/872 , H01L31/0256 , H01L31/0312
CPC分类号： H01L21/0485 , H01L21/046 , H01L21/049 , H01L21/0495 , H01L24/01 , H01L29/1608 , H01L29/45 , H01L29/47 , H01L29/6606 , H01L29/66068 , H01L29/6609 , H01L29/66128 , H01L29/732 , H01L29/7395 , H01L29/812 , H01L29/8128 , H01L29/861 , H01L29/872 , H01L2224/4918 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01043 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0107 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/10329 , H01L2924/12032 , H01L2924/12036 , H01L2924/1301 , H01L2924/13034 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13063 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/3025 , H01L2924/00
摘要： Ohmic and rectifying contacts to a TaC layer (112) on an n-type or p-type area (122) of an SiC substrate (110) are formed by despositing a WC layer (114) over the TaC layer, following by a metallic W layer (116). Such contacts are stable to at least 1150 DEG C. Electrodes (120) connect to the contacts either directly or via a protective bonding layer such as Pt or PtAu alloy throught a dielectric layer (118).
摘要翻译：在SiC衬底（110）的n型或p型区域（122）上的TaC层（112）的欧姆和整流接触是通过在TaC层上去除WC层（114）而形成的，随后是金属 W层（116）。这种接触对至少1150℃是稳定的。电极（120）直接或通过诸如Pt或PtAu合金的保护性结合层通过介电层（118）连接到触点。

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