专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2019089916A1 INTEGRATED PROCESS FLOW FOR SEMICONDUCTOR DEVICES 审中-公开
公开(公告)号：WO2019089916A1
公开(公告)日：2019-05-09
申请号：PCT/US2018/058696
申请日：2018-11-01
申请人： THE CHARLES STARK DRAPER LABORATORY, INC.
发明人： CHESIN, Jordan , CHERN, Winston , MORRISON, Richard, H. , MUZA, John, M.
IPC分类号： H01L21/84 , H01L27/12 , H01L29/735 , H01L29/66 , H01L49/02 , H01L27/06 , H01L21/8249 , H01L27/085
CPC分类号： H01L21/84 , H01L21/0228 , H01L21/3212 , H01L21/823821 , H01L21/8249 , H01L21/845 , H01L27/04 , H01L27/0623 , H01L27/0629 , H01L27/0635 , H01L27/085 , H01L27/0924 , H01L27/1203 , H01L27/1211 , H01L28/60 , H01L29/0692 , H01L29/0808 , H01L29/0821 , H01L29/41708 , H01L29/6625 , H01L29/66901 , H01L29/7317 , H01L29/735 , H01L29/7855 , H01L29/8086
摘要： A method of fabricating a semiconductor device comprises forming, within a single process flow on a silicon on insulator (SOI) wafer, at least one of an n channel, digital VeSFET, a p channel, digital VeSFET, an n channel, analog VeSFET and a p channel, analog VeSFET. The method may further comprise forming, on the SOI wafer, at least one of a JFET, a BJT and a LT-MOM capacitor. The method may further comprise forming the n channel, digital VeSFET, a p channel, digital VeSFET, an n channel, analog VeSFET, and a p channel, analog VeSFET, according to a periodic design based on a unit circle. The method may comprise modifying a design of the semiconductor node, according to a three-dimensional architecture, to form a modified semiconductor node, and fabricating the modified semiconductor node on substrate, along with at least one other node of a different node type.

2. 发明申请

WO2015048304A2 LOW NOISE InGaAs PHOTODIODE ARRAY 审中-公开
标题翻译：低噪声InGaAs光电图阵列
公开(公告)号：WO2015048304A2
公开(公告)日：2015-04-02
申请号：PCT/US2014/057481
申请日：2014-09-25
申请人： PRINCETON INFRARED TECHNOLOGIES, INC.
发明人： ETTENBERG, Martin, H.
IPC分类号： G01N21/359
CPC分类号： H01L27/14679 , H01L27/14609 , H01L27/1461 , H01L27/1465 , H01L27/14652 , H01L27/14694 , H01L29/66901 , H01L29/808 , H01L31/03046 , H01L31/105 , H01L31/1844
摘要： A photodiode pixel structure for imaging short wave infrared (SWIR) and visible light built in a planar structure and may be used for one dimensional and two dimensional photodiode arrays. The photodiode arrays may be hybridized to a read out integrated circuit (ROIC), for example, a silicon complementary metal-oxide-semiconductor (CMOS) circuit. The photodiode in each pixel is buried under the surface and does not directly contact the ROIC amplification circuit. Charge is transferred form the detector using a junction field effect transistor (JFET) in each pixel. Disconnecting the photodiode from the ROIC amplification circuit enables low dark current as well as double correlated sampling in the pixel.
摘要翻译：用于成像短波红外（SWIR）和可见光的光电二极管像素结构，其构建在平面结构中，并且可用于一维和二维光电二极管阵列。光电二极管阵列可以与读出集成电路（ROIC）杂交，例如，硅互补金属氧化物半导体（CMOS）电路。每个像素中的光电二极管埋在表面下，不直接接触ROIC放大电路。在每个像素中使用结场效应晶体管（JFET）从检测器传送电荷。将光电二极管与ROIC放大电路断开，可以实现低暗电流以及像素双重相关采样。

3. 发明申请

WO2014027518A1 炭化珪素半導体装置およびその製造方法审中-公开
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：WO2014027518A1
公开(公告)日：2014-02-20
申请号：PCT/JP2013/068094
申请日：2013-07-02
申请人：住友電気工業株式会社
发明人：玉祖　秀人
IPC分类号： H01L21/28 , H01L21/336 , H01L21/337 , H01L27/098 , H01L29/12 , H01L29/417 , H01L29/78 , H01L29/808
CPC分类号： H01L29/1608 , H01L21/046 , H01L21/049 , H01L21/283 , H01L23/53219 , H01L29/66068 , H01L29/66901 , H01L29/7827 , H01L29/808 , H01L2924/0002 , H01L2924/00
摘要：　炭化珪素半導体装置（１）の製造方法は以下の工程を有している。炭化珪素基板（１０）が準備される。炭化珪素基板（１０）上に二酸化珪素膜（１５）が形成される。炭化珪素基板（１０）および二酸化珪素膜（１５）に接するようにＡｌおよびＴｉを含む電極（１６）が形成される。電極（１６）を形成する工程は、炭化珪素基板（１０）上にＡｌおよびＴｉを含む金属膜（５０）を形成する工程と、酸素ガスが導入される雰囲気中において金属膜（５０）を５００℃以上に加熱する工程とを含む。これにより、絶縁膜の絶縁信頼性を向上させることができる炭化珪素半導体装置（１）の製造方法を提供することができる。
摘要翻译：该制造碳化硅半导体器件（1）的方法具有以下步骤：制备碳化硅衬底（10）; 在所述碳化硅衬底（10）的顶部上形成二氧化硅膜（15）; 并且形成含有铝和钛的电极（16），以与碳化硅衬底（10）和二氧化硅膜（15）接触。形成电极（16）的步骤包括在碳化硅衬底（10）的顶部上形成含有铝和钛的金属膜（50）的步骤，其中所述金属膜（50）在引入氧气的气氛中加热至少500℃。这使得可以提供一种可以提高绝缘膜的绝缘可靠性的碳化硅半导体器件（1）制造方法。

4. 发明申请

WO2012075272A3 STRUCTURES AND METHODS FOR ELECTRICALLY AND MECHANICALLY LINKED MONOLITHICALLY INTEGRATED TRANSISTOR AND MEMS/NEMS DEVICES 审中-公开
标题翻译：电力和机械连接的单相集成晶体管和MEMS / NEMS器件的结构和方法
公开(公告)号：WO2012075272A3
公开(公告)日：2012-08-16
申请号：PCT/US2011062871
申请日：2011-12-01
申请人： UNIV CORNELL , LAL AMIT , AMPONSAH KWAME
发明人： LAL AMIT , AMPONSAH KWAME
IPC分类号： H01L25/16 , B81B7/02
CPC分类号： H01L25/16 , B81C1/00246 , B81C2203/075 , H01L29/42316 , H01L29/66893 , H01L29/66901 , H01L29/735 , H01L29/8086 , H01L29/8126 , H01L2924/0002 , H01L2924/00
摘要： A device including a NEMS/MEMS machine(s) and associated electrical circuitry. The circuitry includes at least one transistor, preferably JFET, that is used to: (i) actuate the NEMS/MEMS machine; and/or (ii) receive feedback from the operation of the NEMS/MEMS machine The transistor (e.g., the JFET) and the NEMS/MEMS machine are monolithically integrated for enhanced signal transduction and signal processing. Monolithic integration is preferred to hybrid integration (e.g., integration using wire bonds, flip chip contact bonds or the like) due to reduce parasitics and mismatches. In one embodiment, the JFET is integrated directly into a MEMS machine, that is in the form of a SOI MEMS cantilever, to form an extra-tight integration between sensing and electronic integration. When a cantilever connected to the JFET is electrostatically actuated; its motion directly affects the current in the JFET through monolithically integrated conduction paths (e.g., traces, vias, etc.) In one embodiment, devices according to the present invention were realized in 2?m thick SOI cross-wire beams, with a MoSi2 contact metallization for stress minimization and ohmic contact. In this embodiment, the pull-in voltage for the MEMS cantilever was 21V and the pinch-off voltage of the JFET was -19V.
摘要翻译：包括NEMS / MEMS机器和相关联的电路的装置。该电路包括至少一个晶体管，优选JFET，其用于：（i）致动NEMS / MEMS机器; 和/或（ii）从NEMS / MEMS机器的操作接收反馈晶体管（例如，JFET）和NEMS / MEMS机器是单片集成的，用于增强的信号传导和信号处理。由于减少寄生和失配，整体集成优于混合集成（例如，使用引线键合，倒装芯片接触键等的集成）。在一个实施例中，JFET直接集成在MEMS机器中，其是以SOI MEMS悬臂的形式，以形成感测和电子集成之间的非常紧密的集成。当连接到JFET的悬臂被静电驱动时; 其运动通过单片集成导电路径（例如，迹线，通孔等）直接影响JFET中的电流。在一个实施例中，根据本发明的器件在2μm厚的SOI交叉线束中实现，其中MoSi 2 接触金属化用于应力最小化和欧姆接触。在本实施例中，MEMS悬臂的拉入电压为21V，JFET的截止电压为-19V。

5. 发明申请

WO2012075272A2 STRUCTURES AND METHODS FOR ELECTRICALLY AND MECHANICALLY LINKED MONOLITHICALLY INTEGRATED TRANSISTOR AND MEMS/NEMS DEVICES 审中-公开
标题翻译：用于电和机械连接的单晶体集成晶体管和MEMS / NEMS器件的结构和方法
公开(公告)号：WO2012075272A2
公开(公告)日：2012-06-07
申请号：PCT/US2011/062871
申请日：2011-12-01
申请人： CORNELL UNIVERSITY , LAL, Amit , AMPONSAH, Kwame
发明人： LAL, Amit , AMPONSAH, Kwame
IPC分类号： H01L25/16 , B81B7/02
CPC分类号： H01L25/16 , B81C1/00246 , B81C2203/075 , H01L29/42316 , H01L29/66893 , H01L29/66901 , H01L29/735 , H01L29/8086 , H01L29/8126 , H01L2924/0002 , H01L2924/00
摘要： A device including a NEMS/MEMS machine(s) and associated electrical circuitry. The circuitry includes at least one transistor, preferably JFET, that is used to: (i) actuate the NEMS/MEMS machine; and/or (ii) receive feedback from the operation of the NEMS/MEMS machine The transistor (e.g., the JFET) and the NEMS/MEMS machine are monolithically integrated for enhanced signal transduction and signal processing. Monolithic integration is preferred to hybrid integration (e.g., integration using wire bonds, flip chip contact bonds or the like) due to reduce parasitics and mismatches. In one embodiment, the JFET is integrated directly into a MEMS machine, that is in the form of a SOI MEMS cantilever, to form an extra-tight integration between sensing and electronic integration. When a cantilever connected to the JFET is electrostatically actuated; its motion directly affects the current in the JFET through monolithically integrated conduction paths (e.g., traces, vias, etc.) In one embodiment, devices according to the present invention were realized in 2?m thick SOI cross-wire beams, with a MoSi2 contact metallization for stress minimization and ohmic contact. In this embodiment, the pull-in voltage for the MEMS cantilever was 21V and the pinch-off voltage of the JFET was -19V.
摘要翻译：包括NEMS / MEMS机器和相关电路的设备。该电路包括至少一个晶体管，优选JFET，其用于：（i）致动NEMS / MEMS机器; 和/或（ii）从NEMS / MEMS机器的操作接收反馈。晶体管（例如，JFET）和NEMS / MEMS机器单片集成以增强信号转换和信号处理。由于减少了寄生和失配，单片集成优于混合集成（例如，使用引线键合，倒装芯片接触键等的集成）。在一个实施例中，JFET直接集成到MEMS机器中，即以SOI MEMS悬臂的形式，以在感测和电子集成之间形成非常紧密的集成。当连接到JFET的悬臂被静电致动时; 其运动通过单片集成传导路径（例如，迹线，过孔等）直接影响JFET中的电流。在一个实施例中，根据本发明的器件在2μm厚的SOI交叉线束中实现，其中MoSi2 用于应力最小化和欧姆接触的接触金属化。在此实施例中，MEMS悬臂的拉入电压为21V，JFET的夹断电压为-19V。

6. 发明申请

WO2011053464A1 JUNCTION FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：连接场效应晶体管
公开(公告)号：WO2011053464A1
公开(公告)日：2011-05-05
申请号：PCT/US2010/052700
申请日：2010-10-14
申请人： ANALOG DEVICES, INC.
发明人： DALY, Paul, Malachy , BAIN, Andrew, David , BOWERS, Derek, Frederick , DEIGNAN, Anne, Maria , DUNBAR, Michael, Thomas , MCGUINNESS, Patrick, Martin , STENSON, Bernard, Patrick , LANE, William, Allan
IPC分类号： H01L21/337 , H01L29/08 , H01L29/808
CPC分类号： H01L29/808 , H01L29/0843 , H01L29/66901
摘要： A junction field effect transistor having a drain and a source, each defined by regions of a first type of semiconductor interconnected by a channel, is disclosed. In the transistor, a dopant profile at a side of the drain facing the channel is modified so as to provide a region (330) of reduced doping compared to a body region (335) of the drain. The region (330) of reduced doping and the body region (335) can be defined by the same mask (300) and doping step, but the mask (300) is shaped to provide a lesser amount and thus less depth of doping for the region (330) of reduced doping.
摘要翻译：公开了一种具有漏极和源极的结型场效应晶体管，每个源极由通过沟道互连的第一类型半导体的区域限定。在晶体管中，面向沟道的漏极一侧的掺杂剂分布被修改，从而与漏极的体区（335）相比提供了减少掺杂的区域（330）。减少掺杂的区域（330）和体区（335）可以由相同的掩模（300）和掺杂步骤限定，但是掩模（300）被成形为提供较小的量，因此较少的掺杂深度用于减少掺杂的区域（330）。

7. 发明申请

WO2008128007A3 LOW NOISE JFET 审中-公开
标题翻译：低噪声JFET
公开(公告)号：WO2008128007A3
公开(公告)日：2009-02-26
申请号：PCT/US2008059973
申请日：2008-04-11
申请人： TEXAS INSTRUMENTS INC , HAO PINGHAI , KHAN IMRAN , TROGOLO JOE
发明人： HAO PINGHAI , KHAN IMRAN , TROGOLO JOE
IPC分类号： H01L29/80 , H01L29/78
CPC分类号： H01L29/8086 , H01L29/66901 , H01L29/808
摘要： A low noise (1/f) junction field effect transistor (JFET) and method are disclosed. A buried layer of first conductivity type is formed in a substrate (102). An epitaxial layer of second conductivity type is formed over the substrate (103). First well regions of first conductivity type are formed in the epitaxial layer down to the bottom gate (106); and a second well region of second conductivity type is formed between the first well regions (108). Isolation regions are formed in the surface of the epitaxial layer (110). A first Vt region of first conductivity type is formed in the second well region between first and second isolation regions (112); and a second Vt region of second conductivity type is formed in the first Vt region (114), the first Vt region being deeper than the second Vt region. A source region and a drain region of first conductivity type are formed in the first Vt region (118).
摘要翻译：公开了低噪声（1 / f）结场效应晶体管（JFET）和方法。在衬底（102）中形成第一导电类型的掩埋层。在衬底（103）上形成第二导电类型的外延层。第一导电类型的第一阱区在外延层中形成到底栅（106）下方; 并且在第一阱区（108）之间形成第二导电类型的第二阱区。在外延层（110）的表面形成隔离区域。在第一和第二隔离区域（112）之间的第二阱区域中形成第一导电类型的第一Vt区域; 并且在第一Vt区域（114）中形成第二导电类型的第二Vt区域，第一Vt区域比第二Vt区域更深。在第一Vt区域（118）中形成第一导电类型的源极区域和漏极区域。

8. 发明申请

WO2008137627A1 SEMICONDUCTOR DEVICE HAVING A FIN STRUCTURE AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：具有精细结构和制造方法的半导体器件
公开(公告)号：WO2008137627A1
公开(公告)日：2008-11-13
申请号：PCT/US2008/062338
申请日：2008-05-02
申请人： DSM SOLUTIONS, INC. , KAPOOR, Ashok, K.
发明人： KAPOOR, Ashok, K.
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L29/8086 , H01L29/66901 , H01L29/785
摘要： A semiconductor device includes a silicon on insulator (SOI) substrate, comprising an insulation layer formed on semiconductor material, and a fin structure. The fin structure is formed of semiconductor material and extends from the SOI substrate. Additionally, the fin structure includes a source region, a drain region, a channel region, and a gate region. The source region, drain region, and the channel region are doped with a first type of impurities, and the gate region is doped with a second type of impurities. The gate region abuts the channel region along at least one boundary, and the channel region is operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state.
摘要翻译：半导体器件包括绝缘体上硅（SOI）衬底，其包括形成在半导体材料上的绝缘层和鳍结构。翅片结构由半导体材料形成并从SOI衬底延伸。另外，鳍结构包括源极区，漏极区，沟道区和栅极区。源极区域，漏极区域和沟道区域掺杂有第一类型的杂质，并且栅极区域掺杂有第二类型的杂质。栅极区域沿着至少一个边界邻接沟道区域，并且当半导体器件工作在导通状态时，沟道区域可操作地在漏极区域和源极区域之间传导电流。

9. 发明申请

WO2008137483A1 DOUBLE GATE JFET AND FABRICATION METHOD THEREFOR 审中-公开
标题翻译：双栅极晶体管及其制造方法
公开(公告)号：WO2008137483A1
公开(公告)日：2008-11-13
申请号：PCT/US2008/062104
申请日：2008-04-30
申请人： DSM SOLUTIONS, INC. , BANNA, Srinivasa R.
发明人： BANNA, Srinivasa R.
IPC分类号： H01L29/808 , H01L21/337 , H01L29/10 , H01L29/423 , H01L29/45 , H01L29/08
CPC分类号： H01L29/808 , H01L27/098 , H01L29/0843 , H01L29/42316 , H01L29/456 , H01L29/66901
摘要： Double gate JFET with reduced area consumption and fabrication method therefor. Double-gate semiconductor device including a substrate (206) having a shallow trench isolator region (212) comprising a first STI and a second STI, a channel region (202) having a first and second channel edges (250, 252), the channel region formed in the substrate and disposed between and in contact with the first STI and the second STI at the first and second channel edge. The first STI has a first cavity (216) at the first channel edge, and the second STI has a second cavity (218) at the second channel edge. The device further includes a gate electrode region (214) comprising conductive material filling at least one of the first and second cavities. At least one of the first and second cavities is physically configured to provide electrical coupling of the gate electrode region to a back-gate P-N junction.
摘要翻译：双栅JFET，减少面积消耗及其制造方法。包括具有包括第一STI和第二STI的浅沟槽隔离器区域（212）的衬底（206）的双栅极半导体器件，具有第一和第二沟道边缘（250,252）的沟道区域（202），所述沟道形成在衬底中并且设置在第一和第二沟道边缘处的第一STI和第二STI之间并与之接触的区域。第一STI在第一通道边缘处具有第一腔（216），并且第二STI在第二通道边缘处具有第二腔（218）。该器件还包括栅极电极区域（214），其包括填充第一和第二腔中的至少一个的导电材料。第一和第二腔中的至少一个物理地构造成提供栅极电极区域与背栅极P-N结的电耦合。

10. 发明申请

WO2008055095A3 JUNCTION ISOLATED POLY-SILICON GATE JFET 审中-公开
标题翻译：结隔离式多晶硅栅极结型场效应管
公开(公告)号：WO2008055095A3
公开(公告)日：2008-09-12
申请号：PCT/US2007082815
申请日：2007-10-29
申请人： DSM SOLUTIONS INC , VORA MADHUKAR B
发明人： VORA MADHUKAR B
IPC分类号： H01L21/337 , H01L21/761 , H01L27/098 , H01L29/808
CPC分类号： H01L29/808 , H01L27/098 , H01L29/66901
摘要： An integrated Junction Field Effect Transistor is disclosed which is much smaller and much less expensive to fabricate because it does not use Shallow Trench Isolation or field oxide in the semiconductor substrate to isolate separate transistors. Instead, a layer of insulating material is formed on the top surface of said substrate, and interconnect trenches are etched in said insulating layer which do not go all the way down to the semiconductor substrate. Contact openings are etched in the insulating layer all the way down to the semiconductor layer. Doped poly-silicon is formed in the contact openings and interconnect trenches and silicide is formed on tops of the poly-silicon. This contact and interconnect structure applies to any integrated transistor. The integrated JFET disclosed herein does not use STI or field oxide and uses junction isolation. A conventional JFET is built in a P- well. The P- well is encapsulated in an N-well which is implanted into the substrate. Separate contacts to the P-well, N-well and substrate are formed as well as to the source, drain and gate so that the device can be isolated by reverse-biasing a PN junction. Operating voltage is restricted to less than 0.7 volts to prevent latching.
摘要翻译：公开了一种集成的结型场效应晶体管，其制造起来小得多并且便宜得多，因为它不在半导体衬底中使用浅沟槽隔离或场氧化物来隔离单独的晶体管。取而代之的是，在所述衬底的顶表面上形成绝缘材料层，并且在所述绝缘层中蚀刻互连沟槽，所述绝缘层不一直向下到半导体衬底。接触开口在绝缘层中一直蚀刻到半导体层。在接触开口和互连沟槽中形成掺杂的多晶硅，并且在多晶硅的顶部形成硅化物。这种接触和互连结构适用于任何集成晶体管。这里公开的集成JFET不使用STI或场氧化物并使用结隔离。传统的JFET是建在一个P-井。将P阱封装在注入衬底中的N阱中。形成与P阱，N阱和衬底分开的触点以及源极，漏极和栅极，从而可以通过反向偏置PN结来隔离器件。工作电压限制在0.7伏以下，以防止锁定。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式