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1. 发明申请

WO2008137294A1 JFET DEVICE WITH VIRTUAL SOURCE AND DRAIN LINK REGIONS AND METHOD OF FABRICATION 审中-公开
标题翻译：具有虚拟源和漏极链接区域的JFET器件和制造方法
公开(公告)号：WO2008137294A1
公开(公告)日：2008-11-13
申请号：PCT/US2008/060987
申请日：2008-04-21
申请人： DSM SOLUTIONS, INC. , SAHA, Samar, K. , KAPOOR, Ashok, K.
发明人： SAHA, Samar, K. , KAPOOR, Ashok, K.
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L29/808 , H01L29/1058 , H01L29/66901
摘要： A junction field effect transistor comprises a semiconductor substrate. A source region of a first conductivity type is formed in the substrate. A drain region of the first conductivity type is formed in the substrate. A channel region of the first conductivity type is formed in the substrate. A gate region of a second conductivity type is formed in the substrate between the source and drain regions. A first virtual link region is formed in the substrate between the gate region and either the source region or the drain region. A dielectric material overlays the first virtual link region. A first electrode region overlays the dielectric material.
摘要翻译：结型场效应晶体管包括半导体衬底。在衬底中形成第一导电类型的源极区域。在衬底中形成第一导电类型的漏区。第一导电类型的沟道区形成在衬底中。在源极和漏极区域之间的衬底中形成第二导电类型的栅极区域。第一虚拟连接区域形成在栅极区域与源极区域或漏极区域之间的衬底中。电介质材料覆盖第一虚拟连接区域。第一电极区覆盖电介质材料。

2. 发明申请

WO2010011487A3 JUNCTION FIELD EFFECT TRANSISTOR USING A SILICON ON INSULATOR ARCHITECTURE 审中-公开
公开(公告)号：WO2010011487A3
公开(公告)日：2010-01-28
申请号：PCT/US2009/049663
申请日：2009-07-06
申请人： DSM SOLUTIONS, INC. , KAPOOR, Ashok, K.
发明人： KAPOOR, Ashok, K.
IPC分类号： H01L29/78 , H01L21/336 , H01L21/20
摘要： A junction field effect transistor comprises a silicon-on-insulator architecture. A front gate region and a back gate region are formed in a silicon region of the SOI architecture. The silicon region has a thin depth such that the back gate region has a thin depth, and whereby a depletion region associated with the back gate region recedes substantially up to an insulating layer of the SOI architecture.

3. 发明申请

WO2009088628A3 STATIC RANDOM ACCESS MEMORY HAVING CELLS WITH JUNCTION FIELD EFFECT AND BIPOLAR JUNCTION TRANSISTORS 审中-公开
公开(公告)号：WO2009088628A3
公开(公告)日：2009-07-16
申请号：PCT/US2008/086311
申请日：2008-12-11
申请人： DSM SOLUTIONS, INC. , KAPOOR, Ashok, K. , THUMMALAPALLY, Damodar, R. , RAY, Abhijit (NMI)
发明人： KAPOOR, Ashok, K. , THUMMALAPALLY, Damodar, R. , RAY, Abhijit (NMI)
IPC分类号： G11C11/41
摘要： A static random access memory (SRAM) device can include at least one SRAM cell having storage section that includes at least a first junction field effect transistor (JFET) with a gate terminal formed from a semiconductor layer deposited on a substrate surface. The storage section can also include at least a first storage node that provides a potential corresponding to a stored data value. The SRAM cell further includes a first access section that includes at least a first bipolar junction transistor (BJT) having an emitter formed from the semiconductor layer.

4. 发明申请

WO2008137627A1 SEMICONDUCTOR DEVICE HAVING A FIN STRUCTURE AND FABRICATION METHOD THEREOF 审中-公开
标题翻译：具有精细结构和制造方法的半导体器件
公开(公告)号：WO2008137627A1
公开(公告)日：2008-11-13
申请号：PCT/US2008/062338
申请日：2008-05-02
申请人： DSM SOLUTIONS, INC. , KAPOOR, Ashok, K.
发明人： KAPOOR, Ashok, K.
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L29/8086 , H01L29/66901 , H01L29/785
摘要： A semiconductor device includes a silicon on insulator (SOI) substrate, comprising an insulation layer formed on semiconductor material, and a fin structure. The fin structure is formed of semiconductor material and extends from the SOI substrate. Additionally, the fin structure includes a source region, a drain region, a channel region, and a gate region. The source region, drain region, and the channel region are doped with a first type of impurities, and the gate region is doped with a second type of impurities. The gate region abuts the channel region along at least one boundary, and the channel region is operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state.
摘要翻译：半导体器件包括绝缘体上硅（SOI）衬底，其包括形成在半导体材料上的绝缘层和鳍结构。翅片结构由半导体材料形成并从SOI衬底延伸。另外，鳍结构包括源极区，漏极区，沟道区和栅极区。源极区域，漏极区域和沟道区域掺杂有第一类型的杂质，并且栅极区域掺杂有第二类型的杂质。栅极区域沿着至少一个边界邻接沟道区域，并且当半导体器件工作在导通状态时，沟道区域可操作地在漏极区域和源极区域之间传导电流。

5. 发明申请

WO2009079244A1 SYSTEM AND METHOD FOR ROUTING CONNECTIONS 审中-公开
标题翻译：用于路由连接的系统和方法
公开(公告)号：WO2009079244A1
公开(公告)日：2009-06-25
申请号：PCT/US2008/085782
申请日：2008-12-08
申请人： DSM SOLUTIONS, INC. , ZARKESH-HA, Payman , HAMLIN, Christopher, L. , KAPOOR, Ashok, K. , KOFORD, James, S. , VORA, Madhukar, B.
发明人： ZARKESH-HA, Payman , HAMLIN, Christopher, L. , KAPOOR, Ashok, K. , KOFORD, James, S. , VORA, Madhukar, B.
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method for modeling a circuit includes receiving a netlist that defines a plurality of connections between a plurality of circuit elements and identifying a subset of the connections. The method also includes routing the identified connections with a first group of wires having a first wire width and routing at least a portion of the remaining connections with a second wire width. The second wire width is smaller than the first wire width. The method further includes replacing the first group of wires with a third group of wires having the second wire width.
摘要翻译：一种用于对电路进行建模的方法包括：接收网表，其定义多个电路元件之间的多个连接并识别连接的子集。该方法还包括使用具有第一线宽度的第一组线路路由所识别的连接，并且以第二线宽度路由至少一部分剩余的连接。第二线宽小于第一线宽度。该方法还包括用具有第二线宽度的第三组线代替第一组线。

6. 发明申请

WO2008024655A2 SILICON-ON-INSULATOR (SOI) JUNCTION FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURE 审中-公开
标题翻译：绝缘体绝缘体（SOI）结场效应晶体管及其制造方法
公开(公告)号：WO2008024655A2
公开(公告)日：2008-02-28
申请号：PCT/US2007/075953
申请日：2007-08-15
申请人： DSM SOLUTIONS, INC. , KAPOOR, Ashok, K.
发明人： KAPOOR, Ashok, K.
IPC分类号： H01L27/098
CPC分类号： H01L27/098 , H01L21/26513 , H01L27/1203 , H01L29/66901 , H01L29/8086
摘要： A semiconductor device including complementary junction field effect transistors (JFETs) manufactured on a silicon on insulator (SOI) wafer is disclosed. A p- type JFET includes a control gate formed from n-type polysilicon and an n-type JFET includes a control gate formed from p-type polysilicon. The complementary JFETs may include four terminal JFETs having a back gate formed below a channel region. The back gate may be electrically connected to a control gate formed above a channel region via a cut region in an isolation structure. Furthermore, the complementary JFETs may be formed on strained silicon formed on a silicon germanium (SiGe) or silicon germanium carbon (SiGeC) layer, or the like.
摘要翻译：公开了一种包括在绝缘体上硅（SOI）晶片上制造的互补结场效应晶体管（JFET）的半导体器件。 p型JFET包括由n型多晶硅形成的控制栅极，n型JFET包括由p型多晶硅形成的控制栅极。互补JFET可以包括四个端子JFET，其具有形成在沟道区下方的背栅。背栅可以经由隔离结构中的切割区域电连接到形成在通道区域上方的控制栅极。此外，互补JFET可以形成在形成在硅锗（SiGe）或硅锗碳（SiGeC）层等上的应变硅上。

7. 发明申请

WO2007053485A2 INTEGRATED CIRCUIT USING COMPLEMENTARY JUNCTION FIELD EFFECT TRANSISTOR AND MOS TRANSISTOR IN SILICON AND SILICON ALLOYS 审中-公开
标题翻译：使用相互连接的场效应晶体管和硅和硅合金中的MOS晶体管的集成电路
公开(公告)号：WO2007053485A2
公开(公告)日：2007-05-10
申请号：PCT/US2006/042139
申请日：2006-10-30
申请人： DSM SOLUTIONS, INC. , KAPOOR, Ashok, K.
发明人： KAPOOR, Ashok, K.
IPC分类号： H01L31/111 , H01L21/337
CPC分类号： H01L29/808 , H01L21/2257 , H01L27/0611 , H01L27/098 , H01L29/41783 , H01L29/456 , H01L29/66492 , H01L29/66901 , H01L29/7833
摘要： This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices.
摘要翻译：本发明描述了使用硅中的结型场效应晶体管构建互补逻辑电路的方法。本发明理想地适用于深亚微米尺寸，优选低于65nm。本发明的基础是在增强模式下操作的互补结型场效应晶体管。 JFET的速度功率性能可以与次级70纳米尺寸的CMOS器件相媲美。然而，JFET的最大电源电压仍然限制在低于内置电位（二极管压降）。为了满足需要与驱动到更高电压电平的外部电路接口的某些应用，本发明包括在与JFET器件相同的衬底上构建CMOS器件的结构和方法。

8. 发明申请

WO2009151769A2 SYSTEM AND METHOD FOR ROUTING CONNECTIONS WITH IMPROVED INTERCONNECT THICKNESS 审中-公开
标题翻译：具有改进的互连厚度的连接的系统和方法
公开(公告)号：WO2009151769A2
公开(公告)日：2009-12-17
申请号：PCT/US2009/040460
申请日：2009-04-14
申请人： DSM SOLUTIONS, INC. , ZARKESH-HA, Payman , HAMLIN, Christopher, L. , KAPOOR, Ashok, K. , KOFORD, James, S. , VORA, Madhukar, B.
发明人： ZARKESH-HA, Payman , HAMLIN, Christopher, L. , KAPOOR, Ashok, K. , KOFORD, James, S. , VORA, Madhukar, B.
CPC分类号： H01L23/5283 , G06F17/5077 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A method for modeling a circuit includes generating a circuit model based on a netlist that defines a plurality of connections between a plurality of circuit elements. The circuit model includes a model of one or more of the circuit elements. The method further includes determining a wire width associated with at least a selected connection based, at least in part, on design rules associated with the netlist. Additionally, the method includes determining a wire thickness associated with the selected connection based, at least in part, on a signal delay associated with the wire thickness. Furthermore, the method also includes routing the selected connection in the circuit model using a wire having a width substantially equal to the wire width calculated for the connection and a thickness equal to the wire thickness calculated for the connection and storing the circuit model in an electronic storage media.
摘要翻译：一种用于对电路进行建模的方法包括基于限定多个电路元件之间的多个连接的网表生成电路模型。电路模型包括一个或多个电路元件的模型。该方法还包括至少部分地基于与网表相关联的设计规则来确定与至少所选连接相关联的线宽度。另外，该方法包括至少部分地基于与线材厚度相关联的信号延迟来确定与所选择的连接相关联的线材厚度。此外，该方法还包括使用具有基本上等于为连接计算出的线宽度的宽度的线和对于连接计算的线厚度等于电路模型中的所选择的连接来路由选择的连接，并将电路模型存储在电子储存媒介。

9. 发明申请

WO2009105466A3 REDUCED LEAKAGE CURRENT FIELD-EFFECT TRANSISTOR HAVING ASYMMETRIC DOPING AND FABRICATION METHOD THEREFOR 审中-公开
公开(公告)号：WO2009105466A3
公开(公告)日：2009-08-27
申请号：PCT/US2009/034396
申请日：2009-02-18
申请人： DSM SOLUTIONS, INC. , SAHA, Samar, K. , KAPOOR, Ashok, K.
发明人： SAHA, Samar, K. , KAPOOR, Ashok, K.
IPC分类号： H01L21/336 , H01L29/78 , H01L21/265
摘要： Reduced leakage current field-effect transistors and fabrication methods. Semiconductor device including substrate of first conductivity type, first well and second well of second conductivity type in substrate, channel of second conductivity type between first well and second well in substrate, and gate region of first conductivity type within channel, wherein gate region is electrically operable to modulate depletion width of channel. First well may be a drain region and the second well may be a source region. Channel includes first link region between gate region and first well or drain region and second link region between the gate region and second well or source region; wherein first link region is of second conductivity type of at least two doping densities. First link region is higher doped in a portion adjacent to drain region than in another portion adjacent to gate region. Method of fabricating a reduced leakage current FET.

10. 发明申请

WO2008137317A1 SEMICONDUCTOR DEVICE HAVING STRAIN-INDUCING SUBSTRATE AND FABRICATION METHODS THEREOF 审中-公开
标题翻译：具有应变诱导基板的半导体器件及其制造方法
公开(公告)号：WO2008137317A1
公开(公告)日：2008-11-13
申请号：PCT/US2008/061198
申请日：2008-04-23
申请人： DSM SOLUTIONS, INC. , KAPOOR, Ashok, K.
发明人： KAPOOR, Ashok, K.
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L29/808 , H01L29/1029 , H01L29/66901
摘要： A semiconductor device (10) includes a semiconductor substrate (12) that includes a substrate layer having a first composition of semiconductor material. A source region (20), drain region (40), and a channel region (60) are formed in the substrate, with the drain region (20) spaced apart from the source region (40) and the gate region (30) abutting the channel region (60). The channel region (60) includes a channel layer (62) having a second composition of semiconductor material. Additionally, the substrate layer abuts the channel layer (62) and applies a stress to the channel region (62) along a boundary between the substrate layer and the channel layer (62).
摘要翻译：半导体器件（10）包括半导体衬底（12），其包括具有半导体材料的第一组成的衬底层。源极区域（20），漏极区域（40）和沟道区域（60）形成在衬底中，漏极区域（20）与源极区域（40）隔开并且栅极区域（30）邻接通道区域（60）。沟道区（60）包括具有半导体材料的第二组成的沟道层（62）。此外，衬底层邻接通道层（62）并且沿着衬底层和沟道层（62）之间的边界向沟道区域（62）施加应力。

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