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1. 发明申请

WO2005024900A2 BIPOLAR TRANSISTOR HAVING RAISED EXTRINSIC BASE WITH SELECTABLE SELF-ALIGNMENT AND METHODS OF FORMING SAME 审中-公开
标题翻译：双极晶体管具有可选择的自对准的提取的外排基底和形成相同的方法
公开(公告)号：WO2005024900A2
公开(公告)日：2005-03-17
申请号：PCT/US2004/021345
申请日：2004-07-01
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , KHATER, Marwan, H. , DUNN, James, S. , HARAME, David, L. , JOSEPH, Alvin, J. , LIU, Qizhi , PAGETTE, Francois , ST. ONGE, Stephen, A. , STRICKER, Andreas, D.
发明人： KHATER, Marwan, H. , DUNN, James, S. , HARAME, David, L. , JOSEPH, Alvin, J. , LIU, Qizhi , PAGETTE, Francois , ST. ONGE, Stephen, A. , STRICKER, Andreas, D.
IPC分类号： H01L
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter (106) is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer (102) of polysilicon or silicon on an intrinsic base (108). A dielectric landing pad (128) is then formed by lithography on the first extrinsic base layer (102). Next, a second extrinsic base layer (104) of polysilicon or silicon is formed on top of the dielectric landing pad (128) to finalize the raised extrinsic base total thickness. An emitter (106) opening is formed using lithography and RIE, where the second extrinsic base layer (104) is etched stopping on the dielectric landing pad (128). The degree of self-alignment between the emitter (106) and the raised extrinsic base is achieved by selecting the first extrinsic base layer (102) thickness, the dielectric landing pad (128) width, and the spacer width.
摘要翻译：公开了具有升高的外部基极和外部基极与发射极（106）之间的可选自对准的双极晶体管。制造方法可以包括在内部基极（108）上形成预定厚度的多晶硅或硅的第一非本征基极层（102）。然后通过光刻在第一非本征基极层（102）上形成电介质接合焊盘（128）。接下来，在电介质着陆垫（128）的顶部上形成多晶硅或硅的第二非本征基极层（104），以完成升高的非本征基极总厚度。使用光刻和RIE形成发射器（106）开口，其中第二非本征基极层（104）被蚀刻停止在电介质着陆焊盘（128）上。通过选择第一非本征基极层（102）厚度，电介质着陆垫（128）宽度和隔离物宽度来实现发射极（106）和凸起的非本征基极之间的自对准程度。

2. 发明申请

WO2013006277A3 BIPOLAR JUNCTION TRANSISTORS WITH A LINK REGION CONNECTING THE INTRINSIC AND EXTRINSIC BASES 审中-公开
公开(公告)号：WO2013006277A3
公开(公告)日：2013-01-10
申请号：PCT/US2012/043443
申请日：2012-06-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , CAMILLO-CASTILLO, Renata , GRAY, Peter, B. , HARAME, David, L. , JOSEPH, Alvin, J. , KHATER, Marwan, H. , LIU, Qizhi
发明人： CAMILLO-CASTILLO, Renata , GRAY, Peter, B. , HARAME, David, L. , JOSEPH, Alvin, J. , KHATER, Marwan, H. , LIU, Qizhi
IPC分类号： H01L29/73
摘要： Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor (80) includes a dielectric layer (32) on an intrinsic base (84) and an extrinsic base (82) at least partially separated from the intrinsic base by the dielectric layer. An emitter opening (52) extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity (60a, 60b) between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer (64) that physically links the extrinsic base and the intrinsic base together.

3. 发明申请

WO2006053257A1 BIPOLAR TRANSISTOR WITH SELFALIGNED SILICIDE AND EXTRINSIC BASE 审中-公开
标题翻译：双极晶体管，具有自熔硅酸盐和极好的基底
公开(公告)号：WO2006053257A1
公开(公告)日：2006-05-18
申请号：PCT/US2005/041049
申请日：2005-11-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , KHATER, Marwan, H. , PAGETTE, Francois
发明人： KHATER, Marwan, H. , PAGETTE, Francois
IPC分类号： H01L27/082 , H01L21/331
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/66272 , H01L29/732
摘要： Disclosed is a bipolar transistor and a method of forming the transistor, where the transistor includes a collector (12) in a substrate (10), an intrinsic base (14) above the collector, an extrinsic base adjacent the intrinsic base, and an emitter (130) above the intrinsic base. The extrinsic base includes extrinsic base implant regions (82, 172, 192) adjacent the intrinsic base, when viewed in cross-section. The transistor is formed by patterning an emitter pedestal (50) for the lower portion of the emitter on the substrate above the intrinsic base. The extrinsic base is formed in regions not protected by the emitter pedestal. Subsequently, the emitter, associated spacers (180) and a silicide region (220) are formed. The silicide, extrinsic base and emitter are all self-aligned with each other.
摘要翻译：公开了双极晶体管和形成晶体管的方法，其中晶体管包括在衬底（10）中的集电极（12），集电极之上的本征基极（14），与本征基极相邻的外部基极和发射极（130）高于内在基数。当从横截面观察时，外部基极包括与本征基底相邻的外部基极注入区域（82,172,192）。晶体管通过对位于本征基极上方的衬底上的发射极的下部的发射极基座（50）进行构图而形成。外部基极形成在不受发射极基座保护的区域中。随后，形成发射极，相关联的间隔物（180）和硅化物区域（220）。硅化物，非本征基极和发射极都彼此自对准。

4. 发明申请

WO2013006277A2 BIPOLAR JUNCTION TRANSISTORS WITH A LINK REGION CONNECTING THE INTRINSIC AND EXTRINSIC BASES 审中-公开
标题翻译：具有连接本地和特殊基础的连接区域的双极性连接晶体管
公开(公告)号：WO2013006277A2
公开(公告)日：2013-01-10
申请号：PCT/US2012043443
申请日：2012-06-21
申请人： IBM , CAMILLO-CASTILLO RENATA , GRAY PETER B , HARAME DAVID L , JOSEPH ALVIN J , KHATER MARWAN H , LIU QIZHI
发明人： CAMILLO-CASTILLO RENATA , GRAY PETER B , HARAME DAVID L , JOSEPH ALVIN J , KHATER MARWAN H , LIU QIZHI
CPC分类号： H01L29/73 , H01L21/8249 , H01L27/0623 , H01L29/0821 , H01L29/107 , H01L29/66272 , H01L29/7322
摘要： Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor (80) includes a dielectric layer (32) on an intrinsic base (84) and an extrinsic base (82) at least partially separated from the intrinsic base by the dielectric layer. An emitter opening (52) extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity (60a, 60b) between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer (64) that physically links the extrinsic base and the intrinsic base together.
摘要翻译：用于制造双极结晶体管的方法，通过该方法制造的双极结型晶体管以及双极结型晶体管的设计结构。双极结晶体管（80）包括在本征基极（84）上的介电层（32）和通过介电层至少部分地与本征基极分离的外部基极（82）。发射极开口（52）延伸穿过外部基极和电介质层。电介质层相对于发射极开口横向凹入以限定内部基极和外部基极之间的空腔（60a，60b）。空腔填充有将外部基极和固有基底物理连接在一起的半导体层（64）。

5. 发明申请

WO2005024900A3 BIPOLAR TRANSISTOR HAVING RAISED EXTRINSIC BASE WITH SELECTABLE SELF-ALIGNMENT AND METHODS OF FORMING SAME 审中-公开
标题翻译：具有可选择的自对准的提升的超级基座的双极晶体管及其形成方法
公开(公告)号：WO2005024900A3
公开(公告)日：2005-06-09
申请号：PCT/US2004021345
申请日：2004-07-01
申请人： IBM , KHATER MARWAN H , DUNN JAMES S , HARAME DAVID L , JOSEPH ALVIN J , LIU QIZHI , PAGETTE FRANCOIS , ST ONGE STEPHEN A , STRICKER ANDREAS D
发明人： KHATER MARWAN H , DUNN JAMES S , HARAME DAVID L , JOSEPH ALVIN J , LIU QIZHI , PAGETTE FRANCOIS , ST ONGE STEPHEN A , STRICKER ANDREAS D
IPC分类号： H01L21/331 , H01L29/10 , H01L29/732 , H01L29/737 , H01L23/62
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter (106) is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer (102) of polysilicon or silicon on an intrinsic base (108). A dielectric landing pad (128) is then formed by lithography on the first extrinsic base layer (102). Next, a second extrinsic base layer (104) of polysilicon or silicon is formed on top of the dielectric landing pad (128) to finalize the raised extrinsic base total thickness. An emitter (106) opening is formed using lithography and RIE, where the second extrinsic base layer (104) is etched stopping on the dielectric landing pad (128). The degree of self-alignment between the emitter (106) and the raised extrinsic base is achieved by selecting the first extrinsic base layer (102) thickness, the dielectric landing pad (128) width, and the spacer width.
摘要翻译：公开了一种具有凸起的非本征基极和在本征基极和发射极（106）之间的可选自对准的双极晶体管。制造方法可以包括在内在基极（108）上形成多晶硅或硅的第一非本征基极层（102）的预定厚度。然后通过光刻在第一非本征基极层（102）上形成电介质着色焊盘（128）。接下来，在电介质着色焊盘（128）的顶部上形成多晶硅或硅的第二非本征基极层（104），以最终确定凸出的非本征基本总厚度。使用光刻和RIE形成发射器（106）开口，其中第二外部基极层（104）被蚀刻停止在电介质着色焊盘（128）上。通过选择第一非本征基极层（102）的厚度，电介质着陆焊盘（128）的宽度和间隔物宽度来实现发射极（106）和凸起的外在基极之间的自对准程度。

6. 发明申请

WO0219387A3 TRANSMISSION LINE BASED INDUCTIVELY COUPLED PLASMA SOURCE WITH STABLE IMPEDANCE 审中-公开
标题翻译：基于传输线的电感耦合等离子体源具有稳定的阻抗
公开(公告)号：WO0219387A3
公开(公告)日：2003-01-30
申请号：PCT/US0126326
申请日：2001-08-23
申请人： REGENTS BOARD OF , KHATER MARWAN H , OVERZET LAWRENCE J
发明人： KHATER MARWAN H , OVERZET LAWRENCE J
IPC分类号： H01J37/32 , B23K10/00
CPC分类号： H01J37/321
摘要： A properly designed and positioned Faraday shield/dielectric spacer/source-coil assembly is used to nearly fix the input impedanceof an Inductively Coupled Plasma (ICP) source-coil (130), making a variable matching network almost unnecessary, and allowing for pulsed plasma processing with very little reflected power. This is not possible without a properly designed and positioned Faraday shield (150) because the source-coil impedance is coupled to that of the plasma and changes significantly with the plasma conditions. The ICP source-coil/dielectric spacer/Faraday shield assembly can then be designed to optimize the symmetry of the plasma generation independent of plasma conditions by varying the source structure (130), dielectric spacer material, dielectric spacer structure (140), and Faraday shield structure (150). An appropriately positioned aperture in the Faraday shield can allow enough capacitive coupling between to ignite the plasma while preventing any significant capacitive coupling.
摘要翻译：使用适当设计和定位的法拉第屏蔽/介质间隔物/源线圈组件几乎固定感应耦合等离子体（ICP）源线圈（130）的输入阻抗，使得可变匹配网络几乎不必要，并允许脉冲等离子体加工反射能力很小。如果没有正确设计和定位的法拉第屏蔽（150），这是不可能的，因为源极线圈阻抗与等离子体的阻抗耦合，并且与等离子体条件显着变化。然后可以设计ICP源线圈/电介质间隔物/法拉第屏蔽组件，以通过改变源结构（130），介电间隔物材料，介电间隔物结构（140）和法拉第（140），从而优化等离子体生成的对称性，而不依赖于等离子体条件屏蔽结构（150）。法拉第屏蔽中适当定位的孔径可以允许足够的电容耦合来点燃等离子体，同时防止任何显着的电容耦合。

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