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1. 发明申请

WO2010011536A3 JUNCTION FIELD EFFECT TRANSISTOR USING SILICIDE CONNECTION REGIONS AND METHOD OF FABRICATION 审中-公开
标题翻译：使用硅氧烷连接区域的连接场效应晶体管和制造方法
公开(公告)号：WO2010011536A3
公开(公告)日：2010-04-01
申请号：PCT/US2009050634
申请日：2009-07-15
申请人： DSM SOLUTIONS INC , KAPOOR ASHOK K , VORA MADHUKAR B
发明人： KAPOOR ASHOK K , VORA MADHUKAR B
IPC分类号： H01L29/80
CPC分类号： H01L29/8086 , H01L29/458 , H01L29/66901
摘要： A junction field effect transistor comprises a semiconductor substrate and a well region formed in the substrate. A source region of a first conductivity type is formed in the well region. A drain region of the first conductivity type is formed in the well region and spaced apart from the source region. A channel region of the first conductivity type is located between the source region and the drain region and formed in the well region. A gate region of a second conductivity type is formed in the well region. The transistor further includes first, second, and third connection regions. The first connection region is in ohmic contact with the source region and formed of suicide. The second connection region is in ohmic contact with the drain region and formed of suicide. The third connection region in ohmic contact with the gate region.
摘要翻译：结型场效应晶体管包括半导体衬底和形成在衬底中的阱区。在阱区中形成第一导电类型的源极区域。第一导电类型的漏极区域形成在阱区域中并且与源极区域间隔开。第一导电类型的沟道区域位于源极区域和漏极区域之间并且形成在阱区域中。在阱区中形成第二导电类型的栅极区域。晶体管还包括第一，第二和第三连接区域。第一连接区域与源区域欧姆接触并形成自杀剂。第二连接区域与漏极区域欧姆接触并由硅化物形成。第三连接区域与栅极区域欧姆接触。

2. 发明申请

WO2010011487A2 JUNCTION FIELD EFFECT TRANSISTOR USING A SILICON ON INSULATOR ARCHITECTURE 审中-公开
标题翻译：使用绝缘体结构上的硅的连接场效应晶体管
公开(公告)号：WO2010011487A2
公开(公告)日：2010-01-28
申请号：PCT/US2009049663
申请日：2009-07-06
申请人： DSM SOLUTIONS INC , KAPOOR ASHOK K
发明人： KAPOOR ASHOK K
IPC分类号： H01L29/78 , H01L21/20 , H01L21/336
CPC分类号： H01L29/808 , H01L29/107 , H01L29/812
摘要： A junction field effect transistor comprises a silicon-on-insulator architecture. A front gate region and a back gate region are formed in a silicon region of the SOI architecture. The silicon region has a thin depth such that the back gate region has a thin depth, and whereby a depletion region associated with the back gate region recedes substantially up to an insulating layer of the SOI architecture.
摘要翻译：结型场效应晶体管包括绝缘体上硅结构。在SOI结构的硅区域中形成前栅极区域和背栅极区域。硅区域具有薄的深度，使得背栅区域具有薄的深度，并且由此与背栅区域相关联的耗尽区域基本上后退到SOI结构的绝缘层。

3. 发明申请

WO2008137294A1 JFET DEVICE WITH VIRTUAL SOURCE AND DRAIN LINK REGIONS AND METHOD OF FABRICATION 审中-公开
标题翻译：具有虚拟源和漏极链接区域的JFET器件和制造方法
公开(公告)号：WO2008137294A1
公开(公告)日：2008-11-13
申请号：PCT/US2008/060987
申请日：2008-04-21
申请人： DSM SOLUTIONS, INC. , SAHA, Samar, K. , KAPOOR, Ashok, K.
发明人： SAHA, Samar, K. , KAPOOR, Ashok, K.
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L29/808 , H01L29/1058 , H01L29/66901
摘要： A junction field effect transistor comprises a semiconductor substrate. A source region of a first conductivity type is formed in the substrate. A drain region of the first conductivity type is formed in the substrate. A channel region of the first conductivity type is formed in the substrate. A gate region of a second conductivity type is formed in the substrate between the source and drain regions. A first virtual link region is formed in the substrate between the gate region and either the source region or the drain region. A dielectric material overlays the first virtual link region. A first electrode region overlays the dielectric material.
摘要翻译：结型场效应晶体管包括半导体衬底。在衬底中形成第一导电类型的源极区域。在衬底中形成第一导电类型的漏区。第一导电类型的沟道区形成在衬底中。在源极和漏极区域之间的衬底中形成第二导电类型的栅极区域。第一虚拟连接区域形成在栅极区域与源极区域或漏极区域之间的衬底中。电介质材料覆盖第一虚拟连接区域。第一电极区覆盖电介质材料。

4. 发明申请

WO2009151769A3 SYSTEM AND METHOD FOR ROUTING CONNECTIONS WITH IMPROVED INTERCONNECT THICKNESS 审中-公开
标题翻译：具有改进的互连厚度的连接的系统和方法
公开(公告)号：WO2009151769A3
公开(公告)日：2010-04-22
申请号：PCT/US2009040460
申请日：2009-04-14
申请人： DSM SOLUTIONS INC , ZARKESH-HA PAYMAN , HAMLIN CHRISTOPHER L , KAPOOR ASHOK K , KOFORD JAMES S , VORA MADHUKAR B
发明人： ZARKESH-HA PAYMAN , HAMLIN CHRISTOPHER L , KAPOOR ASHOK K , KOFORD JAMES S , VORA MADHUKAR B
IPC分类号： H01L29/40 , H01L29/80
CPC分类号： H01L23/5283 , G06F17/5077 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A method for modeling a circuit includes generating a circuit model based on a netlist that defines a plurality of connections between a plurality of circuit elements. The circuit model includes a model of one or more of the circuit elements. The method further includes determining a wire width associated with at least a selected connection based, at least in part, on design rules associated with the netlist. Additionally, the method includes determining a wire thickness associated with the selected connection based, at least in part, on a signal delay associated with the wire thickness. Furthermore, the method also includes routing the selected connection in the circuit model using a wire having a width substantially equal to the wire width calculated for the connection and a thickness equal to the wire thickness calculated for the connection and storing the circuit model in an electronic storage media.
摘要翻译：一种用于对电路进行建模的方法包括基于限定多个电路元件之间的多个连接的网表生成电路模型。电路模型包括一个或多个电路元件的模型。该方法还包括至少部分地基于与网表相关联的设计规则来确定与至少所选连接相关联的线宽度。另外，该方法包括至少部分地基于与线材厚度相关联的信号延迟来确定与所选择的连接相关联的线材厚度。此外，该方法还包括使用具有基本上等于为连接计算出的线宽度的宽度的线和对于连接计算的线厚度等于电路模型中的所选择的连接来路由选择的连接，并将电路模型存储在电子储存媒介。

5. 发明申请

WO2009151769A2 SYSTEM AND METHOD FOR ROUTING CONNECTIONS WITH IMPROVED INTERCONNECT THICKNESS 审中-公开
标题翻译：具有改进的互连厚度的连接的系统和方法
公开(公告)号：WO2009151769A2
公开(公告)日：2009-12-17
申请号：PCT/US2009/040460
申请日：2009-04-14
申请人： DSM SOLUTIONS, INC. , ZARKESH-HA, Payman , HAMLIN, Christopher, L. , KAPOOR, Ashok, K. , KOFORD, James, S. , VORA, Madhukar, B.
发明人： ZARKESH-HA, Payman , HAMLIN, Christopher, L. , KAPOOR, Ashok, K. , KOFORD, James, S. , VORA, Madhukar, B.
CPC分类号： H01L23/5283 , G06F17/5077 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A method for modeling a circuit includes generating a circuit model based on a netlist that defines a plurality of connections between a plurality of circuit elements. The circuit model includes a model of one or more of the circuit elements. The method further includes determining a wire width associated with at least a selected connection based, at least in part, on design rules associated with the netlist. Additionally, the method includes determining a wire thickness associated with the selected connection based, at least in part, on a signal delay associated with the wire thickness. Furthermore, the method also includes routing the selected connection in the circuit model using a wire having a width substantially equal to the wire width calculated for the connection and a thickness equal to the wire thickness calculated for the connection and storing the circuit model in an electronic storage media.
摘要翻译：一种用于对电路进行建模的方法包括基于限定多个电路元件之间的多个连接的网表生成电路模型。电路模型包括一个或多个电路元件的模型。该方法还包括至少部分地基于与网表相关联的设计规则来确定与至少所选连接相关联的线宽度。另外，该方法包括至少部分地基于与线材厚度相关联的信号延迟来确定与所选择的连接相关联的线材厚度。此外，该方法还包括使用具有基本上等于为连接计算出的线宽度的宽度的线和对于连接计算的线厚度等于电路模型中的所选择的连接来路由选择的连接，并将电路模型存储在电子储存媒介。

6. 发明申请

WO2009105466A3 REDUCED LEAKAGE CURRENT FIELD-EFFECT TRANSISTOR HAVING ASYMMETRIC DOPING AND FABRICATION METHOD THEREFOR 审中-公开
公开(公告)号：WO2009105466A3
公开(公告)日：2009-08-27
申请号：PCT/US2009/034396
申请日：2009-02-18
申请人： DSM SOLUTIONS, INC. , SAHA, Samar, K. , KAPOOR, Ashok, K.
发明人： SAHA, Samar, K. , KAPOOR, Ashok, K.
IPC分类号： H01L21/336 , H01L29/78 , H01L21/265
摘要： Reduced leakage current field-effect transistors and fabrication methods. Semiconductor device including substrate of first conductivity type, first well and second well of second conductivity type in substrate, channel of second conductivity type between first well and second well in substrate, and gate region of first conductivity type within channel, wherein gate region is electrically operable to modulate depletion width of channel. First well may be a drain region and the second well may be a source region. Channel includes first link region between gate region and first well or drain region and second link region between the gate region and second well or source region; wherein first link region is of second conductivity type of at least two doping densities. First link region is higher doped in a portion adjacent to drain region than in another portion adjacent to gate region. Method of fabricating a reduced leakage current FET.

7. 发明申请

WO2008118824A3 SIGNALING CIRCUIT AND METHOD FOR INTEGRATED CIRCUIT DEVICES AND SYSTEMS 审中-公开
标题翻译：用于集成电路设备和系统的信号电路和方法
公开(公告)号：WO2008118824A3
公开(公告)日：2009-05-07
申请号：PCT/US2008057943
申请日：2008-03-21
申请人： DSM SOLUTIONS INC , KAPOOR ASHOK K
发明人： KAPOOR ASHOK K
IPC分类号： G06F13/40 , H01L21/331 , H01L21/8248 , H01L27/06 , H01L29/73 , H01L29/808 , H03K19/0175
CPC分类号： H01L21/8248 , H01L27/0623 , H01L29/0692 , H01L29/0804 , H01L29/1004 , H01L29/66272 , H01L29/66901 , H01L29/732 , H01L29/808 , H03K5/2418 , H03K19/001 , H04L25/0264
摘要： Integrated circuit systems and semiconductor devices for generating, transmitting, receiving and manipulating clock and/or data signals. Semiconductor device including clock circuit having FETs and clock driver circuit having BJT. System and devices may include translator circuit translating signals with lower voltage swing into signals with higher voltage swing and circuit block operating at higher voltage swing. Wiring networks for communicating signals between individual circuits or system components. Integrated circuit device can include a BJT having first base electrode comprising semiconductor material doped to first conductivity type formed on and in contact with surface of semiconductor substrate and separated from emitter electrode by separation space. First base region can be formed in substrate below emitter electrode and include first portion of substrate doped to first conductivity type. Second base region can be formed in substrate below separation space and can include second portion of substrate doped to first conductivity type.
摘要翻译：用于生成，发送，接收和操纵时钟和/或数据信号的集成电路系统和半导体器件。包括具有FET的时钟电路和具有BJT的时钟驱动器电路的半导体器件。系统和设备可以包括转换器电路将具有较低电压摆幅的信号转换成具有较高电压摆幅的信号，并且在更高的电压摆幅下操作电路块。用于在各个电路或系统组件之间传送信号的接线网络。集成电路器件可以包括具有第一基极的BJT，该第一基极包括掺杂到第一导电类型的半导体材料，该半导体材料形成在半导体衬底的表面上并与半导体衬底的表面接触，并且通第一基区可以形成在发射极电极下方的衬底中，并且包括掺杂到第一导电类型的衬底的第一部分。第二基区可以形成在分离空间下方的衬底中，并且可以包括掺杂到第一导电类型的衬底的第二部分。

8. 发明申请

WO2008137317A1 SEMICONDUCTOR DEVICE HAVING STRAIN-INDUCING SUBSTRATE AND FABRICATION METHODS THEREOF 审中-公开
标题翻译：具有应变诱导基板的半导体器件及其制造方法
公开(公告)号：WO2008137317A1
公开(公告)日：2008-11-13
申请号：PCT/US2008/061198
申请日：2008-04-23
申请人： DSM SOLUTIONS, INC. , KAPOOR, Ashok, K.
发明人： KAPOOR, Ashok, K.
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L29/808 , H01L29/1029 , H01L29/66901
摘要： A semiconductor device (10) includes a semiconductor substrate (12) that includes a substrate layer having a first composition of semiconductor material. A source region (20), drain region (40), and a channel region (60) are formed in the substrate, with the drain region (20) spaced apart from the source region (40) and the gate region (30) abutting the channel region (60). The channel region (60) includes a channel layer (62) having a second composition of semiconductor material. Additionally, the substrate layer abuts the channel layer (62) and applies a stress to the channel region (62) along a boundary between the substrate layer and the channel layer (62).
摘要翻译：半导体器件（10）包括半导体衬底（12），其包括具有半导体材料的第一组成的衬底层。源极区域（20），漏极区域（40）和沟道区域（60）形成在衬底中，漏极区域（20）与源极区域（40）隔开并且栅极区域（30）邻接通道区域（60）。沟道区（60）包括具有半导体材料的第二组成的沟道层（62）。此外，衬底层邻接通道层（62）并且沿着衬底层和沟道层（62）之间的边界向沟道区域（62）施加应力。

9. 发明申请

WO2008137304A1 JFET DEVICE WITH IMPROVED OFF-STATE LEAKAGE CURRENT AND METHOD OF FABRICATION 审中-公开
标题翻译：具有改进的非状态泄漏电流的JFET器件和制造方法
公开(公告)号：WO2008137304A1
公开(公告)日：2008-11-13
申请号：PCT/US2008/061095
申请日：2008-04-22
申请人： DSM SOLUTIONS, INC. , SAHA, Samar, K. , KAPOOR, Ashok, K.
发明人： SAHA, Samar, K. , KAPOOR, Ashok, K.
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L29/808 , H01L29/66901
摘要： A junction field effect transistor comprises a semiconductor substrate (90). A first impurity region (20) of a first conductivity type is formed in the substrate. A second impurity region (40) of the first conductivity type is formed in the substrate and spaced apart from the first impurity region. A channel region (60) of the first conductivity type is formed between the first and second impurity regions (20, 40). A gate region (30) of a second conductivity type is formed in the substrate (90) between the first and second impurity regions (20, 40). A gap region (52a) is formed in the substrate between the gate region (30) and the first impurity region (20) such that the first impurity region (20) is spaced apart from the gate region (30).
摘要翻译：结型场效应晶体管包括半导体衬底（90）。在衬底中形成第一导电类型的第一杂质区（20）。第一导电类型的第二杂质区（40）形成在衬底中并与第一杂质区隔开。第一导电类型的沟道区（60）形成在第一和第二杂质区（20,40）之间。在第一和第二杂质区域（20,40）之间的衬底（90）中形成第二导电类型的栅极区域（30）。在栅极区域（30）和第一杂质区域（20）之间的衬底中形成间隙区域（52a），使得第一杂质区域（20）与栅极区域（30）间隔开。

10. 发明申请

WO2010011536A2 JUNCTION FIELD EFFECT TRANSISTOR USING SILICIDE CONNECTION REGIONS AND METHOD OF FABRICATION 审中-公开
标题翻译：使用硅化物连接区域的结型场效应晶体管及其制造方法
公开(公告)号：WO2010011536A2
公开(公告)日：2010-01-28
申请号：PCT/US2009/050634
申请日：2009-07-15
申请人： DSM SOLUTIONS, INC. , KAPOOR, Ashok, K. , VORA, Madhukar, B.
发明人： KAPOOR, Ashok, K. , VORA, Madhukar, B.
IPC分类号： H01L29/80
CPC分类号： H01L29/8086 , H01L29/458 , H01L29/66901
摘要： A junction field effect transistor comprises a semiconductor substrate and a well region formed in the substrate. A source region of a first conductivity type is formed in the well region. A drain region of the first conductivity type is formed in the well region and spaced apart from the source region. A channel region of the first conductivity type is located between the source region and the drain region and formed in the well region. A gate region of a second conductivity type is formed in the well region. The transistor further includes first, second, and third connection regions. The first connection region is in ohmic contact with the source region and formed of suicide. The second connection region is in ohmic contact with the drain region and formed of suicide. The third connection region in ohmic contact with the gate region.
摘要翻译：结型场效应晶体管包括半导体衬底和形成在衬底中的阱区。第一导电类型的源极区域形成在阱区域中。第一导电类型的漏极区形成在阱区中并与源极区隔开。第一导电类型的沟道区位于源极区和漏极区之间并形成在阱区中。第二导电类型的栅极区域形成在阱区域中。晶体管还包括第一，第二和第三连接区域。第一连接区域与源极区域欧姆接触并由硅化物形成。第二连接区与漏极区欧姆接触并由硅化物形成。第三个连接区与栅极区欧姆接触。

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