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1. 发明申请

WO2017215038A1 电极的制备方法审中-公开
公开(公告)号：WO2017215038A1
公开(公告)日：2017-12-21
申请号：PCT/CN2016/087677
申请日：2016-06-29
申请人：深圳市华星光电技术有限公司
发明人：周志超 , 夏慧
IPC分类号： H01L21/82
CPC分类号： H01L21/0425 , G02F1/13439 , H01L21/28123 , H01L21/82 , H01L27/1218 , H01L27/124 , H01L27/1288 , H01L29/78603
摘要：本发明公开一种电极的制备方法，包括：提供衬底；在所述衬底上形成缓冲层；在所述缓冲层的远离所述衬底的表面上形成图案化的光阻，所述光阻具有相对设置的底面和顶面以及连接在所述底面与所述顶面之间的侧面，所述底面贴合所述缓冲层；通过干蚀刻，将所述缓冲层的未被所述光阻覆盖的部分去除，以形成容纳区；沉积导电膜层，所述导电膜层包括形成在所述顶面上的废料和填充于所述容纳区的电极；以及剥离所述废料和所述光阻。本发明所述电极的制备方法的良品率高。

2. 发明申请

WO2016062358A1 TRANSISTOR 审中-公开
标题翻译：晶体管
公开(公告)号：WO2016062358A1
公开(公告)日：2016-04-28
申请号：PCT/EP2014/072914
申请日：2014-10-24
申请人： X-FAB SEMICONDUCTOR FOUNDRIES AG
发明人： KIM, Hyeon Cheol , ECKOLDT, Uwe , YANG, Peng
IPC分类号： H01L21/28 , H01L21/285 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/4238 , H01L21/28052 , H01L21/28105 , H01L21/28123 , H01L29/4983 , H01L29/665 , H01L29/78
摘要： There is provided a transistor comprising a source, gate and a drain, the source, gate and drain being arranged next to each other in a lengthwise direction of the transistor. The gate comprises a layer of an at least partially conductive material, wherein said layer has a recess such that, at a lengthwise position within the recess, the width of said layer is smaller than at a lengthwise position outside the recess.
摘要翻译：提供了一种包括源极，栅极和漏极的晶体管，源极，栅极和漏极在晶体管的长度方向上彼此相邻布置。栅极包括至少部分导电材料的层，其中所述层具有凹部，使得在凹部内的纵向位置处，所述层的宽度小于凹部外侧的纵向位置。

3. 发明申请

WO2014098990A1 PATTERNING OF VERTICAL NANOWIRE TRANSISTOR CHANNEL AND GATE WITH DIRECTED SELF ASSEMBLY 审中-公开
标题翻译：用直线自组装法绘制垂直纳米晶体管通道和闸门
公开(公告)号：WO2014098990A1
公开(公告)日：2014-06-26
申请号：PCT/US2013/046899
申请日：2013-06-20
申请人： INTEL CORPORATION
发明人： NYHUS, Paul A. , SIVAKUMAR, Swaminathan
IPC分类号： H01L21/336 , H01L29/78 , H01L21/027
CPC分类号： H01L21/823487 , B82Y10/00 , B82Y40/00 , H01L21/02532 , H01L21/02603 , H01L21/02642 , H01L21/28123 , H01L21/30625 , H01L21/823412 , H01L21/823418 , H01L21/823437 , H01L27/088 , H01L29/0676 , H01L29/16 , H01L29/42376 , H01L29/42392 , H01L29/517 , H01L29/66666 , H01L29/66742 , H01L29/775 , H01L29/7827 , H01L29/78618 , H01L29/78642 , H01L29/78651 , H01L29/78684 , H01L29/78696
摘要： Directed self-assembly (DSA) material, or di-block co-polymer, to pattern features that ultimately define a channel region a gate electrode of a vertical nanowire transistor, potentially based on one lithographic operation. In embodiments, DSA material is confined within a guide opening patterned using convention lithography. In embodiments, channel regions and gate electrode materials are aligned to edges of segregated regions within the DSA material.
摘要翻译：定向自组装（DSA）材料或二嵌段共聚物可能基于一个光刻操作来最终限定垂直纳米线晶体管的栅电极的沟道区的图案特征。在实施例中，DSA材料被限制在使用常规光刻图案化的引导开口内。在实施例中，沟道区域和栅电极材料与DSA材料内的分离区域的边缘对准。

4. 发明申请

WO2014086052A1 一种后栅工艺假栅的制造方法和后栅工艺假栅审中-公开
公开(公告)号：WO2014086052A1
公开(公告)日：2014-06-12
申请号：PCT/CN2012/086397
申请日：2012-12-12
申请人：中国科学院微电子研究所
发明人：李春龙 , 李俊峰 , 闫江 , 赵超
IPC分类号： H01L21/00 , H01L27/088
CPC分类号： H01L29/66545 , H01L21/28123 , H01L29/42364 , H01L29/513 , H01L29/518
摘要：提供了一种后栅工艺假栅的制造方法和后栅工艺假栅，该方法包括：提供半导体衬底（20）；在所述半导体衬底（20）上生长栅氧化层（22）；在所述栅氧化层（22）上淀积底层非晶硅（24）；在所述底层非晶硅（24）上淀积ONO结构硬掩膜（26）；在所述ONO结构硬掩膜（26）上淀积顶层非晶硅（28）；在所述顶层非晶硅（28）上淀积硬掩膜层（30）；在所述硬掩膜层（30）上形成光刻胶线条（32），并对所形成的光刻胶线条（32）进行微缩，使微缩后的光刻胶线条宽度小于等于22nm；以所述光刻胶线条（32）为标准，对所述硬掩膜层（30）、顶层非晶硅（28）、ONO结构硬掩膜（26）和底层非晶硅（24）进行刻蚀，并去除所述光刻胶线条（32）、硬掩膜层（30）和顶层非晶硅（28）。能精确控制栅极的关键尺寸，栅极的剖面形貌，并能有效改善栅极线条的粗糙度，保证了器件的性能及稳定性。

5. 发明申请

WO2011090571A2 SELF-ALIGNED CONTACTS 审中-公开
标题翻译：自对准联系人
公开(公告)号：WO2011090571A2
公开(公告)日：2011-07-28
申请号：PCT/US2010/059302
申请日：2010-12-07
申请人： INTEL CORPORATION , BOHR, Mark T. , GHANI, Tahir , RAHHAL-ORABI, Nadia M. , JOSHI, Subhash , STEIGERWALD, Joseph M. , KLAUS, Jason W. , HWANG, Jack , MACKIEWICZ, Ryan
发明人： BOHR, Mark T. , GHANI, Tahir , RAHHAL-ORABI, Nadia M. , JOSHI, Subhash , STEIGERWALD, Joseph M. , KLAUS, Jason W. , HWANG, Jack , MACKIEWICZ, Ryan
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336
CPC分类号： H01L21/76897 , H01L21/28123 , H01L21/28229 , H01L21/28255 , H01L21/283 , H01L21/28562 , H01L21/31105 , H01L21/76802 , H01L21/76831 , H01L21/76849 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/535 , H01L29/0847 , H01L29/16 , H01L29/42364 , H01L29/456 , H01L29/495 , H01L29/4966 , H01L29/512 , H01L29/517 , H01L29/518 , H01L29/66477 , H01L29/665 , H01L29/66545 , H01L29/6656 , H01L29/78 , H01L29/785 , H01L2029/7858 , H01L2924/0002 , H01L2924/00
摘要： A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.
摘要翻译：晶体管包括衬底，衬底上的一对间隔物，衬底上的栅介质层和一对衬垫之间，栅极电介质层上的栅电极层和一对衬垫之间的绝缘盖层栅极电极层和一对间隔物之间，以及与该对间隔物相邻的一对扩散区域。绝缘盖层形成了与栅极自对准的防蚀结构，并防止接触蚀刻暴露栅电极，从而防止栅极和接触之间的短路。绝缘体盖层能够进行自对准触点，允许对图案化限制更坚固的较宽触点的初始图案化。

6. 发明申请

WO2009099987A1 GATE PATTERNING SCHEME WITH SELF ALIGNED INDEPENDENT GATE ETCH 审中-公开
标题翻译：具有自对准独立门控阀的门控方案
公开(公告)号：WO2009099987A1
公开(公告)日：2009-08-13
申请号：PCT/US2009/032800
申请日：2009-02-02
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , HALLE, Scott , COLBURN, Matthew, E. , DYER, Thomas , DORIS, Bruce
发明人： HALLE, Scott , COLBURN, Matthew, E. , DYER, Thomas , DORIS, Bruce
IPC分类号： G03F7/20
CPC分类号： H01L21/32139 , H01L21/266 , H01L21/28123 , H01L21/823828
摘要： A method for self-aligned gate patterning is disclosed. Two masks are used to process adjacent semiconductor components, such as an nFET and pFET that are separated by a shallow trench isolation region. The mask materials are chosen to facilitate selective etching. The second mask is applied while the first mask is still present, thereby causing the second mask to self align to the first mask. This avoids the undesirable formation of a stringer over the shallow trench isolation region, thereby improving the yield of a semiconductor manufacturing operation.
摘要翻译：公开了一种用于自对准栅极图案化的方法。使用两个掩模来处理相邻的半导体部件，例如由浅沟槽隔离区分隔的nFET和pFET。选择掩模材料以便于选择性蚀刻。当第一掩模仍然存在时，施加第二掩模，从而使第二掩模与第一掩模自对准。这避免了在浅沟槽隔离区域上不期望地形成纵梁，从而提高半导体制造操作的产量。

7. 发明申请

WO2005122254A3 GATE STACK AND GATE STACK ETCH SEQUENCE FOR METAL GATE INTEGRATION 审中-公开
标题翻译：用于金属浇口整合的门盖和门盖堆焊层序列
公开(公告)号：WO2005122254A3
公开(公告)日：2006-09-14
申请号：PCT/US2005018118
申请日：2005-05-23
申请人： TEXAS INSTRUMENTS INC , VISOKAY MARK R
发明人： VISOKAY MARK R
IPC分类号： H01L29/78 , H01L21/28 , H01L21/3213 , H01L21/441 , H01L21/467 , H01L21/469 , H01L21/471 , H01L21/4763 , H01L23/58
CPC分类号： H01L21/32139 , H01L21/28123
摘要： The present invention provides, in one embodiment, a process for fabricating a metal gate stack (200) for a semiconductor device (205). The process includes depositing a metal layer (210) over a gate dielectric layer (215) located over a semiconductor substrate (220). The process further includes forming a polysilicon layer (225) over the metal layer (210) and creating a protective layer (230) over the polysilicon layer (225). The process also includes placing an inorganic anti-reflective coating (235) over the protective layer (230). Other embodiments include a metal gate stack precursor structure and a method of manufacturing an integrated circuit.
摘要翻译：本发明在一个实施例中提供一种用于制造用于半导体器件（205）的金属栅极叠层（200）的工艺。该方法包括在位于半导体衬底（220）上方的栅极介电层（215）上沉积金属层（210）。该方法还包括在金属层（210）上形成多晶硅层（225），并在多晶硅层（225）上形成保护层（230）。该方法还包括将无机抗反射涂层（235）放置在保护层（230）上。其他实施例包括金属栅极堆叠前体结构和制造集成电路的方法。

8. 发明申请

WO2006058332A2 REDUCED CHANNEL PITCH IN SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件中的减少通道栅极
公开(公告)号：WO2006058332A2
公开(公告)日：2006-06-01
申请号：PCT/US2005/043115
申请日：2005-11-29
申请人： TEXAS INSTRUMENTS INCORPORATED , VENUGOPAL, Ramesh , WASSHUBER, Christoph
发明人： VENUGOPAL, Ramesh , WASSHUBER, Christoph
IPC分类号： H01L29/06 , H01L21/467
CPC分类号： H01L21/28123 , H01L29/045 , H01L29/0657 , H01L29/1037 , H01L29/4236 , H01L29/78 , H01L29/78696 , H01L29/808 , H01L29/8086
摘要： A method for multiplying the pitch of a semiconductor device is disclosed. The method includes forming a patterned mask layer on a first layer, where the patterned mask layer has a first line width. The first layer can then be etched to form a first plurality of sloped sidewalls. After removing a portion of the patterned mask so that the patterned mask layer has a second line width less than the first line width, the first layer can be etched again to form a second plurality of sloped sidewalls. The patterned mask layer can then be removed. The first layer can be etched again to form a third plurality of sloped sidewalls. The first plurality of sloped sidewalls, the second plurality of sloped sidewalls, and the third plurality of sloped sidewalls can form an array of parallel triangular channels. In one implementation, the channels are formed in the fabrication of a triangular wire channel MOSFET (300), including a plurality of parallel triangular wire channels (325), a buried oxide layer (310), a gate oxide (360), and a gate (375).
摘要翻译：公开了一种用于乘以半导体器件的间距的方法。该方法包括在第一层上形成图案化掩模层，其中图案化掩模层具有第一线宽度。然后可以蚀刻第一层以形成第一多个倾斜的侧壁。在去除图案化掩模的一部分以使得图案化掩模层具有小于第一线宽度的第二线宽度之后，可以再次蚀刻第一层以形成第二多个倾斜侧壁。然后可以去除图案化的掩模层。可以再次蚀刻第一层以形成第三多个倾斜的侧壁。第一多个倾斜侧壁，第二多个倾斜侧壁和第三多个倾斜侧壁可以形成平行三角形通道的阵列。在一个实施方案中，通道形成在三角形线通道MOSFET（300）的制造中，该三角形线通道MOSFET（300）包括多个平行的三角形线通道（325），掩埋氧化物层（310），栅极氧化物（360）和门（375）。

9. 发明申请

WO2005117089A2 DECOUPLED COMPLEMENTARY MASK PATTERNING TRANSFER METHOD 审中-公开
标题翻译：解码补码掩码传输方法
公开(公告)号：WO2005117089A2
公开(公告)日：2005-12-08
申请号：PCT/US2005/013077
申请日：2005-04-18
申请人： FREESCALE SEMICONDUCTOR, INC. , STEPHENS, Tab A. , FU, Chong-Cheng , KING, Charles F.
发明人： STEPHENS, Tab A. , FU, Chong-Cheng , KING, Charles F.
IPC分类号： H01L21/3205
CPC分类号： H01L21/32139 , H01L21/28123
摘要： A patterning method allows for separate transfer of a complementary reticle set. In one embodiment, for example, the method includes etching a phase shift mask (PSM) [112], then etching a cut mask for a cPSM mask (110). Moreover, a decoupled complementary mask patterning transfer method includes two separate and decoupled mask patterning steps which form combined patterns through the use of partial image transfers into an intermediate hard mask (112) prior to final wafer patterning. The intermediate (112) and final hard mask (110) materials are chosen to prevent image transfer into an underlying substrate (102) or wafer prior to the final etch process.
摘要翻译：图案化方法允许互补掩模版集合的单独转移。在一个实施例中，例如，该方法包括蚀刻相移掩模（PSM）[112]，然后蚀刻用于cPSM掩模（110）的切割掩模。此外，解耦互补掩模图案转印方法包括两个单独的和去耦的掩模图案化步骤，其在最终的晶片图案化之前通过使用部分图像转移到中间硬掩模（112）中形成组合图案。选择中间体（112）和最终硬掩模（110）材料以防止在最终蚀刻工艺之前图像转移到下面的基底（102）或晶片中。

10. 发明申请

WO2005057663A2 METHOD AND APPARATUS FOR FABRICATION OF METAL-OXIDE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES 审中-公开
标题翻译：金属氧化物半导体集成电路器件的制造方法和装置
公开(公告)号：WO2005057663A2
公开(公告)日：2005-06-23
申请号：PCT/IB2004/003992
申请日：2004-12-03
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SALVETTI, Frédéric , ROBILLIART, Etienne , DRAY, Alexandre , WACQUANT, François , LENOBLE, Damien , PALLA, Ramiro
发明人： SALVETTI, Frédéric , ROBILLIART, Etienne , DRAY, Alexandre , WACQUANT, François , LENOBLE, Damien , PALLA, Ramiro
IPC分类号： H01L29/78
CPC分类号： H01L29/7833 , H01L21/265 , H01L21/28123 , H01L29/66545 , H01L29/6659
摘要： A method of forming a semiconductor device, the method comprising sequentially forming on a semiconductor substrate (10), a gate structure (14) including a gate electrode layer (15) forming an upper surface of said gate structure, performing heavy impurity doping in portions (126) of said semiconductor substrate (10) not covered by said gate structure (14) to partially form source and drain regions of said semiconductor device, removing in a single step a first layer of substantially uniform thickness from the upper surface and sidewalls of said gate structure (14), performing light impurity doping in portions (124) of said semiconductor substrate (10) not covered by said gate structure (14) to complete said source and drain regions of said semiconductor device, removing in a single step a second layer of substantially uniform thickness from the upper surface and sidewalls of said gate structure (14), forming a spacer layer (125) on the sidewalls of said gate structure (14) and forming a silicide contact (28) on the upper surface of said gate structure (14).
摘要翻译：一种形成半导体器件的方法，所述方法包括在半导体衬底（10）上依次形成栅极结构（14），栅极结构（14）包括形成所述栅极结构的上表面的栅电极层（15），部分地进行重杂质掺杂（14）的不被所述半导体衬底（10）覆盖的部分（126），以部分地形成所述半导体器件的源极和漏极区域，从而从单个步骤中去除基本均匀厚度的第一层，所述栅极结构（14），在未被所述栅极结构（14）覆盖的所述半导体衬底（10）的部分（124）中进行光杂质掺杂以完成所述半导体器件的所述源极和漏极区域，在单个步骤中去除从所述栅极结构（14）的上表面和侧壁的厚度基本均匀的第二层，在所述栅极结构（14）的侧壁上形成间隔层（125）并形成在所述栅极结构（14）的上表面上的硅化物接触（28）。

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