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1. 发明申请

WO2019095924A1 一种利用极化掺杂制备增强型GaN基晶体管的方法审中-公开
公开(公告)号：WO2019095924A1
公开(公告)日：2019-05-23
申请号：PCT/CN2018/110708
申请日：2018-10-17
申请人：厦门市三安集成电路有限公司
发明人：房育涛 , 叶念慈
IPC分类号： H01L21/335
CPC分类号： H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/7786
摘要：本发明公开了一种通过极化掺杂的方法制备增强型GaN基晶体管的方法。利用AlN和GaN 的自发极化强度之间存在较大的差别，可以通过组分渐变Al x Ga 1-x N实现极化掺杂获得P型Al x Ga 1-x N层。在GaN基材料外延生长Al组分逐渐减小的P-型Al x Ga 1-x N层，然后在P-型Al x Ga 1-x N层上生长Al x Ga 1-x N层，Al x Ga 1-x N层为Al组分x从0%-10%增加到15%-35%的组分渐变层或x为15%-35%的组分固定层，再制作与Al x Ga 1-x N层形成欧姆接触的源、漏极以及与P-型Al x Ga 1-x N层形成肖特基接触的栅极。通过改变P-型AlxGa 1-x N的组分厚度可以调节器件开启电压，通过改变Al x Ga 1-x N层的厚度和组分可以调节导通电阻，从而获得低导通电阻高开启电压的增强型GaN基晶体管。制作方法简单，无特殊工艺要求，可控性强。

2. 发明申请

WO2019066995A1 GROUP III-NITRIDE (III-N) DEVICES WITH IMPROVED RF PERFORMANCE AND THEIR METHODS OF FABRICATION 审中-公开
公开(公告)号：WO2019066995A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/054679
申请日：2017-09-30
申请人： INTEL CORPORATION
发明人： RADOSAVLJEVIC, Marko , DASGUPTA, Sansaptak , THEN, Han Wui , BAN, Ibrahim , FISCHER, Paul B.
IPC分类号： H01L29/778 , H01L29/49 , H01L29/51
CPC分类号： H01L29/7786 , H01L29/0657 , H01L29/0847 , H01L29/2003 , H01L29/66462
摘要： A device including a III-N material is described. The device includes a transistor structure having a first layer including a first group III-nitride (III-N) material, a polarization charge inducing layer above the first layer, the polarization charge inducing layer including a second III-N material, a gate electrode above the polarization charge inducing layer and a source structure and a drain structure on opposite sides of the gate electrode. The device further includes a plurality of peripheral structures adjacent to transistor structure, where each of the peripheral structure includes the first layer, but lacks the polarization charge inducing layer, an insulating layer above the peripheral structure and the transistor structure, wherein the insulating layer includes a first dielectric material. A metallization structure, above the peripheral structure, is coupled to the transistor structure.

3. 发明申请

WO2019066973A1 GROUP III-NITRIDE (III-N) DEVICES WITH REDUCED CONTACT RESISTANCE AND THEIR METHODS OF FABRICATION 审中-公开
公开(公告)号：WO2019066973A1
公开(公告)日：2019-04-04
申请号：PCT/US2017/054631
申请日：2017-09-29
申请人： INTEL CORPORATION
发明人： RADOSAVLJEVIC, Marko , THEN, Han Wui , DASGUPTA, Sansaptak
IPC分类号： H01L29/778 , H01L29/51 , H01L29/49
CPC分类号： H01L29/7786 , H01L29/0847 , H01L29/2003 , H01L29/201 , H01L29/66462
摘要： A device including a III-N material is described. In an example, a device includes a first layer including a first group III-nitride (III-N) material and a polarization charge inducing layer, including a second III-N material, above the first layer. 5 The device further includes a gate electrode above the polarization charge inducing layer and a source structure and a drain structure on opposite sides of the gate electrode. The source structure and the drain structure both include a first portion adjacent to the first layer and a second portion above the first portion, the first portion includes a third III-N material with an impurity dopant, and the second portion 10 includes a fourth III-N material, where the fourth III-N material includes the impurity dopant and further includes indium, where the indium content increases with distance from the first portion.

4. 发明申请

WO2019008603A1 HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) WITH RESURF JUNCTION 审中-公开
公开(公告)号：WO2019008603A1
公开(公告)日：2019-01-10
申请号：PCT/IN2018/050438
申请日：2018-07-06
申请人： INDIAN INSTITUTE OF SCIENCE
发明人： SOMAN, Rohith , SONI, Ankit , SHRIVASTAVA, Mayank , RAGHAVAN, Srinivasan , BHAT, Navakant
IPC分类号： H01L29/772 , H01L29/15
CPC分类号： H01L29/7786 , H01L29/063 , H01L29/1066 , H01L29/1087 , H01L29/2003 , H01L29/402 , H01L29/4236
摘要： The present subject matter provides a High Electron Mobility Transistor (HEMT) comprising a reduced surface field (RESURF) junction. The HEMT comprises a source electrode at a first end and a drain electrode at a second end. A gate electrode is provided between the source electrode and the drain electrode. A reduced surface field (RESURF) junction extends from the first end to the second end. The gate electrode is provided above the RESURF junction. A buried channel layer is formed in the RESURF junction on application of a positive voltage at the gate electrode. The RESURF junction comprises an n-type Gallium nitride (GaN) layer and a p-type GaN layer. The n-type GaN layer is provided between the p-type GaN layer and the gate electrode.

5. 发明申请

WO2019005031A1 N-POLAR GROUP III-NITRIDE HETEROJUNCTION DIODES 审中-公开
公开(公告)号：WO2019005031A1
公开(公告)日：2019-01-03
申请号：PCT/US2017/039699
申请日：2017-06-28
申请人： INTEL CORPORATION
发明人： THEN, Han Wui , DASGUPTA, Sansaptak , RADOSAVLJEVIC, Marko
IPC分类号： H01L29/66 , H01L29/861 , H01L21/28
CPC分类号： H01L29/7786 , H01L21/28575 , H01L21/28581 , H01L27/0255 , H01L29/045 , H01L29/0847 , H01L29/2003 , H01L29/205 , H01L29/4236 , H01L29/872
摘要： Diodes employing N-polar Group III-Nitride heterostructures that may provide low on-resistance for a given diode footprint. An N-polar III-N heterostructure may include a first layer of III-N material over an N-face of a second layer of III-N material. Through control of the III-N material composition of the first and second layers, a two-dimensional charge carrier sheet (e.g., 2D electron gas) may be induced within the first layer. With N-polarity, a rectifying contact and a non-rectifying contact may each access the 2D charge carrier sheet without a patterning or recessing of the first III-N material layer.

6. 发明申请

WO2018063397A1 GATE TRENCH PRECISION RESISTORS WITH HIGH-K RMG GAN TRANSISTOR 审中-公开
标题翻译：栅极沟槽式高精度电阻器，采用高K RMG GAN晶体管
公开(公告)号：WO2018063397A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/055015
申请日：2016-09-30
申请人： INTEL CORPORATION
发明人： THEN, Han Wui , DASGUPTA, Sansaptak , RADOSAVLJEVIC, Marko
IPC分类号： H01L27/24 , H01L21/28 , H01L29/417
CPC分类号： H01L27/0629 , H01L23/5228 , H01L27/0605 , H01L28/24 , H01L29/2003 , H01L29/66522 , H01L29/66568 , H01L29/7786
摘要： Embodiments of the invention include an RF switch and methods of forming an RF switch. In an embodiment, the RF switch may include a semiconductor substrate with a GaN active device layer. The RF switch may further include a transistor region formed over the substrate and an isolation region formed over the substrate. The transistor region may include a source, a drain, and a gate electrode formed between the source and the drain. In an embodiment, the gate electrode is separated from the active device layer by a gate dielectric and a workfunction metal. The isolation region may include a resistor electrically coupled to the gate electrode by the workfunction metal. In an embodiment, the resistor is formed in the same layer as the workfunction metal. In an embodiment, a resistor mask may be formed over the resistor.
摘要翻译：本发明的实施例包括RF开关和形成RF开关的方法。在一个实施例中，RF开关可以包括具有GaN有源器件层的半导体衬底。 RF开关可以进一步包括形成在衬底上方的晶体管区域和形成在衬底上方的隔离区域。晶体管区域可以包括形成在源极和漏极之间的源极，漏极和栅极电极。在一个实施例中，栅电极通过栅极电介质和功函数金属与有源器件层分离。隔离区可以包括通过功函数金属电耦合到栅电极的电阻器。在一个实施例中，电阻器形成在与功函数金属相同的层中。在一个实施例中，可以在电阻上形成电阻掩膜。

7. 发明申请

WO2018063248A1 GROUP III-V MATERIAL TRANSISTORS EMPLOYING NITRIDE-BASED DOPANT DIFFUSION BARRIER LAYER 审中-公开
标题翻译：使用氮化物基掺杂剂扩散阻挡层的III-V族材料晶体管
公开(公告)号：WO2018063248A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054461
申请日：2016-09-29
申请人： INTEL CORPORATION
发明人： MOHAPATRA, Chandra S. , KENNEL, Harold W. , GLASS, Glenn A. , RACHMADY, Willy , MURTHY, Anand S. , DEWEY, Gilbert , KAVALIEROS, Jack T. , GHANI, Tahir , METZ, Matthew V. , MA, Sean T.
IPC分类号： H01L29/78 , H01L29/66 , H01L29/417 , H01L21/8252
CPC分类号： H01L29/785 , H01L21/823412 , H01L21/823431 , H01L21/8252 , H01L27/0886 , H01L27/0924 , H01L29/0673 , H01L29/1033 , H01L29/16 , H01L29/20 , H01L29/2003 , H01L29/26 , H01L29/42376 , H01L29/42392 , H01L29/66 , H01L29/66469 , H01L29/66545 , H01L29/66795 , H01L29/775 , H01L29/78696
摘要： Techniques are disclosed for forming group III-V material transistors employing nitride-based dopant diffusion barrier layers. The techniques can include growing the dilute nitride-based barrier layer as a relatively thin layer of III-V material in the sub-channel (or sub-fin) region of a transistor, near the substrate/III-V material interface, for example. Such a nitride-based barrier layer can be used to trap atoms from the substrate at vacancy sites within the III-V material. Therefore, the barrier layer can arrest substrate atoms from diffusing in an undesired manner by protecting the sub-channel layer from being unintentionally doped due to subsequent processing in the transistor fabrication. In addition, by forming the barrier layer pseudomorphically, the lattice mismatch of the barrier layer with the sub-channel layer in the heterojunction stack becomes insignificant. In some embodiments, the group III-V alloyed with nitrogen (N) material may include an N concentration of less than 5, 2, or 1.5 percent.
摘要翻译：公开了用于形成采用氮化物基掺杂剂扩散阻挡层的III-V族材料晶体管的技术。该技术可以包括例如在衬底/ III-V材料界面附近的晶体管的子沟道（或子鳍状物）区域中将稀氮化物基阻挡层生长为相对较薄的III-V材料层。这种基于氮化物的阻挡层可用于在III-V材料内的空位处捕获来自衬底的原子。因此，由于晶体管制造中的后续处理，通过保护子沟道层免于无意掺杂，阻挡层可阻止衬底原子以不希望的方式扩散。另外，通过伪势垒地形成势垒层，势垒层与异质结叠层中的子沟道层的晶格失配变得不明显。在一些实施方案中，与氮（N）材料合金化的III-V族可以包含小于5,2或1.5％的N浓度。

8. 发明申请

WO2018063160A1 METHODS AND APPARATUS TO FORM GaN-BASED TRANSISTORS DURING BACK-END-OF-LINE PROCESSING 审中-公开
标题翻译：用于在线后处理期间形成GaN基晶体管的方法和设备
公开(公告)号：WO2018063160A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/053976
申请日：2016-09-27
申请人： INTEL CORPORATION
发明人： RADOSAVLJEVIC, Marko , DASGUPTA, Sansaptak , THEN, Han Wui
IPC分类号： H01L29/778 , H01L27/092 , H01L21/8238
CPC分类号： H01L29/2003 , H01L21/76898 , H01L21/823807 , H01L21/8258 , H01L23/481 , H01L27/0605 , H01L27/0688 , H01L27/092 , H01L27/1207 , H01L27/1218 , H01L27/1225
摘要： Methods and apparatus to form GaN-based transistors during backend-of-line processing are disclosed. An example integrated circuit includes a first transistor formed on a first semiconductor substrate. The example integrated circuit includes a dielectric material formed on the first semiconductor substrate. The dielectric material extends over the first transistor. The example integrated circuit further includes a second semiconductor substrate formed on the dielectric material. The example integrated circuit also includes a second transistor formed on the second semiconductor substrate.
摘要翻译：公开了在后端处理期间形成GaN基晶体管的方法和设备。示例集成电路包括形成在第一半导体衬底上的第一晶体管。示例集成电路包括形成在第一半导体衬底上的电介质材料。介电材料在第一晶体管上方延伸。示例集成电路进一步包括形成在电介质材料上的第二半导体衬底。示例集成电路还包括形成在第二半导体衬底上的第二晶体管。

9. 发明申请

WO2017199110A1 MICROELECTRONIC SENSOR FOR BIOMETRIC AUTHENTICATION 审中-公开
标题翻译：用于生物识别的微电子传感器
公开(公告)号：WO2017199110A1
公开(公告)日：2017-11-23
申请号：PCT/IB2017/051884
申请日：2017-04-03
申请人： RG INNOVATIONS PTE LTD
发明人： RAM, Ayal , LICHTENSTEIN, Amir
IPC分类号： A61B5/00 , H01L27/00 , H01L29/00 , G01N27/414
CPC分类号： G01N27/414 , H01L29/0657 , H01L29/0843 , H01L29/2003 , H01L29/41766 , H01L29/7786
摘要： In some embodiments, a microelectronic sensor includes an open-gate pseudo-conductive high-electron mobility transistor and used for biometric authentication of a user. The transistor comprises a substrate, on which a multilayer hetero-junction structure is deposited. This hetero-junction structure comprises a buffer layer and a barrier layer, both grown from III-V single-crystalline or polycrystalline semiconductor materials. A two- dimensional electron gas (2DEG) conducting channel is formed at the interface between the buffer and barrier layers and provides electron current in the system between source and drain electrodes. The source and drain contacts, which maybe either ohmic or non- ohmic (capacitively-coupled), are connected to the formed 2DEG channel and to electrical metallizations, the latter are placed on top of the transistor and connect it to the sensor system. The metal gate electrode is placed between the source and drain areas on or above the barrier layer, which may be recessed or grown to a specific thickness. An optional dielectric layer is deposited on top of the barrier layer.
摘要翻译：在一些实施例中，微电子传感器包括开栅伪导电高电子迁移率晶体管并且用于用户的生物测定认证。晶体管包括衬底，在衬底上沉积多层异质结结构。该异质结结构包括均由III-V单晶或多晶半导体材料生长的缓冲层和阻挡层。在缓冲层和阻挡层之间的界面处形成二维电子气（2DEG）传导沟道，并且在源极和漏极之间的系统中提供电子电流。可以是欧姆或非欧姆（电容耦合）的源极和漏极触点连接到形成的2DEG沟道和电气金属，后者放置在晶体管的顶部并将其连接到传感器系统。金属栅极电极放置在阻挡层上或上方的源极和漏极区域之间，其可以凹陷或生长至特定厚度。可选的电介质层沉积在阻挡层的顶部。

10. 发明申请

WO2017171755A1 WAFER EDGE PROTECTION FOR CRACK-FREE MATERIAL GROWTH 审中-公开
标题翻译： WAFER EDGE保护无裂纹材料增长
公开(公告)号：WO2017171755A1
公开(公告)日：2017-10-05
申请号：PCT/US2016/025021
申请日：2016-03-30
申请人： INTEL CORPORATION
发明人： GARDNER, Sanaz K. , DASGUPTA, Sansaptak , RADOSAVLJEVIC, Marko , THEN, Han Wui , SUNG, Seung Hoon
IPC分类号： H01L21/768 , H01L29/778
CPC分类号： H01L21/768 , H01L21/02381 , H01L21/02433 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L21/02639 , H01L23/3185 , H01L23/562 , H01L29/2003 , H01L29/7786 , H01L33/20 , H01L33/44
摘要： A method of fabricating a wafer is disclosed. The method includes forming a protective layer on a device side and a non-device side of a substrate of the wafer. The method further includes removing the protective layer from a center portion of the device side of the substrate while retaining the protective layer in an edge portion of the substrate. The method also includes forming a semiconductor layer in the center portion of the device side of the substrate while the protective layer is in the edge portion of the substrate.
摘要翻译：公开了一种制造晶片的方法。该方法包括在晶片的衬底的器件侧和非器件侧上形成保护层。该方法还包括从基板的器件侧的中心部分去除保护层，同时将保护层保持在基板的边缘部分中。该方法还包括在保护层位于衬底的边缘部分的同时在衬底的器件侧的中心部分中形成半导体层。

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