专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2006121874A3 MEMORY DEVICE AND METHOD HAVING A DATA BYPASS PATH TO ALLOW RAPID TESTING AND CALIBRATION 审中-公开
标题翻译：具有数据旁路的存储器件和方法允许快速测试和校准
公开(公告)号：WO2006121874A3
公开(公告)日：2007-08-02
申请号：PCT/US2006017439
申请日：2006-05-04
申请人： MICRON TECHNOLOGY INC , JOHNSON JAMES B , MANNING TROY A
发明人： JOHNSON JAMES B , MANNING TROY A
IPC分类号： G01R31/26
CPC分类号： G11C7/1039 , G11C7/1048 , G11C11/401 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50012 , G11C2207/105 , G11C2207/2254
摘要： A synchronous dynamic random access memory ("SDRAM") device (100) includes a pipelined write data path coupling data from a data bus to a DRAM array (122), and a pipelined read data path coupling read data from the array ((122) to the data bus. The SDRAM device also includes a bypass path allowing the write data in the write data path to be coupled directly to the read data path without firs being stored in the DRAM array. The write data are preferably coupled through the write data path by issuing a write command to the DRAM device, and the read data are preferably coupled through the read data path by issuing a read command to the DRAM device. The memory array is inhibited from responding to these commands so that the write data are not stored in the array, and read data from the array are not coupled to the read data path.
摘要翻译：同步动态随机存取存储器（“SDRAM”）装置（100）包括将从数据总线到DRAM阵列（122）的数据耦合的流水线写入数据路径，以及将读取数据从阵列（（122 ）SDRAM装置还包括旁路路径，允许写入数据路径中的写入数据直接耦合到读取数据路径，而没有保存在DRAM阵列中的数据，写入数据优选地通过写入通过向DRAM设备发出写入命令，读取数据优选地通过读取数据路径耦合到DRAM设备，读取命令被禁止响应于这些命令，使得写入数据是不存储在阵列中，并且从阵列读取数据不会耦合到读取的数据路径。

2. 发明申请

WO2012094481A3 MEMORY ADDRESS TRANSLATION 审中-公开
标题翻译：存储地址翻译
公开(公告)号：WO2012094481A3
公开(公告)日：2012-09-20
申请号：PCT/US2012020312
申请日：2012-01-05
申请人： MICRON TECHNOLOGY INC , MANNING TROY A , CULLEY MARTIN L , LARSEN TROY D
发明人： MANNING TROY A , CULLEY MARTIN L , LARSEN TROY D
IPC分类号： G06F12/06 , G06F12/10
CPC分类号： G06F12/1045 , G06F12/0246 , G06F12/0292 , G06F12/1009 , G06F12/1027 , G06F2212/1004 , G06F2212/7201 , Y02B60/1225 , Y02D10/13
摘要： The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.
摘要翻译：本公开包括用于存储器地址转换的装置，系统和方法。一个或多个实施例包括存储器阵列和耦合到阵列的控制器。阵列包括具有多个记录的第一表，其中每个记录包括多个条目，其中每个条目包括对应于阵列中存储的数据段的物理地址和逻辑地址。控制器包括具有多个记录的第二表，其中每个记录包括多个条目，其中每个条目包括对应于第一表中的记录的物理地址和逻辑地址。控制器还包括具有多个记录的第三表，其中每个记录包括多个条目，其中每个条目包括对应于第二表中的记录的物理地址和逻辑地址。

3. 发明申请

WO2010016879A8 ROW MASK ADDRESSING 审中-公开
公开(公告)号：WO2010016879A8
公开(公告)日：2010-09-16
申请号：PCT/US2009004443
申请日：2009-08-03
申请人： MICRON TECHNOLOGY INC , MANNING TROY A
发明人： MANNING TROY A
IPC分类号： G11C8/00 , G11C8/08 , G11C8/10 , G11C8/18
CPC分类号： G11C8/10 , G11C11/4087
摘要： Electronic apparatus, systems, and methods may operate structures to access a portion of a row of a memory array without accessing the entire row. Additional apparatus, systems, and methods are disclosed.
摘要翻译：电子设备，系统和方法可以操作结构以访问存储器阵列的一部分行而不访问整个行。公开了另外的设备，系统和方法。

4. 发明申请

WO2007005218B1 APPARATUS AND METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY 审中-公开
标题翻译：修复半导体存储器的装置和方法
公开(公告)号：WO2007005218B1
公开(公告)日：2007-04-26
申请号：PCT/US2006023219
申请日：2006-06-14
申请人： MICRON TECHNOLOGY INC , MARTIN CHRIS G , MANNING TROY A , KEETH BRENT
发明人： MARTIN CHRIS G , MANNING TROY A , KEETH BRENT
IPC分类号： G11C29/00
CPC分类号： G11C17/165 , G11C29/4401 , G11C29/789 , G11C29/802 , G11C29/808 , G11C2029/4402
摘要： An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.
摘要翻译：一种用于修复半导体存储器件的装置和方法包括第一存储器单元阵列，第一冗余单元阵列和修复电路，该修复电路被配置为非易失性地将指定至少一个故障存储器单元的第一地址存储在第一存储器单元阵列中。第一易失性高速缓存存储对应于指定至少一个有缺陷的存储单元的第一地址的第一高速缓存地址。修复电路将指定第一存储单元阵列的至少一个故障存储单元的第一地址分配给第一易失性缓存。当第一存储器访问对应于第一高速缓存地址时，匹配电路将来自第一冗余单元阵列的至少一个冗余存储器单元替换为第一存储器单元阵列中的至少一个有缺陷存储器单元。

5. 发明申请

WO2004001846A3 METHOD AND STRUCTURES FOR REDUCED PARASITIC CAPACITANCE IN INTEGRATED CIRCUIT METALLIZATIONS 审中-公开
标题翻译：集成电路金属化中降低PARASIIC电容的方法与结构
公开(公告)号：WO2004001846A3
公开(公告)日：2004-10-28
申请号：PCT/US0321029
申请日：2003-06-18
申请人： MICRON TECHNOLOGY INC , BATRA SHUBNEESH , CHAINE MICHAEL D , KEETH BRENT , AKRAM SALMAN , MANNING TROY A , JOHNSON BRIAN , MARTIN CHRIS G , MERRITT TODD A , SMITH ERIC J
发明人： BATRA SHUBNEESH , CHAINE MICHAEL D , KEETH BRENT , AKRAM SALMAN , MANNING TROY A , JOHNSON BRIAN , MARTIN CHRIS G , MERRITT TODD A , SMITH ERIC J
IPC分类号： H01L23/485 , H01L23/522 , H01L23/64
CPC分类号： H01L24/05 , H01L23/5222 , H01L24/03 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01061 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/30105
摘要： A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels (M1, M2, M3, etc) is described. The method comprises forming a bond pad (20) at least partially exposed at the top surface of the integrated circuit, forming a metal pad (22) on the metal level (42) below the bond pad (20) and forming an underlying metal pad (26b) on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads (22, 26b) to the area of the bond pad (20) is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.
摘要翻译：描述了一种降低具有三个或更多个金属水平（M1，M2，M3等）的集成电路中的寄生电容的方法。该方法包括形成至少部分地暴露在集成电路的顶表面处的接合焊盘（20），在接合焊盘（20）下方的金属层（42）上形成金属焊盘（22），并形成下面的金属焊盘（26b）在所述一个或多个下层金属层中的每一个上。在所示实施例中，下面的金属焊盘（22,26b）中的至少一个的面积与焊盘（20）的面积之比小于30％。寄生电容因此大大降低，信号传播速度提高。

6. 发明申请

WO2012166723A2 DATA PROTECTION ACROSS MULTIPLE MEMORY BLOCKS 审中-公开
标题翻译：数据保护通过多个存储块
公开(公告)号：WO2012166723A2
公开(公告)日：2012-12-06
申请号：PCT/US2012039846
申请日：2012-05-29
申请人： MICRON TECHNOLOGY INC , RATNAM SAMPATH K , LARSEN TROY D , RIVERS DOYLE W , MANNING TROY A , CULLEY MARTIN L
发明人： RATNAM SAMPATH K , LARSEN TROY D , RIVERS DOYLE W , MANNING TROY A , CULLEY MARTIN L
IPC分类号： G06F12/16 , G11C7/24
CPC分类号： G06F11/1068 , G06F11/10 , G06F11/108 , G11C11/5628 , G11C16/0483
摘要： Data protection across multiple memory blocks can include writing a first portion of a codeword in a first location of a first memory block and writing a second portion of the codeword in a second location of a second memory block. The second location can be different than the first location with respect to the second and the first memory blocks.
摘要翻译：跨越多个存储器块的数据保护可以包括将码字的第一部分写入第一存储器块的第一位置，并将码字的第二部分写入第二存储器块的第二位置。第二位置可以不同于第二位置和第一存储块的第一位置。

7. 发明申请

WO2012121968A2 LOGICAL ADDRESS TRANSLATION 审中-公开
标题翻译：逻辑地址翻译
公开(公告)号：WO2012121968A2
公开(公告)日：2012-09-13
申请号：PCT/US2012027265
申请日：2012-03-01
申请人： MICRON TECHNOLOGY INC , CULLEY MARTIN L , MANNING TROY A , LARSEN TROY D
发明人： CULLEY MARTIN L , MANNING TROY A , LARSEN TROY D
IPC分类号： G06F12/02 , G06F13/14
CPC分类号： G06F3/0665 , G06F12/00 , G06F12/0246 , G06F12/0292 , G06F12/04 , G06F12/10 , G06F12/1027 , G06F12/1408 , G06F12/1475 , G06F2212/7201 , G06F2212/7202 , Y02B60/1225 , Y02D10/13
摘要： The present disclosure includes methods for logical address translation, methods for operating memory systems, and memory systems. One such method includes receiving a command associated with a LA, wherein the LA is in a particular range of LAs and translating the LA to a physical location in memory using an offset corresponding to a number of physical locations skipped when writing data associated with a range of LAs other than the particular range.
摘要翻译：本公开包括用于逻辑地址转换的方法，用于操作存储器系统的方法和存储器系统。一种这样的方法包括接收与LA相关联的命令，其中LA在LAs的特定范围内，并且使用对应于当写入与范围相关联的数据时跳过的物理位置的数量来将LA转换到存储器中的物理位置的特定范围以外的。

8. 发明申请

WO2010042496A3 STACKED DEVICE REMAPPING AND REPAIR 审中-公开
标题翻译：堆叠设备重新修复和维修
公开(公告)号：WO2010042496A3
公开(公告)日：2010-07-22
申请号：PCT/US2009059669
申请日：2009-10-06
申请人： MICRON TECHNOLOGY INC , KEETH BRENT , MARTIN CHRIS G , MANNING TROY A , JEDDELOH JOE M , COWLES TIMOTHY B , REHMEYER JIM , LABERGE PAUL A
发明人： KEETH BRENT , MARTIN CHRIS G , MANNING TROY A , JEDDELOH JOE M , COWLES TIMOTHY B , REHMEYER JIM , LABERGE PAUL A
IPC分类号： G11C8/04 , G11C8/06
CPC分类号： G06F12/08 , G06F12/10 , G11C5/025 , G11C29/04 , G11C29/18 , G11C29/76 , G11C29/78 , G11C29/808 , G11C29/812 , G11C29/883 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599
摘要： Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die.
摘要翻译：各种实施例包括具有布置在堆叠中的多个骰子的装置，系统和方法，其中有缺陷的单元可以被同一裸片上的备用单元或不同的管芯替代。

9. 发明申请

WO2015187771A3 APPARATUSES AND METHODS FOR PERFORMING AN EXCLUSIVE OR OPERATION USING SENSING CIRCUITRY 审中-公开
标题翻译：使用传感电路进行专有或操作的设备和方法
公开(公告)号：WO2015187771A3
公开(公告)日：2017-05-04
申请号：PCT/US2015033889
申请日：2015-06-03
申请人： MICRON TECHNOLOGY INC
发明人： MANNING TROY A
IPC分类号： G11C7/06 , G11C7/10
CPC分类号： G11C11/4091 , G11C7/065 , G11C7/1006 , G11C7/1012 , G11C11/4087 , G11C11/4093 , G11C11/4096 , G11C29/42
摘要： The present disclosure includes apparatuses and methods related to determining an XOR value in memory. An example method can include performing a NAND operation on a data value stored in a first memory cell and a data value stored in a second memory cell. The method can include performing an OR operation on the data values stored in the first and second memory cells. The method can include performing an AND operation on the result of the NAND operation and a result of the OR operation without transferring data from the memory array via an input/output (I/O) line.
摘要翻译：本公开包括与确定存储器中的异或值有关的设备和方法。示例方法可以包括对存储在第一存储器单元中的数据值和存储在第二存储器单元中的数据值执行NAND操作。该方法可以包括对存储在第一和第二存储器单元中的数据值执行或运算。该方法可以包括对NAND操作的结果和OR操作的结果执行AND操作，而不通过输入/输出（I / O）线传输来自存储器阵列的数据。

10. 发明申请

WO9839846A3 DELAY-LOCKED LOOP WITH BINARY-COUPLED CAPACITOR 审中-公开
标题翻译：带二元耦合电容的延迟锁定环
公开(公告)号：WO9839846A3
公开(公告)日：1998-12-03
申请号：PCT/US9804346
申请日：1998-03-05
申请人： MICRON TECHNOLOGY INC
发明人： MANNING TROY A
IPC分类号： G11C7/00 , G11C7/22 , H03K5/13 , H03L7/081
CPC分类号： G11C7/222 , G11C7/22 , H03K5/131 , H03L7/0814
摘要： A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay line to be varied. In response to an input clock signal, the variable delay line produces a delayed output clock signal that is compared at a race detection circuit to the input clock signal. If the delayed clock signal leads the input clock signal, the race detection circuit increments a counter that controls the binary-coupled capacitors. The incremented counter increases the capacitance by coupling additional capacitance to the variable delay line to delay propagation of the delayed clock signal. If the delayed clock signal lags the original clock signal, the race detection circuit decrements the counter to decrease the capacitance, thereby decreasing the delay of the variable delay line. The race detection circuit includes an arbitration circuit that detects when the delayed clock signal and the variable clock signal are substantially synchronized and disables incrementing or decrementing of the counter in response.
摘要翻译：延迟锁定环路将二进制耦合电容器并入电容器组，以沿延迟线产生可变电容。可变电容允许可变延迟线的延迟变化。响应于输入时钟信号，可变延迟线产生延迟输出时钟信号，其在竞争检测电路处与输入时钟信号进行比较。如果延迟的时钟信号超前输入时钟信号，则竞争检测电路递增控制二进制耦合电容器的计数器。递增计数器通过将附加电容耦合到可变延迟线来延迟电容，以延迟延迟时钟信号的传播。如果延迟时钟信号滞后于原始时钟信号，则竞争检测电路递减计数器以减小电容，由此减小可变延迟线的延迟。竞争检测电路包括仲裁电路，该仲裁电路检测延迟时钟信号和可变时钟信号何时基本同步并且响应于禁止计数器递增或递减。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式