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1. 发明申请

WO2017048377A1 MRAM INITIALIZATION DEVICES AND METHODS 审中-公开
标题翻译： MRAM初始化设备和方法
公开(公告)号：WO2017048377A1
公开(公告)日：2017-03-23
申请号：PCT/US2016/044703
申请日：2016-07-29
申请人： QUALCOMM INCORPORATED
发明人： SHIN, Hyunsuk , KIM, Jung Pill , KIM, Sungryul
IPC分类号： G11C29/00 , G11C7/20 , G11C11/16 , G06F12/02
CPC分类号： G11C29/76 , G06F12/0238 , G06F2212/7207 , G06F2212/7209 , G11C7/20 , G11C11/1653 , G11C29/44 , G11C29/789 , G11C29/808 , G11C29/82 , G11C29/84
摘要： A device includes a redundant region of a magnetoresistive random access memory (MRAM) array that includes first memory cells. The device includes a data region of the MRAM array that includes second memory cells. The device includes a fail address region of the MRAM array, a first row of the fail address region including validity data, wherein the validity data includes multiple validity indicators, a last row indicator, or both.
摘要翻译：一种器件包括包含第一存储器单元的磁阻随机存取存储器（MRAM）阵列的冗余区域。该装置包括包括第二存储器单元的MRAM阵列的数据区域。该设备包括MRAM阵列的故障地址区域，包括有效性数据的故障地址区域的第一行，其中有效性数据包括多个有效性指示符，最后一行指示符，或两者。

2. 发明申请

WO2016073178A2 SHARED REPAIR REGISTER FOR MEMORY REDUNDANCY 审中-公开
标题翻译：共享维修注册记忆冗余
公开(公告)号：WO2016073178A2
公开(公告)日：2016-05-12
申请号：PCT/US2015/056218
申请日：2015-10-19
申请人： QUALCOMM INCORPORATED
发明人： BOYNAPALLI, Venugopal , ZAFAR, Bilal
IPC分类号： G11C29/00
CPC分类号： G11C29/70 , G11C11/419 , G11C29/765 , G11C29/808 , G11C29/886
摘要： A cross-bar switch is provided that enables each master from a plurality of masters to read from and write to selected memories from an array of memories. A logic circuit controls the cross-bar switch so that redundancy for the memories is provided by a shared redundancy storage element.
摘要翻译：提供了一种横杆开关，其使得来自多个主机的每个主机能够从存储器阵列中读取和写入所选择的存储器。逻辑电路控制交叉开关，使得存储器的冗余由共享冗余存储元件提供。

3. 发明申请

WO2013115790A1 SINGLE AND DOUBLE CHIP SPARE 审中-公开
标题翻译：单和双芯片备件
公开(公告)号：WO2013115790A1
公开(公告)日：2013-08-08
申请号：PCT/US2012/023313
申请日：2012-01-31
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY L.P. , GOSTIN, Gary , HANDGEN, Erin
发明人： GOSTIN, Gary , HANDGEN, Erin
IPC分类号： G06F13/16 , G06F11/07 , G06F11/10
CPC分类号： G06F11/1666 , G06F3/0619 , G06F3/0658 , G06F3/0683 , G06F11/1064 , G06F11/1068 , G11C29/808
摘要： Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be 'accessed in both single and double chip spare modes.
摘要翻译：提供了克服内存故障的技术。存储器的一部分可以以单个芯片备用模式工作。当在存储器的该部分中检测到单个芯片中的错误时，存储器的该部分的区域可被转换为以双芯片备用模式工作。存储器可以在单芯片和双芯片备用模式下访问。

4. 发明申请

WO2010042496A3 STACKED DEVICE REMAPPING AND REPAIR 审中-公开
标题翻译：堆叠设备重新修复和维修
公开(公告)号：WO2010042496A3
公开(公告)日：2010-07-22
申请号：PCT/US2009059669
申请日：2009-10-06
申请人： MICRON TECHNOLOGY INC , KEETH BRENT , MARTIN CHRIS G , MANNING TROY A , JEDDELOH JOE M , COWLES TIMOTHY B , REHMEYER JIM , LABERGE PAUL A
发明人： KEETH BRENT , MARTIN CHRIS G , MANNING TROY A , JEDDELOH JOE M , COWLES TIMOTHY B , REHMEYER JIM , LABERGE PAUL A
IPC分类号： G11C8/04 , G11C8/06
CPC分类号： G06F12/08 , G06F12/10 , G11C5/025 , G11C29/04 , G11C29/18 , G11C29/76 , G11C29/78 , G11C29/808 , G11C29/812 , G11C29/883 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599
摘要： Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die.
摘要翻译：各种实施例包括具有布置在堆叠中的多个骰子的装置，系统和方法，其中有缺陷的单元可以被同一裸片上的备用单元或不同的管芯替代。

5. 发明申请

WO2010042496A2 STACKED DEVICE REMAPPING AND REPAIR 审中-公开
标题翻译：堆叠设备重新包装和维修
公开(公告)号：WO2010042496A2
公开(公告)日：2010-04-15
申请号：PCT/US2009/059669
申请日：2009-10-06
申请人： MICRON TECHNOLOGY, INC. , KEETH, Brent , MARTIN, Chris G. , MANNING, Troy A. , JEDDELOH, Joe M. , COWLES, Timothy B. , REHMEYER, Jim , LABERGE, Paul A.
发明人： KEETH, Brent , MARTIN, Chris G. , MANNING, Troy A. , JEDDELOH, Joe M. , COWLES, Timothy B. , REHMEYER, Jim , LABERGE, Paul A.
IPC分类号： G11C8/04 , G11C8/06
CPC分类号： G06F12/08 , G06F12/10 , G11C5/025 , G11C29/04 , G11C29/18 , G11C29/76 , G11C29/78 , G11C29/808 , G11C29/812 , G11C29/883 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die.
摘要翻译：各种实施例包括具有以堆叠方式布置的多个管芯的设备，系统和方法，其中有缺陷的单元可以被同一管芯或不同管芯上的备用单元替换。

6. 发明申请

WO2006121529A2 METHOD AND APPARATUS FOR INCORPORATING BLOCK REDUNDANCY IN A MEMORY ARRAY 审中-公开
标题翻译：在存储阵列中加入块冗余的方法和装置
公开(公告)号：WO2006121529A2
公开(公告)日：2006-11-16
申请号：PCT/US2006/012107
申请日：2006-03-31
申请人： SANDISK 3D LLC , FASOLI, Luca, G. , SCHEUERLEIN, Roy, E.
发明人： FASOLI, Luca, G. , SCHEUERLEIN, Roy, E.
IPC分类号： G11C29/00
CPC分类号： G11C29/808 , G11C29/76 , G11C29/804 , G11C29/816
摘要： An integrated circuit memory array includes alternating first and second types of memory blocks, each memory block including respective array lines shared with a respective array line in an adjacent memory block. The array lines of a defective block of one type are mapped into a spare block of the same type. The array lines of a first adjacent block which are shared with array lines of the defective block, and the array lines of a second adjacent block which are shared with array lines of the defective block, are mapped into a second spare block of the other type, thereby mapping the defective block and portions of both adjacent blocks into just two spare blocks.
摘要翻译：集成电路存储器阵列包括交替的第一和第二类型的存储块，每个存储块包括与相邻存储器块中的相应阵列线共享的相应阵列线。一种类型的缺陷块的阵列线被映射到相同类型的备用块。与缺陷块的阵列线共享的第一相邻块的阵列线和与缺陷块的阵列线共享的第二相邻块的阵列线被映射到另一种类型的第二备用块从而将缺陷块和两个相邻块的部分映射到仅两个备用块中。

7. 发明申请

WO2005091304A1 MEMORY DEVICE WITH REDUNDANCY HAVING COMMON ROW INTERFACE 审中-公开
标题翻译：具有通用接口的冗余存储器件
公开(公告)号：WO2005091304A1
公开(公告)日：2005-09-29
申请号：PCT/EP2005/001896
申请日：2005-02-23
申请人： INFINEON TECHNOLOGIES AG , OH, Jong-Hoon
发明人： OH, Jong-Hoon
IPC分类号： G11C29/00
CPC分类号： G11C29/808 , G11C29/842
摘要： One embodiment of the present invention provides a semiconductor memory receiving an external address including an array address and a row address. The semiconductor memory includes a memory bank having N arrays, each array having an array address and a plurality of primary rows of memory cells and a plurality of redundant rows of memory cells, a redundancy block, and N local row control blocks. The redundancy block provides a match signal having an active state when the external address matches one of a plurality of defective addresses, provides a redundant row address when the match signal has the active state, and provides a redirected array address comprising a redundant array address when the match signal has the active state and otherwise comprising the external array address. Each of the N local row control blocks is associated with a different one of the N arrays, wherein the local row control block associated with the array whose address matches the redirected array address opens a redundant row of memory cells for access based on the redundant row address when the match signal has the first state, and otherwise opens a normal row of memory cells for access based on the external row address.
摘要翻译：本发明的一个实施例提供了接收包括阵列地址和行地址的外部地址的半导体存储器。半导体存储器包括具有N个阵列的存储体，每个阵列具有阵列地址和存储器单元的多个主行和多个存储单元冗余行，冗余块和N个本地行控制块。当外部地址匹配多个缺陷地址之一时，冗余块提供具有活动状态的匹配信号，当匹配信号具有活动状态时提供冗余行地址，并且当冗余阵列地址包括冗余阵列地址时匹配信号具有活动状态，否则包括外部阵列地址。 N个本地行控制块中的每一个与N个阵列中的不同的一个相关联，其中与地址与重定向阵列地址匹配的阵列相关联的本地行控制块基于冗余行打开用于访问的冗余行存储器单元匹配信号具有第一状态时的地址，否则基于外部行地址打开用于访问的正常的存储单元行。

8. 发明申请

WO2003092012A2 FLEXIBLE REDUNDANCY FOR MEMORIES 审中-公开
标题翻译：用于记忆的灵活冗余
公开(公告)号：WO2003092012A2
公开(公告)日：2003-11-06
申请号：PCT/EP2003/004078
申请日：2003-04-17
申请人： INFINEON TECHNOLOGIES AG , ROEHR, Thomas , REHM, Norbert
发明人： ROEHR, Thomas , REHM, Norbert
IPC分类号： G11C
CPC分类号： G11C29/808 , G11C11/22
摘要： An improved redundancy scheme for a memory matrix is disclosed. The memory matrix a plurality of memory cells interconnected in first and second directions. The memory cells are grouped into memory elements. A redundant memory element having a plurality of redundant memory cells is provided. The redundant memory element is segmented into R sections in the first direction, wherein R is a whole number greater to or equal to 2. By segmenting the redundant element into R sections, it can be used to repair defects in up to R different memory elements.
摘要翻译：公开了一种用于存储器矩阵的改进的冗余方案。所述存储矩阵是在第一和第二方向上互连的多个存储单元。存储单元被分组成存储元件。提供具有多个冗余存储单元的冗余存储元件。冗余存储器元件在第一方向被分割成R部分，其中R是大于或等于2的整数。通过将冗余元件分割成R部分，其可用于修复多达R个不同存储元件的缺陷。

9. 发明申请

WO2002101749A1 METHODS AND APPARATUS FOR ANALYZING AND REPAIRING MEMORY 审中-公开
标题翻译：分析和修复记忆的方法和装置
公开(公告)号：WO2002101749A1
公开(公告)日：2002-12-19
申请号：PCT/US2002/017744
申请日：2002-06-07
申请人： MITSUBISHI ELECTRIC CORPORATION , SAUVAGEAU, Anthony, J. , MULLINS, Michael, A.
发明人： SAUVAGEAU, Anthony, J. , MULLINS, Michael, A.
IPC分类号： G11C7/00
CPC分类号： G11C29/72 , G11C29/808
摘要： Methods and apparatus for analyzing and repairing memory are presented. The method includes the step (302,304,306) of determining if failed memory cells detected in at least a portion of memory must be repaired using only one of a number of types of memory spares or may be repaired using any of the types of memory spares. Failed memory cells that must be repaired using only one of the number of types of memory spares are repeatedly repaired (308) skipping any failed memory cells that may be repaired using any of the number of types of memory spares, until either no new errors that must be repaired are repaired and no failed memory cells are skipped or memory is determined to not be repairable.
摘要翻译：介绍了分析和修复记忆体的方法和装置。该方法包括确定在至少一部分存储器中检测到的故障存储器单元是否必须仅使用多种类型的存储器备件中的一种来修复的步骤（302,304,306），或者可以使用任何类型的存储器备件进行修复。必须使用只有一种类型的内存备件修复的故障内存单元被重复修复（308）跳过任何可能使用任何数量类型的内存备件修复的故障内存单元，直到没有新的错误必须进行维修修理，并且不会跳过失败的内存单元，或将内存确定为不可修复。

10. 发明申请

WO00038066A1 INTEGRATED MEMORY WITH REDUNDANCY 审中-公开
标题翻译：冗余集成内存
公开(公告)号：WO00038066A1
公开(公告)日：2000-06-29
申请号：PCT/DE1999/003905
申请日：1999-12-07
IPC分类号： G11C11/22 , G11C29/00 , G11C29/04 , G06F11/20
CPC分类号： G11C29/808 , G11C29/846
摘要： An integrated memory with two read amplifiers (sAi) and two first redundant read amplifiers (RSA0..3). Said memory also comprises normal bit lines (BL) that merge into at least two individually addressable slots (CL), whereby at least one of said lines is connected to one of the normal read amplifiers from one of said slots. The inventive memory also comprises first redundant bit lines (RBL1) that merge into at least one individually addressable redundant slot (RCL), whereby at least one of said lines is connected to one of the redundant amplifiers (RSA0..3). The first redundant amplifier (RSA0..3) and the redundant slot (RCL) pertaining thereto are provided as replacements for the two normal read amplifiers (Sai) and one of the normal slots (CL).
摘要翻译：该集成的存储器具有两个正常读出放大器（SAI）和两个第一冗余读出放大器（RSA0..3）。此外，它具有至少两个单独可寻址的正常柱（CL）其中在每种情况下各柱正常的至少一个被连接到该正常的读出放大器的一个骨料正常位线（BL）。此外，它有一个可单独寻址的冗余列（RCL）合并第一冗余位线（RBL1），其每一个的每个的至少一个与所述冗余读出放大器（RSA0..3）中的一个连接。提供了用于替换两个正常读出放大器（SAI）和正常的一列（CL）设置的第一冗余读出放大器（RSA0..3）和其冗余列（RCL）。

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