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1. 发明申请

WO2010042496A3 STACKED DEVICE REMAPPING AND REPAIR 审中-公开
标题翻译：堆叠设备重新修复和维修
公开(公告)号：WO2010042496A3
公开(公告)日：2010-07-22
申请号：PCT/US2009059669
申请日：2009-10-06
申请人： MICRON TECHNOLOGY INC , KEETH BRENT , MARTIN CHRIS G , MANNING TROY A , JEDDELOH JOE M , COWLES TIMOTHY B , REHMEYER JIM , LABERGE PAUL A
发明人： KEETH BRENT , MARTIN CHRIS G , MANNING TROY A , JEDDELOH JOE M , COWLES TIMOTHY B , REHMEYER JIM , LABERGE PAUL A
IPC分类号： G11C8/04 , G11C8/06
CPC分类号： G06F12/08 , G06F12/10 , G11C5/025 , G11C29/04 , G11C29/18 , G11C29/76 , G11C29/78 , G11C29/808 , G11C29/812 , G11C29/883 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599
摘要： Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die.
摘要翻译：各种实施例包括具有布置在堆叠中的多个骰子的装置，系统和方法，其中有缺陷的单元可以被同一裸片上的备用单元或不同的管芯替代。

2. 发明申请

WO2010042496A2 STACKED DEVICE REMAPPING AND REPAIR 审中-公开
标题翻译：堆叠设备重新包装和维修
公开(公告)号：WO2010042496A2
公开(公告)日：2010-04-15
申请号：PCT/US2009/059669
申请日：2009-10-06
申请人： MICRON TECHNOLOGY, INC. , KEETH, Brent , MARTIN, Chris G. , MANNING, Troy A. , JEDDELOH, Joe M. , COWLES, Timothy B. , REHMEYER, Jim , LABERGE, Paul A.
发明人： KEETH, Brent , MARTIN, Chris G. , MANNING, Troy A. , JEDDELOH, Joe M. , COWLES, Timothy B. , REHMEYER, Jim , LABERGE, Paul A.
IPC分类号： G11C8/04 , G11C8/06
CPC分类号： G06F12/08 , G06F12/10 , G11C5/025 , G11C29/04 , G11C29/18 , G11C29/76 , G11C29/78 , G11C29/808 , G11C29/812 , G11C29/883 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die.
摘要翻译：各种实施例包括具有以堆叠方式布置的多个管芯的设备，系统和方法，其中有缺陷的单元可以被同一管芯或不同管芯上的备用单元替换。

3. 发明申请

WO2004001846A2 METHOD AND STRUCTURES FOR REDUCED PARASITIC CAPACITANCE IN INTEGRATED CIRCUIT METALLIZATIONS 审中-公开
标题翻译：集成电路金属化中降低PARASIIC电容的方法与结构
公开(公告)号：WO2004001846A2
公开(公告)日：2003-12-31
申请号：PCT/US2003/021029
申请日：2003-06-18
申请人： MICRON TECHNOLOGY, INC. , BATRA, Shubneesh , CHAINE, Michael, D. , KEETH, Brent , AKRAM, Salman , MANNING, Troy, A. , JOHNSON, Brian , MARTIN, Chris, G. , MERRITT, Todd, A. , SMITH, Eric, J.
发明人： BATRA, Shubneesh , CHAINE, Michael, D. , KEETH, Brent , AKRAM, Salman , MANNING, Troy, A. , JOHNSON, Brian , MARTIN, Chris, G. , MERRITT, Todd, A. , SMITH, Eric, J.
IPC分类号： H01L23/485
CPC分类号： H01L24/05 , H01L23/5222 , H01L24/03 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01061 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/30105
摘要： A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels (M1, M2, M3, etc) is described. The method comprises forming a bond pad (20) at least partially exposed at the top surface of the integrated circuit, forming a metal pad (22) on the metal level (42) below the bond pad (20) and forming an underlying metal pad (26b) on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads (22, 26b) to the area of the bond pad (20) is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.
摘要翻译：描述了一种降低具有三个或更多个金属水平（M1，M2，M3等）的集成电路中的寄生电容的方法。该方法包括形成至少部分地暴露在集成电路的顶表面处的接合焊盘（20），在接合焊盘（20）下方的金属层（42）上形成金属焊盘（22），并形成下面的金属焊盘（26b）在所述一个或多个下层金属层中的每一个上。在所示实施例中，下面的金属焊盘（22,26b）中的至少一个的面积与焊盘（20）的面积之比小于30％。寄生电容因此大大降低，信号传播速度提高。

4. 发明申请

WO2007005218B1 APPARATUS AND METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY 审中-公开
标题翻译：修复半导体存储器的装置和方法
公开(公告)号：WO2007005218B1
公开(公告)日：2007-04-26
申请号：PCT/US2006023219
申请日：2006-06-14
申请人： MICRON TECHNOLOGY INC , MARTIN CHRIS G , MANNING TROY A , KEETH BRENT
发明人： MARTIN CHRIS G , MANNING TROY A , KEETH BRENT
IPC分类号： G11C29/00
CPC分类号： G11C17/165 , G11C29/4401 , G11C29/789 , G11C29/802 , G11C29/808 , G11C2029/4402
摘要： An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.
摘要翻译：一种用于修复半导体存储器件的装置和方法包括第一存储器单元阵列，第一冗余单元阵列和修复电路，该修复电路被配置为非易失性地将指定至少一个故障存储器单元的第一地址存储在第一存储器单元阵列中。第一易失性高速缓存存储对应于指定至少一个有缺陷的存储单元的第一地址的第一高速缓存地址。修复电路将指定第一存储单元阵列的至少一个故障存储单元的第一地址分配给第一易失性缓存。当第一存储器访问对应于第一高速缓存地址时，匹配电路将来自第一冗余单元阵列的至少一个冗余存储器单元替换为第一存储器单元阵列中的至少一个有缺陷存储器单元。

5. 发明申请

WO2004001846A3 METHOD AND STRUCTURES FOR REDUCED PARASITIC CAPACITANCE IN INTEGRATED CIRCUIT METALLIZATIONS 审中-公开
标题翻译：集成电路金属化中降低PARASIIC电容的方法与结构
公开(公告)号：WO2004001846A3
公开(公告)日：2004-10-28
申请号：PCT/US0321029
申请日：2003-06-18
申请人： MICRON TECHNOLOGY INC , BATRA SHUBNEESH , CHAINE MICHAEL D , KEETH BRENT , AKRAM SALMAN , MANNING TROY A , JOHNSON BRIAN , MARTIN CHRIS G , MERRITT TODD A , SMITH ERIC J
发明人： BATRA SHUBNEESH , CHAINE MICHAEL D , KEETH BRENT , AKRAM SALMAN , MANNING TROY A , JOHNSON BRIAN , MARTIN CHRIS G , MERRITT TODD A , SMITH ERIC J
IPC分类号： H01L23/485 , H01L23/522 , H01L23/64
CPC分类号： H01L24/05 , H01L23/5222 , H01L24/03 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01061 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/30105
摘要： A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels (M1, M2, M3, etc) is described. The method comprises forming a bond pad (20) at least partially exposed at the top surface of the integrated circuit, forming a metal pad (22) on the metal level (42) below the bond pad (20) and forming an underlying metal pad (26b) on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads (22, 26b) to the area of the bond pad (20) is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.
摘要翻译：描述了一种降低具有三个或更多个金属水平（M1，M2，M3等）的集成电路中的寄生电容的方法。该方法包括形成至少部分地暴露在集成电路的顶表面处的接合焊盘（20），在接合焊盘（20）下方的金属层（42）上形成金属焊盘（22），并形成下面的金属焊盘（26b）在所述一个或多个下层金属层中的每一个上。在所示实施例中，下面的金属焊盘（22,26b）中的至少一个的面积与焊盘（20）的面积之比小于30％。寄生电容因此大大降低，信号传播速度提高。

6. 发明申请

WO2007005218A1 APPARATUS AND METHOD FOR REPAIRING A SEMICONDUCTOR MEMORY 审中-公开
标题翻译：用于修复半导体存储器的装置和方法
公开(公告)号：WO2007005218A1
公开(公告)日：2007-01-11
申请号：PCT/US2006/023219
申请日：2006-06-14
申请人： MICRON TECHNOLOGY, INC. , MARTIN, Chris, G. , MANNING, Troy, A. , KEETH, Brent
发明人： MARTIN, Chris, G. , MANNING, Troy, A. , KEETH, Brent
IPC分类号： G11C29/00
CPC分类号： G11C17/165 , G11C29/4401 , G11C29/789 , G11C29/802 , G11C29/808 , G11C2029/4402
摘要： An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.
摘要翻译：用于修复半导体存储器件的装置和方法包括：第一存储单元阵列，第一冗余单元阵列和修复电路，被配置为在第一存储单元阵列中非易失性地存储指定至少一个有缺陷的存储单元的第一地址。第一易失性高速缓存存储对应于指定所述至少一个有缺陷的存储器单元的第一地址的第一高速缓存地址。修复电路将指定第一存储单元阵列的至少一个缺陷存储单元的第一地址分配给第一易失性高速缓存。当第一存储器访问对应于第一高速缓存地址时，匹配电路将来自第一冗余单元阵列的至少一个冗余存储单元替换为第一存储单元阵列中的至少一个有缺陷的存储单元。

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