专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2003001529A2 METHOD AND CIRCUIT ARRANGEMENT FOR MEMORY ERROR RECOVERY 审中-公开
标题翻译：用于存储器错误恢复的方法和电路布置
公开(公告)号：WO2003001529A2
公开(公告)日：2003-01-03
申请号：PCT/IB2002/002334
申请日：2002-06-18
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SALTERS, Roelof, H., W. , CUPPENS, Roger , DITEWEG, Anthonie, M., H.
发明人： SALTERS, Roelof, H., W. , CUPPENS, Roger , DITEWEG, Anthonie, M., H.
IPC分类号： G11C
CPC分类号： G11C29/802 , G11C29/812
摘要： The present invention relates to a method and circuit arrangement for performing an error recovery in a memory arrangement comprising at least two separate memories. The memory arrangement comprises a central storage for storing a faulty-address information of the at least two separate memories. Each memory has its own local address comparison unit and local volatile memory for addresses. The faulty-address information is transported from the central storage to the local volatile memories for address comparison of a redundancy system. Thereby, overhead and complexity can be reduced and flexibility of the architecture enhanced.
摘要翻译：本发明涉及一种用于在包括至少两个分开的存储器的存储器装置中执行错误恢复的方法和电路装置。存储器装置包括用于存储至少两个单独存储器的故障地址信息的中央存储器。每个存储器都有自己的本地地址比较单元和用于地址的本地易失性存储器。故障地址信息从中央存储器传送到本地易失性存储器，用于冗余系统的地址比较。因此，可以降低开销和复杂性并增强架构的灵活性。

2. 发明申请

WO2008154290A1 MEMORY REPAIR SYSTEM AND METHOD 审中-公开
标题翻译：记忆修复系统和方法
公开(公告)号：WO2008154290A1
公开(公告)日：2008-12-18
申请号：PCT/US2008/065920
申请日：2008-06-05
申请人： TEXAS INSTRUMENTS INCORPORATED , RAHMAN, Mohammad, Jahidur , GEORGE, Sabuson
发明人： RAHMAN, Mohammad, Jahidur , GEORGE, Sabuson
IPC分类号： G11C29/00 , G11C16/00
CPC分类号： G11C29/02 , G11C17/14 , G11C29/027 , G11C29/76 , G11C29/812 , G11C2029/0401 , G11C2229/726
摘要： A system and method for making efficient use of fuse ROM redundancy to increase yield and security. Some embodiments provide a memory repair system including a non¬ volatile memory component (104) and a controller (106) coupled to the non-volatile memory component. The non-volatile memory component includes a plurality of memory locations. The plurality of memory locations includes a replacement memory location to replace a faulty memory location and a replacement indicia memory location to store replacement memory location indicia. The controller coupled to the non-volatile memory component reads replacement memory location indicia from the replacement indicia memory location, determines an address for the replacement memory location using the indicia, reads the replacement memory location, and transfers a data value contained in the replacement memory location to a second memory component (112) to repair a defective memory location of the second memory component.
摘要翻译：一种用于有效利用熔丝ROM冗余来增加产量和安全性的系统和方法。一些实施例提供了包括非易失性存储器组件（104）和耦合到非易失性存储器组件的控制器（106）的存储器修复系统。非易失性存储器组件包括多个存储器位置。多个存储器位置包括替换存储器位置以替换故障存储器位置和替换标记存储器位置以存储替换存储器位置标记。耦合到非易失性存储器组件的控制器从替换标记存储器位置读取替代存储器位置标记，使用标记确定替换存储器位置的地址，读取替换存储器位置，并且传送包含在替换存储器中的数据值位置到第二存储器组件（112）以修复第二存储器组件的有缺陷的存储器位置。

3. 发明申请

WO2007028109A3 METHODS AND APPARATUS OF STACKING DRAMS 审中-公开
标题翻译：堆叠工艺的方法与装置
公开(公告)号：WO2007028109A3
公开(公告)日：2008-01-10
申请号：PCT/US2006034390
申请日：2006-09-01
申请人： METARAM INC , RAJAN SURESH , SMITH MICHAEL , WANG DAVID
发明人： RAJAN SURESH , SMITH MICHAEL , WANG DAVID
IPC分类号： G11C8/00
CPC分类号： G11C7/00 , G11C5/02 , G11C7/10 , G11C11/4093 , G11C29/812
摘要： Large capacity memory systems (FB-DIMMs) are constructed using stacked memory integrated circuits (220) or chips (310). The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.
摘要翻译：使用堆叠存储器集成电路（220）或芯片（310）构建大容量存储器系统（FB-DIMM）。堆叠的存储器芯片被构造成在满足当前和将来的存储器标准的同时消除诸如信号完整性的问题。

4. 发明申请

WO2007028109A2 METHODS AND APPARATUS OF STACKING DRAMS 审中-公开
标题翻译：堆叠工艺的方法与装置
公开(公告)号：WO2007028109A2
公开(公告)日：2007-03-08
申请号：PCT/US2006/034390
申请日：2006-09-01
申请人： METARAM, INC. , RAJAN, Suresh , SMITH, Michael , WANG, David
发明人： RAJAN, Suresh , SMITH, Michael , WANG, David
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C5/02 , G11C7/10 , G11C11/4093 , G11C29/812
摘要： Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.
摘要翻译：使用堆叠式存储器集成电路或芯片构建大容量存储器系统。堆叠的存储器芯片被构造成在满足当前和将来的存储器标准的同时消除诸如信号完整性的问题。

5. 发明申请

WO2006059797A1 SEMICONDUCTOR MEMORY DEVICE WITH REDUNDANCY FUNCTION 审中-公开
标题翻译：具有冗余功能的半导体存储器件
公开(公告)号：WO2006059797A1
公开(公告)日：2006-06-08
申请号：PCT/JP2005/022513
申请日：2005-12-01
申请人： KABUSHIKI KAISHA TOSHIBA , TAKAI, Tomohisa , HAGA, Ryo
发明人： TAKAI, Tomohisa , HAGA, Ryo
IPC分类号： G11C29/00
CPC分类号： G11C29/802 , G11C29/812
摘要： A fuse and fuse latch includes first and second fuse and fuse latches each serving as a redundancy information storage circuit. Fuse elements and a fuse latch are provided in each of the first and second fuse and fuse latches. The first and second fuse and fuse latches each output latched data as serial data to a fuse data transfer control circuit. The fuse data transfer control circuit serving as a redundancy information creation circuit is configured of a counter and a data transfer control circuit. The data transfer control circuit combines data output from the first and second fuse and fuse latches, thereby to create new data.
摘要翻译：保险丝和保险丝锁存器包括第一和第二保险丝和熔丝锁存器，每个用作冗余信息存储电路。保险丝元件和保险丝锁存器设置在第一和第二保险丝和熔丝锁存器的每一个中。第一和第二熔丝和熔丝将每个输出的锁存数据作为串行数据输出到熔丝数据传输控制电路。作为冗余信息生成电路的熔丝数据传送控制电路由计数器和数据传送控制电路构成。数据传输控制电路组合从第一和第二熔丝和熔丝锁存器输出的数据，从而创建新的数据。

6. 发明申请

WO03001529A3 METHOD AND CIRCUIT ARRANGEMENT FOR MEMORY REDUNDANCY SYSTEM 审中-公开
标题翻译：存储器冗余系统的方法和电路布置
公开(公告)号：WO03001529A3
公开(公告)日：2003-04-10
申请号：PCT/IB0202334
申请日：2002-06-18
申请人： KONINKL PHILIPS ELECTRONICS NV , SALTERS ROELOF H W , CUPPENS ROGER , DITEWEG ANTHONIE M H
发明人： SALTERS ROELOF H W , CUPPENS ROGER , DITEWEG ANTHONIE M H
IPC分类号： G11C29/00
CPC分类号： G11C29/802 , G11C29/812
摘要： The present invention relates to a method and circuit arrangement for performing an error recovery in a memory arrangement comprising at least two separate memories. The memory arrangement comprises a central storage for storing a faulty-address information of the at least two separate memories. Each memory has its own local address comparison unit and local volatile memory for addresses. The faulty-address information is transported from the central storage to the local volatile memories for address comparison of a redundancy system. Thereby, overhead and complexity can be reduced and flexibility of the architecture enhanced.
摘要翻译：本发明涉及一种用于在包括至少两个分开的存储器的存储器装置中执行错误恢复的方法和电路装置。存储器装置包括用于存储至少两个单独存储器的故障地址信息的中央存储器。每个存储器都有自己的本地地址比较单元和用于地址的本地易失性存储器。故障地址信息从中央存储器传送到本地易失性存储器，用于冗余系统的地址比较。因此，可以降低开销和复杂性并增强架构的灵活性。

7. 发明申请

WO2010042496A3 STACKED DEVICE REMAPPING AND REPAIR 审中-公开
标题翻译：堆叠设备重新修复和维修
公开(公告)号：WO2010042496A3
公开(公告)日：2010-07-22
申请号：PCT/US2009059669
申请日：2009-10-06
申请人： MICRON TECHNOLOGY INC , KEETH BRENT , MARTIN CHRIS G , MANNING TROY A , JEDDELOH JOE M , COWLES TIMOTHY B , REHMEYER JIM , LABERGE PAUL A
发明人： KEETH BRENT , MARTIN CHRIS G , MANNING TROY A , JEDDELOH JOE M , COWLES TIMOTHY B , REHMEYER JIM , LABERGE PAUL A
IPC分类号： G11C8/04 , G11C8/06
CPC分类号： G06F12/08 , G06F12/10 , G11C5/025 , G11C29/04 , G11C29/18 , G11C29/76 , G11C29/78 , G11C29/808 , G11C29/812 , G11C29/883 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599
摘要： Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die.
摘要翻译：各种实施例包括具有布置在堆叠中的多个骰子的装置，系统和方法，其中有缺陷的单元可以被同一裸片上的备用单元或不同的管芯替代。

8. 发明申请

WO2010047912A1 METHOD FOR SELECTIVELY RETRIEVING COLUMN REDUNDANCY DATA IN MEMORY DEVICE 审中-公开
标题翻译：用于选择性地在存储器件中检索色谱冗余数据的方法
公开(公告)号：WO2010047912A1
公开(公告)日：2010-04-29
申请号：PCT/US2009/057996
申请日：2009-09-23
申请人： SANDISK 3D LLC , BOTTELLI, Aldo , FASOLI, Luca , SOJOURNER, Doug
发明人： BOTTELLI, Aldo , FASOLI, Luca , SOJOURNER, Doug
IPC分类号： G11C29/00
CPC分类号： G11C29/812 , G11C29/802 , G11C29/82
摘要： Column redundancy data is selectively retrieved in a memory device according to a set of storage elements which is currently being accessed, such as in a read or write operation. The memory device is organized into sets of storage elements such as logical blocks, where column redundancy data is loaded from a non-volatile storage location to a volatile storage location for one or more particular blocks which are being accessed. The volatile storage location need only be large enough to store the current data entries. The size of the set of storage elements for which column redundancy data is concurrently loaded can be configured based on an expected maximum number of defects and a desired repair probability. During a manufacturing lifecycle, the size of the set can be increased as the number of defects is reduced due to improvements in manufacturing processes and materials.
摘要翻译：根据当前正在被访问的一组存储元件，例如在读取或写入操作中，在存储器件中选择性地检索列冗余数据。存储器设备被组织成诸如逻辑块的存储元件组，其中列冗余数据从非易失性存储位置加载到正被访问的一个或多个特定块的易失性存储位置。易失性存储位置仅需要足够大以存储当前数据条目。可以基于期望的最大缺陷数量和期望的修复概率来配置列冗余数据同时加载的存储元件组的大小。在制造生命周期中，随着制造工艺和材料的改进，缺陷数量的减少可以增加组件的尺寸。

9. 发明申请

WO2010042496A2 STACKED DEVICE REMAPPING AND REPAIR 审中-公开
标题翻译：堆叠设备重新包装和维修
公开(公告)号：WO2010042496A2
公开(公告)日：2010-04-15
申请号：PCT/US2009/059669
申请日：2009-10-06
申请人： MICRON TECHNOLOGY, INC. , KEETH, Brent , MARTIN, Chris G. , MANNING, Troy A. , JEDDELOH, Joe M. , COWLES, Timothy B. , REHMEYER, Jim , LABERGE, Paul A.
发明人： KEETH, Brent , MARTIN, Chris G. , MANNING, Troy A. , JEDDELOH, Joe M. , COWLES, Timothy B. , REHMEYER, Jim , LABERGE, Paul A.
IPC分类号： G11C8/04 , G11C8/06
CPC分类号： G06F12/08 , G06F12/10 , G11C5/025 , G11C29/04 , G11C29/18 , G11C29/76 , G11C29/78 , G11C29/808 , G11C29/812 , G11C29/883 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die.
摘要翻译：各种实施例包括具有以堆叠方式布置的多个管芯的设备，系统和方法，其中有缺陷的单元可以被同一管芯或不同管芯上的备用单元替换。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式