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1. 发明申请

WO2016032784A1 BUFFER CIRCUIT WITH ADAPTIVE REPAIR CAPABILITY 审中-公开
标题翻译：具有自适应维修能力的缓冲电路
公开(公告)号：WO2016032784A1
公开(公告)日：2016-03-03
申请号：PCT/US2015/045495
申请日：2015-08-17
申请人： RAMBUS INC.
发明人： BEST, Scott, C , LINSTADT, John Eric , ROUKEMA, Paul William
IPC分类号： G11C29/04 , G11C29/44 , G11C29/52
CPC分类号： G11C29/4401 , G11C5/04 , G11C11/401 , G11C29/022 , G11C29/52 , G11C29/76 , G11C29/783 , G11C29/88 , G11C2029/4402
摘要： A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.
摘要翻译：公开了一种缓冲电路。缓冲电路包括用于接收输入激活（ACT）命令和输入列地址选通（CAS）命令的命令地址（C / A）接口。第一匹配电路包括用于存储与存储器相关联的故障行地址信息的第一存储器和第一比较逻辑。第一个比较逻辑响应于ACT命令，将输入的行地址信息与存储的故障行地址信息进行比较。第二匹配电路包括用于存储与存储器相关联的故障列地址信息的第二存储器和第二比较逻辑。第二个比较逻辑响应CAS命令，将输入的列地址信息与存储的故障列地址信息进行比较。在由第二比较逻辑执行的比较期间，门控逻辑维持由第一比较逻辑识别的匹配行地址的状态。

2. 发明申请

WO2015191235A1 INDEPENDENT SYNCHRONIZATION OF OUTPUT DATA VIA DISTRIBUTED CLOCK SYNCHRONIZATION 审中-公开
标题翻译：通过分布式时钟同步的输出数据的独立同步
公开(公告)号：WO2015191235A1
公开(公告)日：2015-12-17
申请号：PCT/US2015/031044
申请日：2015-05-15
申请人： QUALCOMM INCORPORATED
发明人： CLOVIS, Philip Michael , TSENG, Yi-Hung , HUANG, Xuhao , CHILUKURI, Sushma
IPC分类号： G06F13/16 , G06F13/42 , G11C7/10 , G11C7/22 , G11C29/02 , H03L7/07 , H03L7/081
CPC分类号： G11C7/222 , G06F13/1689 , G06F13/4243 , G06F13/4291 , G11C7/10 , G11C7/1066 , G11C7/1093 , G11C29/022 , G11C29/023 , G11C29/028 , H03L7/07 , H03L7/0814
摘要： A memory controller is provided that drives data and a corresponding first data strobe to a plurality of endpoints. Each endpoint is configured to register the received data from the memory controller responsive to the first data strobe and then to re-register the received data responsive to a second data strobe. A clock synchronization circuit functions to keep the received first data strobe at one of the endpoints sufficiently synchronous with the second data strobe.
摘要翻译：提供了一种存储器控制器，其将数据和相应的第一数据选通信号驱动到多个端点。每个端点被配置为响应于第一数据选通从存储器控制器注册接收到的数据，然后响应于第二数据选通来重新注册接收到的数据。时钟同步电路用于将接收到的第一数据选通信号保持在其中一个端点与第二数据选通脉冲充分同步。

3. 发明申请

WO2014165214A3 CONTINUOUS ADAPTIVE TRAINING FOR DATA INTERFACE TIMING CALIBRATION 审中-公开
标题翻译：数据接口定时校准的连续适应性训练
公开(公告)号：WO2014165214A3
公开(公告)日：2014-11-27
申请号：PCT/US2014024818
申请日：2014-03-12
申请人： UNIQUIFY INC
发明人： IYER VENKAT , LEE JUNG , JOSHI PRASHANT
IPC分类号： G11C7/10
CPC分类号： G06F13/3625 , G06F13/1689 , G06F13/4256 , G11C8/18 , G11C29/022 , G11C29/023 , G11C29/028 , H03K5/133 , H03K5/14 , H03K2005/00019 , H03L7/08 , H03L7/0812 , H03L7/10
摘要： Circuits and methods for implementing a continuously adaptive timing calibration training function in an integrated circuit interface are disclosed. A mission data path is established where a data bit is sampled by a strobe. A similar reference data path is established for calibration purposes only. At an initialization time both paths are calibrated and a delta value between them is established. During operation of the mission path, the calibration path continuously performs calibration operations to determine if its optimal delay has changed by more than a threshold value. If so, the new delay setting for the reference path is used to change the delay setting for the mission path after adjustment by the delta value. Circuits and methods are also disclosed for performing multiple parallel calibrations for the reference path to speed up the training process.
摘要翻译：公开了用于在集成电路接口中实现连续自适应定时校准训练功能的电路和方法。任务数据路径建立在通过选通脉冲对数据位进行采样的地方。仅为校准目的建立类似的参考数据路径。在初始化时，两个路径都被校准并且它们之间的增量值被建立。在任务路径的操作期间，校准路径连续执行校准操作以确定其最佳延迟是否已经改变超过阈值。如果是，则参考路径的新延迟设置用于在由增量值调整之后改变任务路径的延迟设置。还公开了用于对参考路径执行多个平行校准以加速训练过程的电路和方法。

4. 发明申请

WO2012118770A8 SYSTEM AND METHOD FOR BONDED CONFIGURATION PAD CONTINUITY CHECK 审中-公开
标题翻译：用于粘结配置连续性检查的系统和方法
公开(公告)号：WO2012118770A8
公开(公告)日：2012-11-15
申请号：PCT/US2012026827
申请日：2012-02-27
申请人： SANDISK TECHNOLOGIES INC , LIU BAOJING , GUTTA ARUNA , SKALA STEPHEN
发明人： LIU BAOJING , GUTTA ARUNA , SKALA STEPHEN
IPC分类号： G11C29/02 , G01R31/04 , G01R31/28 , G01R31/317
CPC分类号： G11C29/022 , G01R31/026
摘要： A continuity test circuit for a boundary pad includes a pull-up transistor electrically connected between the boundary pad and a first power supply, and a pull-down transistor electrically connected between the boundary pad and a first reference ground potential. A normal output conductor is electrically connected to have a same electrical state as the boundary pad during normal operation. A continuity test output conductor is electrically connected to have a same electrical state as the boundary pad during continuity test operation. Continuity testing control circuitry is defined to control the pull-up transistor, the pull-down transistor, and the normal output conductor during continuity test operation such that an electrical state present on the continuity test output conductor indicates a status of electrical continuity between the boundary pad and either a second power supply or a second reference ground potential to which the boundary pad should be electrically connected.
摘要翻译：用于边界焊盘的连续性测试电路包括电连接在边界焊盘和第一电源之间的上拉电晶体，以及电连接在边界焊盘和第一参考接地电位之间的下拉晶体管。在正常操作期间，正常输出导体电连接以具有与边界焊盘相同的电状态。连续性测试输出导体在连续性测试操作期间电连接以具有与边界焊盘相同的电状态。连续性测试控制电路被定义为在连续性测试操作期间控制上拉晶体管，下拉晶体管和正常输出导体，使得存在于导通性测试输出导体上的电状态指示边界之间的电连续性状态焊盘以及边界焊盘应与其电连接的第二电源或第二参考地电位。

5. 发明申请

WO2012059985A1 集積回路、電圧値取得方法および送受信システム审中-公开
标题翻译：集成电路，电压值采集方法和传输系统
公开(公告)号：WO2012059985A1
公开(公告)日：2012-05-10
申请号：PCT/JP2010/069527
申请日：2010-11-02
申请人：富士通株式会社 , 酒巻秀行 , 岩見義和
发明人：酒巻　秀行 , 岩見　義和
IPC分类号： H04L7/02 , G06F12/00 , H04L7/04
CPC分类号： G06F1/04 , G06F13/1689 , G11C5/04 , G11C7/1066 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要：　メモリコントローラ１０は、ＤＩＭＭ３０から送信されたＤＱ信号を受信するレシーバ１２Ａと、送信回路から送信された、データ信号の読み取りタイミングを示すＤＱＳ信号を受信するレシーバ１２Ｂとを有する。また、メモリコントローラ１０は、受信されたタイミング信号の出力タイミングを調整するＤｅｌａｙ回路１３Ａを有する。そして、メモリコントローラ１０は、Ｄｅｌａｙ回路１３Ａによって出力タイミングが調整された遅延ＤＱＳ信号に応じて、ＤＱ信号を読み取る。そして、メモリコントローラ１０は、遅延ＤＱ信号の電圧値と、遅延ＤＱＳ信号の電圧値とを取得する。
摘要翻译：存储器控制器（10）具有用于接收从DIMM（30）发送的DQ信号的接收器（12A）和用于接收从发送电路发送的DQS信号的接收器（12B），并且用于显示数据信号。此外，存储器控制器（10）具有用于调整接收到的定时信号的输出定时的延迟电路（13A）。存储器控制器（10）根据延迟DQS信号读出DQ信号，其中输出定时已由延迟电路（13A）调节。存储器控制器（10）获取延迟DQ信号的电压值和延迟DQS信号的电压值。

6. 发明申请

WO2011092526A1 A DRIVER FOR DDR2/3 MEMORY INTERFACES 审中-公开
标题翻译： DDR2 / 3内存接口的驱动程序
公开(公告)号：WO2011092526A1
公开(公告)日：2011-08-04
申请号：PCT/GR2011/000005
申请日：2011-01-27
申请人： ANALOGIES S.A. , PLESSAS, Fotis , DAVRAZOS, Efthimios , BIRBAS, Michael , KIKIDIS, John
发明人： PLESSAS, Fotis , DAVRAZOS, Efthimios , BIRBAS, Michael , KIKIDIS, John
IPC分类号： G11C29/02 , G11C7/10 , G11C11/4096
CPC分类号： G11C7/1072 , G11C7/10 , G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/1069 , G11C7/1078 , G11C7/1084 , G11C7/12 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/028 , G11C2207/2254
摘要： An apparatus is described that includes a combined drive and termination circuit programmable to interface to DDR2 and DDR3 memory modules. In an exemplary embodiment the apparatus includes a combined output/termination driver, an input driver and a calibration subsystem. The combined output/termination driver includes a number of pull-up circuits and a number of pull-down circuits. One of the pull-up circuits presents a fixed output impedance. The rest of the pull-up circuits have an impedance programmable between two desired impedance values. One of the pull-down circuits presents a fixed output impedance. The rest of the pull-down circuits have an impedance programmable between two desired impedance values. The necessary number of pull-up circuits and pull-down circuits is activated in order to provide a desired driving and termination circuit such as to interface to specific impedance values as defined by the DDR2 and DDR3 interface protocol.
摘要翻译：描述了一种装置，其包括可编程以与DDR2和DDR3存储器模块接口的组合的驱动和终端电路。在示例性实施例中，该装置包括组合的输出/终端驱动器，输入驱动器和校准子系统。组合的输出/终端驱动器包括多个上拉电路和多个下拉电路。其中一个上拉电路呈现固定的输出阻抗。其余的上拉电路的阻抗可编程在两个所需的阻抗值之间。一个下拉电路呈现固定的输出阻抗。其余的下拉电路具有两个所需阻抗值之间可编程的阻抗。激活必要数量的上拉电路和下拉电路，以便提供期望的驱动和终止电路，以便与由DDR2和DDR3接口协议定义的特定阻抗值相连接。

7. 发明申请

WO2009024423A1 PROGRAMMABLE DIAGNOSTIC MEMORY MODULE 审中-公开
标题翻译：可编程诊断记忆模块
公开(公告)号：WO2009024423A1
公开(公告)日：2009-02-26
申请号：PCT/EP2008/059539
申请日：2008-07-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , IBM UNITED KINGDOM LIMITED , CASES, Moises , PHAM, Nam, Huu , ARAUJO, Daniel, N de , MUTNURY, Bhyrav, Murthy , DREPS, Daniel, Mark
发明人： CASES, Moises , PHAM, Nam, Huu , ARAUJO, Daniel, N de , MUTNURY, Bhyrav, Murthy , DREPS, Daniel, Mark
IPC分类号： G11C29/56 , G06F11/273
CPC分类号： G06F11/2733 , G11C5/04 , G11C29/02 , G11C29/022 , G11C29/16 , G11C29/56 , G11C2029/5602
摘要： A programmable diagnostic memory module provides enhanced testability of memory controller and memory subsystem design. The programmable diagnostic memory module includes an interface for communicating with an external diagnostic system, and the interface is used to transfer commands to the memory module to alter various behaviors of the memory module. The altered behaviors may be changing data streams that are written to the memory module to simulate errors, altering the timing and/or loading of the memory module signals, downloading programs for execution by a processor core within the memory module, changing driver strengths of output signals of the memory module, and manipulating in an analog domain, signals at terminals of the memory module such as injecting noise on power supply connections to the memory module. The memory module may emulate multiple selectable memory module types, and may include a complete storage array to provide standard memory module operation.
摘要翻译：可编程诊断内存模块提供了内存控制器和内存子系统设计的增强的可测试性。可编程诊断存储器模块包括用于与外部诊断系统通信的接口，并且该接口用于将命令传送到存储器模块以改变存储器模块的各种行为。改变的行为可能是改变被写入存储器模块的数据流，以模拟错误，改变存储器模块信号的定时和/或加载，下载由存储器模块内的处理器核心执行的程序，改变驱动器的输出强度存储器模块的信号和在模拟域中的操作，在存储器模块的端子处发出信号，例如在与存储器模块的电源连接上注入噪声。存储器模块可以模拟多个可选择的存储器模块类型，并且可以包括完整的存储阵列以提供标准存储器模块操作。

8. 发明申请

WO2008145703A1 REGISTER WITH PROCESS, SUPPLY VOLTAGE AND TEMPERATURE VARIATION INDEPENDENT PROPAGATION DELAY PATH 审中-公开
标题翻译：具有过程，供电电压和温度变化独立传播延迟路径的寄存器
公开(公告)号：WO2008145703A1
公开(公告)日：2008-12-04
申请号：PCT/EP2008/056629
申请日：2008-05-29
申请人： TEXAS INSTRUMENTS DEUTSCHLAND GMBH , ROMBACH, Gerd , TAMBOURIS, Sotirios
发明人： ROMBACH, Gerd , TAMBOURIS, Sotirios
IPC分类号： H03L7/081 , G11C7/10 , G11C7/22
CPC分类号： H03L7/06 , G11C7/04 , G11C7/22 , G11C7/225 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028
摘要： The digital data register has a plurality of parallel matched data paths, each data path having a data input for receiving a digital data input signal (CA/CNTRL), an output driver with a data output providing a digital data output signal (Q_CA/CNTRL) for application to an associated memory module and a flip-flop (FF1) arranged between the data input and the data output. The data register further comprises a clock input for receiving a clock input signal (CLK), a clock output for providing an output clock signal (Q_CLKn, Q_NCLKn) to the memory modules, a phase locked loop (PLL) with a clock input (REF), a feedback input (FB), a feedback output providing a feedback output signal (Q_NFB) and a clock output providing a clock output signal (Q_CLK, QNCLK). In addition a flip-flop (FF1 DELAY) and output driver replica is matched with the flip-flop and output driver of the data paths. The flip-flops (FF1) of the data paths and the flip-flop (FF1 DELAY) of the replica are clocked by the feedback signal applied to the feedback input (FB) of the phase locked loop (PLL). The phase locked loop (PLL) includes a phase aligner with a phase interpolator. The phase interpolator has an output that provides the output clock signal (Q_CLKn, Q_NCLKn) to the memory modules through a flip-flop (FF1 DELAY) and output driver matched with the flip-flop and output driver of the data paths. A phase frequency detector (PFD) has a first input (REF) coupled to the output of the output driver replica and a second input (SYS) coupled to the clock output. The phase interpolator is controlled by the output of the phase frequency detector (PFD). The proposed data register satisfies the three requirements of: (i) setup and hold timing on the pre-register side, (ii) clock centring on the post-register side, and (iii) constant propagation delay (tpd) over PVT variations from the clock input to the data output.
摘要翻译：数字数据寄存器具有多个并行匹配的数据路径，每个数据路径具有用于接收数字数据输入信号（CA / CNTRL）的数据输入端，具有提供数字数据输出信号（Q_CA / CNTRL）的数据输出的输出驱动器），用于应用于相关联的存储器模块和布置在数据输入和数据输出之间的触发器（FF1）。数据寄存器还包括用于接收时钟输入信号（CLK）的时钟输入，用于向存储器模块提供输出时钟信号（Q_CLKn，Q_NCLKn）的时钟输出，具有时钟输入（REF）的锁相环（PLL）），反馈输入（FB），提供反馈输出信号（Q_NFB）的反馈输出和提供时钟输出信号（Q_CLK，QNCLK）的时钟输出。此外，触发器（FF1 DELAY）和输出驱动器副本与数据路径的触发器和输出驱动器匹配。数据路径的触发器（FF1）和副本的触发器（FF1 DELAY）由施加到锁相环（PLL）的反馈输入（FB）的反馈信号计时。锁相环（PLL）包括具有相位内插器的相位对准器。相位内插器具有通过触发器（FF1 DELAY）和与触发器和数据路径的输出驱动器匹配的输出驱动器将输出时钟信号（Q_CLKn，Q_NCLKn）提供给存储器模块的输出。相位频率检测器（PFD）具有耦合到输出驱动器副本的输出的第一输入（REF）和耦合到时钟输出的第二输入（SYS）。相位内插器由相位频率检测器（PFD）的输出控制。所提出的数据寄存器满足以下三个要求：（i）预寄存器侧的建立和保持定时，（ii）以寄存器侧为中心的时钟，以及（iii）PVT变化之后的恒定传播延迟（tpd）时钟输入到数据输出。

9. 发明申请

WO2007131130A2 INTERFACE TEST CIRCUIT 审中-公开
标题翻译：接口测试电路
公开(公告)号：WO2007131130A2
公开(公告)日：2007-11-15
申请号：PCT/US2007/068177
申请日：2007-05-03
申请人： RAMBUS INC. , TRAN, Chanh, V. , STOTT, Bret , LAU, Benedict , BROOKS, John, W. , YEUNG, Philip , HO, Eugene, C.
发明人： TRAN, Chanh, V. , STOTT, Bret , LAU, Benedict , BROOKS, John, W. , YEUNG, Philip , HO, Eugene, C.
IPC分类号： G01R31/317 , G01R31/3187 , G06F11/27
CPC分类号： G01R31/31716 , G11C29/022
摘要： An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.
摘要翻译：描述了集成电路。集成电路包括包括发射机和接收机的接口电路。集成电路中的发生器选择性地耦合到发射机。发生器将提供在测试操作模式期间由发射器输出的测试序列。集成电路中的存储器选择性地耦合到发生器和接收器。存储器是接收并同步测试序列和对应于由接收机接收的测试序列的信号。集成电路中的逻辑电路是比较测试序列和信号。

10. 发明申请

WO2007103892A2 METHOD AND APPARATUS FOR TESTING DATA STEERING LOGIC FOR DATA STORAGE HAVING INDEPENDENTLY ADDRESSABLE SUBUNITS 审中-公开
标题翻译：用于测试具有独立地址的数据存储的数据转向逻辑的方法和装置
公开(公告)号：WO2007103892A2
公开(公告)日：2007-09-13
申请号：PCT/US2007/063339
申请日：2007-03-05
申请人： QUALCOMM INCORPORATED , MAMILETI, Lakshmikant , KRISHNAMURTHY, Anand , MUMFORD, Clint Wayne , PATEL, Sanjay B.
发明人： MAMILETI, Lakshmikant , KRISHNAMURTHY, Anand , MUMFORD, Clint Wayne , PATEL, Sanjay B.
CPC分类号： G11C29/16 , G11C29/022 , G11C29/1201 , G11C29/44 , G11C29/4401 , G11C2029/1208
摘要： Read and write data steering logic in the I/O of a memory array is tested by providing a data bus lane for each addressable subunit of a memory array storage location. Each bus lane is connected to the data input of a comparator. A BIST controller writes test patterns to the memory through the write steering logic and reads the test patterns in parallel to test the write steering logic. The BIST controller writes test patterns to the memory in parallel and reads the test patterns through the read steering logic to test the read steering logic. In both cases, a separate comparator dedicated to each bus lane verifies that the subunit data was properly shifted between the data bus lane and memory storage location subunit. The comparators are effectively disabled during normal operations to prevent logic gate switching.
摘要翻译：通过为存储器阵列存储位置的每个可寻址子单元提供数据总线通道来测试存储器阵列的I / O中的读写数据转向逻辑。每个总线通道连接到比较器的数据输入。 BIST控制器通过写入指导逻辑将测试模式写入存储器，并并行读取测试模式以测试写入转向逻辑。 BIST控制器将测试模式并行地写入存储器，并通过读取转向逻辑读取测试模式，以测试读取转向逻辑。在这两种情况下，专用于每个总线通道的单独的比较器验证子数据在数据总线通道和存储器存储位置子单元之间正确移位。比较器在正常操作期间被有效地禁用，以防止逻辑门切换。

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