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1. 发明申请

WO2004001846A3 METHOD AND STRUCTURES FOR REDUCED PARASITIC CAPACITANCE IN INTEGRATED CIRCUIT METALLIZATIONS 审中-公开
标题翻译：集成电路金属化中降低PARASIIC电容的方法与结构
公开(公告)号：WO2004001846A3
公开(公告)日：2004-10-28
申请号：PCT/US0321029
申请日：2003-06-18
申请人： MICRON TECHNOLOGY INC , BATRA SHUBNEESH , CHAINE MICHAEL D , KEETH BRENT , AKRAM SALMAN , MANNING TROY A , JOHNSON BRIAN , MARTIN CHRIS G , MERRITT TODD A , SMITH ERIC J
发明人： BATRA SHUBNEESH , CHAINE MICHAEL D , KEETH BRENT , AKRAM SALMAN , MANNING TROY A , JOHNSON BRIAN , MARTIN CHRIS G , MERRITT TODD A , SMITH ERIC J
IPC分类号： H01L23/485 , H01L23/522 , H01L23/64
CPC分类号： H01L24/05 , H01L23/5222 , H01L24/03 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01061 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/30105
摘要： A method of reducing parasitic capacitance in an integrated circuit having three or more metal levels (M1, M2, M3, etc) is described. The method comprises forming a bond pad (20) at least partially exposed at the top surface of the integrated circuit, forming a metal pad (22) on the metal level (42) below the bond pad (20) and forming an underlying metal pad (26b) on each of the one or more lower metal levels. In the illustrated embodiments, the ratio of an area of at least one of the underlying metal pads (22, 26b) to the area of the bond pad (20) is less than 30%. Parasitic capacitance is thus greatly reduced and signal propagation speeds improved.
摘要翻译：描述了一种降低具有三个或更多个金属水平（M1，M2，M3等）的集成电路中的寄生电容的方法。该方法包括形成至少部分地暴露在集成电路的顶表面处的接合焊盘（20），在接合焊盘（20）下方的金属层（42）上形成金属焊盘（22），并形成下面的金属焊盘（26b）在所述一个或多个下层金属层中的每一个上。在所示实施例中，下面的金属焊盘（22,26b）中的至少一个的面积与焊盘（20）的面积之比小于30％。寄生电容因此大大降低，信号传播速度提高。

2. 发明申请

WO2006026526A3 MEMORY SYSTEM AND METHOD FOR STROBING DATA, COMMAND AND ADDRESS SIGNALS 审中-公开
标题翻译：存储器系统和数据，命令和地址信号的方法
公开(公告)号：WO2006026526A3
公开(公告)日：2006-05-04
申请号：PCT/US2005030593
申请日：2005-08-26
申请人： MICRON TECHNOLOGY INC , LIN FENG , KEETH BRENT , JOHNSON BRIAN , LEE SEONG-HOON
发明人： LIN FENG , KEETH BRENT , JOHNSON BRIAN , LEE SEONG-HOON
IPC分类号： H04L7/00 , G06F12/16
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C7/222
摘要： A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory device each generates an in-phase strobe signal and a quadrature strobe signal. Command, address or write data signals stored in respective output latches in the memory controller are clocked by the in-phase signals from the internal strobe generator circuit. These command, address or write data signals are latched into input latches in the memory device by the quadrature strobe signal coupled from the memory controller to the memory device. In substantially the same manner, read data signals are coupled from the memory device to the memory controller using the in-phase and quadrature strobe signals generated by the internal strobe generator circuit.
摘要翻译：存储器系统将来自存储器控制器的命令，地址或写入数据信号耦合到存储器设备，并将数据信号从存储器设备读取到存储器控制器。存储器控制器和存储器设备中的每一个中的相应选通脉冲发生器电路均产生同相选通信号和正交选通信号。存储在存储器控制器中的各个输出锁存器中的命令，地址或写入数据信号由来自内部选通脉冲发生器电路的同相信号计时。这些命令，地址或写入数据信号被从存储器控制器耦合到存储器装置的正交选通信号锁存到存储器装置中的输入锁存器中。以基本上相同的方式，使用内部选通脉冲发生器电路产生的同相和正交选通信号将读取数据信号从存储器装置耦合到存储器控制器。

3. 发明申请

WO02099661A2 METHOD AND APPARATUS FOR DETERMINING ACTUAL WRITE LATENCY AND ACCURATELY ALIGNING THE START OF DATA CAPTURE WITH THE ARRIVAL OF DATA AT A MEMORY DEVICE 审中-公开
标题翻译：用于确定实际写入延迟的方法和装置，并精确地按照存储器件中数据到达的数据捕获开始
公开(公告)号：WO02099661A2
公开(公告)日：2002-12-12
申请号：PCT/US0217849
申请日：2002-06-06
申请人： MICRON TECHNOLOGY INC
发明人： JOHNSON BRIAN , KEETH BRENT , MANNING TROY A
IPC分类号： G11C11/407 , G06F12/00 , G06F13/16 , G11C7/10 , G11C11/409 , G06F13/00
CPC分类号： G11C29/028 , G06F13/1694 , G11C7/1072 , G11C7/1078 , G11C7/1093 , G11C11/401 , G11C29/50012 , G11C2207/2254
摘要： A method and apparatus for accurately determining the actual arrival of data at a memory device relative to the write clock to accurately align the start of data capture and the arrival of the data at the memory device is disclosed. The actual time of arrival of data at the inputs to a memory device is determined by sending back-to-back write commands along with the predetermined data pattern to the memory device. The data pattern is stored in a register and any difference between the predicted arrival time of the data and the actual arrival time of the data is determined by logic circuitry. Any determined difference can then be compensated for by delaying the start of the capture of the data at the memory device, thereby accurately aligning the start of the data capture and the arrival of the data at the memory device.
摘要翻译：公开了一种用于准确地确定数据在存储器件相对于写入时钟的实际到达以精确对准数据捕获的开始和数据到达存储器件的方法和装置。将数据到输入到存储器件的实际时间通过与存储器件一起发送背靠背写入命令以及预定数据模式来确定。数据模式存储在寄存器中，数据的预计到达时间与数据的实际到达时间之间的任何差异由逻辑电路确定。然后可以通过延迟在存储器件处捕获数据的开始来补偿任何确定的差异，从而将数据捕获的开始和数据的到达准确地对准在存储器件处。

4. 发明申请

WO0185884A3 PREDICTIVE TIMING CALIBRATION FOR MEMORY DEVICES 审中-公开
标题翻译：用于存储器件的预测时序校准
公开(公告)号：WO0185884A3
公开(公告)日：2002-05-23
申请号：PCT/US0114658
申请日：2001-05-07
申请人： MICRON TECHNOLOGY INC
发明人： KEETH BRENT , JOHNSON BRIAN
IPC分类号： G11C11/407 , G11C7/10 , G11C11/4076 , G06F13/16
CPC分类号： G11C11/4076 , G11C7/1072 , G11C2207/2254
摘要： The present invention provides a unique way of using a 2 bit synchronization pattern to obtain a faster and more reliable calibration of multiple data paths in a memory system. If the 2 bit synchronization pattern is generated with a known clock phase relationship, then the data-to-clock phase alignment can be determined using simple decode logic to predict the next m-bits from a just-detected m-bits. If the succeeding m-bit pattern does not match the predicted pattern, then the current data-to-clock alignment fails for a particular delay value adjustment in the data path undergoing alignment, and the delay in that data path is adjusted to a new value. The invention also ensures that data alignment will occur to a desired edge of the clock signal, e.g., a positive going edge, by forcing a failure of all predicted m-bit patterns which are associated with an undesired edge, e.g., a negative going edge, of the clock signal.
摘要翻译：本发明提供使用2＆lt; N＆gt;位同步模式以获得存储器系统中的多个数据路径的更快更可靠的校准的独特方式。如果以已知的时钟相位关系产生2 位同步模式，则可以使用简单的解码逻辑来确定数据到时钟相位对准，以便从刚刚检测到的m位来预测下一个m位。如果后续的m位模式与预测模式不匹配，则对于经历对准的数据路径中的特定延迟值调整，当前数据对时钟对准失败，并且该数据路径中的延迟被调整到新值。本发明还确保通过强制与不期望的边缘相关联的所有预测的m位模式的故障（例如，正向沿），时钟信号的期望边缘（例如，正向边缘）将发生数据对准的时钟信号。

5. 发明申请

WO2004053879A2 MEMORY DEVICE AND METHOD HAVING LOW-POWER, HIGH WRITE LATENCY MODE AND HIGH-POWER, LOW WRITE LATENCY MODE AND/OR INDEPENDENTLY SELECTABLE WRITE LATENCY 审中-公开
标题翻译：具有低功率，高写入时间模式和大功率，低写入时间模式和/或独立可选择写入时间的存储器件和方法
公开(公告)号：WO2004053879A2
公开(公告)日：2004-06-24
申请号：PCT/US0339187
申请日：2003-12-09
申请人： MICRON TECHNOLOGY INC
发明人： JOHNSON CHRISTOPHER S , JOHNSON BRIAN
IPC分类号： G11C7/10 , G11C
CPC分类号： G11C7/1087 , G11C7/1045 , G11C7/1078 , G11C7/1096 , G11C7/22 , G11C11/4074 , G11C11/4076 , G11C11/4093 , G11C2207/2227
摘要： A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled, a second signal indicative of whether a row of memory cells in the memory device is active, a third signal indicative of whether the memory device is being operated in a power down mode, and a fourth signal indicative of whether read transmitters in the memory device are active. The logic circuit maintains power to the write receivers whenever the high-power, low write latency mode has been enabled if a row of memory cells in the memory device is active, the memory device is not being operated in the power down mode, and the read transmitters in the memory device are not active.
摘要翻译：逻辑电路在动态随机存取存储器件中以低功率模式，高写延迟模式或高功率模式，低写延迟模式操作写接收器。逻辑电路接收指示高功率，低写入等待时间模式是否已经被使能的第一信号，指示存储器装置中的行存储器单元是否有效的第二信号，指示存储器件正在以断电模式操作，并且指示存储器装置中的读取发送器是否有效的第四信号。只要存储器件中的一行存储器单元处于活动状态，存储器件没有在掉电模式下运行，则只要高功率，低写入延迟模式被使能，逻辑电路就保持写入接收器的电力，并且读存储器中的发送器不起作用。

6. 发明申请

WO02073619A9 SYSTEM LATENCY LEVELIZATION FOR READ DATA 审中-公开
标题翻译：用于读取数据的系统延迟级别
公开(公告)号：WO02073619A9
公开(公告)日：2003-12-18
申请号：PCT/US0207226
申请日：2002-03-12
申请人： MICRON TECHNOLOGY INC
发明人： JANZEN JEFFERY W , BRENT KEETH , RYAN KEVIN J , MANNING TROY A , JOHNSON BRIAN
IPC分类号： G06F12/00 , G11C7/10 , G11C7/22 , G11C11/407 , G06F13/42 , G11C7/20 , G11C11/4067 , G11C11/4072 , G11C11/4076
CPC分类号： G11C7/22 , G11C7/1072
摘要： In a high speed memory subsystem differences in each memory device's minimum device read latency and differences in signal propagation time between the memory device and the memory controller can result in widely varying system read latencies. The present invention equalizes the system read latencies of every memory device in a high speed memory system by comparing the differences in system read latencies of each device and then operating each memory device with a device system read latency which causes every device to exhibit the same system read latency.
摘要翻译：在高速存储器子系统中，每个存储器件的最小器件读取延迟和存储器件与存储器控制器之间的信号传播时间差异都会导致系统读取延迟的变化。本发明通过比较每个设备的系统读取延迟的差异，然后用设备系统读取延迟来操作每个存储器设备来均衡每个存储器设备在高速存储器系统中的系统读取延迟，这使得每个设备呈现相同的系统读延迟。

7. 发明申请

WO0217323A3 SYNCHRONIZED WRITE DATA ON A HIGH SPEED MEMORY BUS 审中-公开
标题翻译：在高速存储器总线上同步写入数据
公开(公告)号：WO0217323A3
公开(公告)日：2003-01-30
申请号：PCT/US0125957
申请日：2001-08-21
申请人： MICRON TECHNOLOGY INC
发明人： KEETH BRENT , JOHNSON BRIAN
IPC分类号： G11C11/407 , G06F12/00 , G06F13/16 , G11C7/10 , G11C7/22 , G11C11/4076 , G06F13/28
CPC分类号： G11C7/1084 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/24 , G11C8/20 , G11C11/4076 , G11C11/4078 , G11C16/22
摘要： Some synchronous semiconductor memory devices accept a command clock which is buffered and a write clock which is unbuffered. Write command are synchronized to the command clock while the associated write data is synchronized to the write clock. Due to the use of the buffer, an arbitrary phase shift can exist between the command and write clocks. The presence of the phase shift between the two clocks makes it difficult to determine when a memory device should accept write data associated a write command. A synchronous memory device in accordance with the present invention utilizes the unbuffered strobe signal which is normally tristated during writes as a flag to mark the start of write data. A preamble signal may be asserted on the strobe signal line prior to asserting the flag signal in order to simplify flag detection.
摘要翻译：一些同步半导体存储器件接受缓冲的命令时钟和不缓冲的写时钟。写命令与命令时钟同步，而相关的写数据与写时钟同步。由于使用缓冲器，在命令和写时钟之间可能存在任意的相移。两个时钟之间的相移的存在使得难以确定存储器件何时应该接受与写入命令相关联的写入数据。根据本发明的同步存储器件利用在写入期间正常三态的无缓冲选通信号作为标记写数据开始的标志。在断言标志信号之前，可以在选通信号线上断言前导信号，以简化标志检测。

8. 发明申请

WO2009039953A8 METHOD FOR OPERATING A SHIPPING PROCESS WITHIN A LOGISTICS SYSTEM 审中-公开
标题翻译：在物流系统中运行运输过程的方法
公开(公告)号：WO2009039953A8
公开(公告)日：2009-05-22
申请号：PCT/EP2008007353
申请日：2008-09-09
申请人： DEUTSCHE POST AG , JOHNSON BRIAN
发明人： JOHNSON BRIAN
IPC分类号： G06Q10/00
CPC分类号： G06Q10/08 , G06Q10/0833 , G06Q10/0835
摘要： The invention relates to a method for operating a shipping process within a logistics system as well a to a corresponding logistics system. The method for operating a shipping process within a logistics system with a first client (10) and a shipping station (20) comprising a second client (40), both clients (10, 40) connected to a server (110), wherein a shipment (30) is deposited at the shipping station (20), is characterized by the following steps: receiving identification and/or authentication data on the shipment (30) via the first client (10) and forwarding the data to the server (110), processing the data and preparing a pre-configuration of the shipping process, forwarding the pre-configuration of the shipping process to the second client (40), supplementing the pre-configuration of the shipping process via the second client (40) when the shipment (30) is deposited at the shipping station (20).
摘要翻译：本发明涉及一种用于操作物流系统内的运输过程以及对应的物流系统的方法。一种用于操作物流系统内的运送过程的方法，所述方法包括具有连接到服务器（110）的两个客户端（10,40）的第二客户端（40）的第一客户端（10）和运送站（20），其中装运（30）存放在运送站（20），其特征在于以下步骤：经由第一客户端（10）接收装运（30）上的识别和/或认证数据，并将数据转发到服务器（110））处理所述数据并准备所述装运过程的预配置，将所述装运处理的预配置转发给所述第二客户端（40），以补充所述第二客户端（40）的装运过程的预配置，货物（30）存放在装运站（20）。

9. 发明申请

WO2012151486A3 SYSTEM AND METHOD OF USING MOBILE DEVICES TO PERSONALIZE AND ISSUE PERSONALIZED IDENTIFICATION DOCUMENTS 审中-公开
标题翻译：使用移动设备来个性化和发布个性化身份证明文件的系统和方法
公开(公告)号：WO2012151486A3
公开(公告)日：2013-02-14
申请号：PCT/US2012036520
申请日：2012-05-04
申请人： DATACARD CORP , PHILLIPS KATHLEEN , JOHNSON BRIAN , KAHANA ERAN , MIAFFO YANNICK , BIEHLMANN CHRISTOPHER JACQUES MARIE
发明人： PHILLIPS KATHLEEN , JOHNSON BRIAN , KAHANA ERAN , MIAFFO YANNICK , BIEHLMANN CHRISTOPHER JACQUES MARIE
IPC分类号： G06Q40/02 , G06F9/44
CPC分类号： G06F8/61
摘要： Systems and methods are described that utilize mobile devices that are provided with applications that allow the user of the mobile device to request a personalized identification document from an issuing entity using the user's mobile device. After the issuing entity receives a request for a personalized identification document from the user, the issuing entity issues the personalized identification document to the user. The use of mobile devices in the personalized identification document issuance process is attractive because of their portability, the versatility of their operating systems, and their relatively long battery life. The use of mobile devices permits extraction of a variety of functions that are not available with the use of laptop computers.
摘要翻译：描述了利用移动设备的移动设备的系统和方法，该移动设备具有允许移动设备的用户使用用户的移动设备从发布实体请求个性化标识文档的应用。在发行实体从用户接收到对个性化识别文件的请求之后，发行实体向用户发布个性化识别文件。在个性化身份证件发行过程中使用移动设备因其便携性，操作系统的多功能性以及相对较长的电池寿命而具有吸引力。移动设备的使用允许提取使用膝上型计算机不可用的各种功能。

10. 发明申请

WO2008063571A9 STOWABLE, UNOBTRUSIVE ACCESS AND ESCAPE DEVICES 审中-公开
标题翻译：可扩展的，无障碍的访问和ESCAPE设备
公开(公告)号：WO2008063571A9
公开(公告)日：2008-07-31
申请号：PCT/US2007024098
申请日：2007-11-15
申请人： JOHNSON BRIAN
发明人： JOHNSON BRIAN
IPC分类号： A62B1/20
CPC分类号： A62B1/20 , E06C1/56 , E06C9/14
摘要： To provide another way to exit and/or enter an elevated structure may include alternative access devices. For example, some of the windows on the upper floors of a building may be equipped with devices to allow occupants of those floors to exit and/or enter the building via the window. The devices may be integrated with the building. The alternative access devices also may be used for other applications. For example, the devices may provide access to a structure that is a considerable distance from the ground, such as a tree house or other play structure. The invented access device includes a chute mounted at the top to a pivotal frame mounted, for example near a window or other elevated opening, the chute having a connected or independently deployable step ladder therein and optionally spaced apart support members such as circular, rectangular or oval hoops therearound. The rungs of the step ladder provide a standoff for the webbed material of the chute. Stowage can be in a stowage receptacle mounted to an exterior portion of an elevated structure and deployment can be semi-automatic, reliable and smooth. In accordance with one embodiment of the invention, the access/escape device is hidden within and behind a box-like receptacle on an exterior wall of the building below a window sill. The receptacle generally includes aesthetic elements which closely correspond to aesthetic elements of the structure, rending the receptacle visually unobtrusive and relatively hidden upon casual observation.
摘要翻译：提供退出和/或进入升高的结构的另一种方式可以包括替代的接入设备。例如，建筑物较高楼层的一些窗户可能配备有允许这些楼层的乘客通过窗户离开和/或进入建筑物的设备。设备可以与建筑物集成。替代的接入设备也可以用于其他应用。例如，设备可以提供对距地面相当距离的结构（例如树屋或其他游戏结构）的访问。本发明的进入装置包括安装在顶部的滑道，其安装在例如靠近窗户或其他提升的开口处的枢转框架上，滑槽具有连接或可独立展开的梯级梯子，并且可选地间隔开的支撑构件，例如圆形，矩形或椭圆形环绕在其周围。梯子的梯级为滑槽的网状材料提供了间隔。储存可以放在安装在升高结构的外部部分的装载插座中，部署可以半自动，可靠和平稳。根据本发明的一个实施例，入口/逃生装置被隐藏在建筑物外壁上的箱状容器内和后方，在门窗下方。容器通常包括与结构的美学元件紧密对应的美学元件，使容器视觉上不引人注意并且在偶然观察时相对隐藏。

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