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1. 发明申请

WO2011078917A1 REWRITABLE MEMORY DEVICE WITH MULTI-LEVEL, WRITE-ONCE MEMORY CELLS 审中-公开
标题翻译：具有多级一体化存储器单元的可恢复存储器件
公开(公告)号：WO2011078917A1
公开(公告)日：2011-06-30
申请号：PCT/US2010/055547
申请日：2010-11-05
申请人： SANDISK CORPORATION , SCHEUERLEIN, Roy, E. , FASOLI, Luca
发明人： SCHEUERLEIN, Roy, E. , FASOLI, Luca
IPC分类号： G11C11/56 , G11C16/34 , G11C17/16
CPC分类号： G11C11/5692 , G11C16/349 , G11C17/16 , G11C2211/5641 , G11C2211/5646
摘要： The embodiments described herein are directed to a memory device with multi level, write-once memory cells. In one embodiment, a memory device has a memory array comprising a plurality of multi-level write-once memory cells, wherein each memory cell is programmable to one of a plurality of resistivity levels. The memory device also contains circuitry configured to select a group of memory cells from the memory array, and read a set of flag bits associated with the group of memory cells. The set of flag bits indicate a number of times the group of memory cells has been written to. The circuitry is also configured to select a threshold read level appropriate for the number of times the group of memory cells has been written to, and for each memory cell in the group, read the memory cell as an unprogrammed single-bit memory cell or as a programmed single-bit memory cell based on the selected threshold read level.
摘要翻译：这里描述的实施例涉及具有多级，一次写入存储器单元的存储器件。在一个实施例中，存储器装置具有包括多个多级一次写入存储器单元的存储器阵列，其中每个存储器单元可编程为多个电阻率水平中的一个。存储器件还包含被配置为从存储器阵列中选择一组存储器单元的电路，并且读取与该组存储器单元相关联的一组标志位。该组标志位指示存储器单元组被写入的次数。电路还被配置为选择适合于已经写入存储器单元组的次数的阈值读取电平，并且对于组中的每个存储器单元，读取作为未编程的单位存储器单元的存储器单元或者作为基于所选择的阈值读取电平的编程的单位存储器单元。

2. 发明申请

WO2010080437A3 MEMORY CELL COMPRISING A DIODE CONNECTED TO AT LEAST THREE RESISTIVITY-SWITCHING ELEMENTS AND METHODS OF FABRICATING AND READING THE SAME 审中-公开
标题翻译：包含连接到至少三个电阻开关元件的二极管的存储单元及其制造和读取方法
公开(公告)号：WO2010080437A3
公开(公告)日：2010-09-02
申请号：PCT/US2009068234
申请日：2009-12-16
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E
发明人： SCHEUERLEIN ROY E
IPC分类号： H01L27/02 , G11C13/02 , G11C16/02 , G11C17/16 , H01L27/06 , H01L27/102 , H01L27/24 , H01L27/28 , H01L29/861
CPC分类号： H01L27/1021 , G11C13/0002 , G11C2213/72 , H01L27/0207 , H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L27/2481 , H01L29/1606 , H01L29/861 , H01L29/868
摘要： A non-volatile memory device (100) includes a first electrode (110), a diode steering element (120) at least three resistivity switching storage elements (131,132,133) and a second electrode (151) The diode steering element electrically contacts the first electrode and the at least three resistivity switching storage elements. The second electrode electrically contacts only one of the at least three resistivity switching storage elements.
摘要翻译：非易失性存储器件（100）包括第一电极（110），至少三个电阻率切换存储元件（131,132,133）和第二电极（151）的二极管操纵元件（120）。二极管操作元件电接触第一电极和至少三个电阻率切换存储元件。第二电极只电连接至少三个电阻率开关存储元件中的一个。

3. 发明申请

WO2010080334A1 PROGRAMMING A MEMORY CELL WITH A DIODE IN SERIES BY APPLYING REVERSE BIAS 审中-公开
标题翻译：通过应用反向偏置来编程具有二极管的存储器单元
公开(公告)号：WO2010080334A1
公开(公告)日：2010-07-15
申请号：PCT/US2009/067604
申请日：2009-12-11
申请人： SANDISK 3D LLC , NIAN, Yibo , KUMAR, Tanmay , SCHEUERLEIN, Roy, E.
发明人： NIAN, Yibo , KUMAR, Tanmay , SCHEUERLEIN, Roy, E.
IPC分类号： G11C11/56 , G11C13/00 , G11C16/02 , G11C13/02
CPC分类号： G11C13/0007 , B82Y10/00 , G11C11/5614 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C11/5692 , G11C13/0004 , G11C13/0011 , G11C13/0014 , G11C13/0016 , G11C13/0069 , G11C13/025 , G11C17/16 , G11C17/165 , G11C2013/009 , G11C2213/31 , G11C2213/32 , G11C2213/35 , G11C2213/72
摘要： A method of programming a memory cell comprises applying a reverse bias to the memory cell using a temporary resistor in series with the memory cell. The memory cell comprises a diode and a resistivity switching material element in series. The state of the resistivity switching material element changes from a first initial state to a second state different from the first state.
摘要翻译：一种对存储器单元进行编程的方法包括使用与存储单元串联的临时电阻器向存储单元施加反向偏置。存储单元包括串联的二极管和电阻率切换材料元件。电阻率切换材料元件的状态从第一初始状态变为与第一状态不同的第二状态。

4. 发明申请

WO2010074784A1 THREE-DIMENSIONAL MEMORY STRUCTURES HAVING SHARED PILLAR MEMORY CELLS 审中-公开
标题翻译：具有共享的柱状记忆细胞的三维记忆结构
公开(公告)号：WO2010074784A1
公开(公告)日：2010-07-01
申请号：PCT/US2009/058855
申请日：2009-09-29
申请人： SANDISK 3D LLC , HARARI, Eliyahou , SCHEUERLEIN, Roy, E.
发明人： HARARI, Eliyahou , SCHEUERLEIN, Roy, E.
IPC分类号： G11C13/00 , H01L27/24
CPC分类号： G11C13/0007 , G11C13/0004 , G11C13/0011 , G11C17/16 , G11C2213/19 , G11C2213/32 , G11C2213/34 , G11C2213/35 , G11C2213/52 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/14 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/1675
摘要： A three-dimensional non-volatile memory system is disclosed including a memory array utilizing shared pillar structures for memory cell formation. A shared pillar structure includes two non- volatile storage elements. A first end surface of each pillar contacts one array line from a first set of array lines and a second end surface of each pillar contacts two array lines from a second set of array lines that is vertically separated from the first set of array lines. Each pillar includes a first subset of layers that are divided into portions for the individual storage elements in the pillar. Each pillar includes a second subset of layers that is shared between both non-volatile storage elements formed in the pillar. The individual storage elements each include a steering element and a state change element.
摘要翻译：公开了一种三维非易失性存储器系统，其包括利用用于存储单元形成的共享柱结构的存储器阵列。共享支柱结构包括两个非易失性存储元件。每个柱的第一端表面与第一组阵列线接触一个阵列线，并且每个柱的第二端表面与第二组阵列线接触两个阵列线，所述第二组阵列线与第一组阵列线垂直分离。每个支柱包括被分成用于支柱中的各个存储元件的部分的第一子层子集。每个柱包括在形成在柱中的两个非易失性存储元件之间共享的层的第二子集。各个存储元件各自包括转向元件和状态改变元件。

5. 发明申请

WO2009158676A1 CAPACITIVE DISCHARGE METHOD FOR WRITING TO NON-VOLATILE MEMORY 审中-公开
标题翻译：用于写入非易失性存储器的电容式放电方法
公开(公告)号：WO2009158676A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/048955
申请日：2009-06-26
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E. , FASOLI, Luca, G. , YAN, Tianhong
发明人： SCHEUERLEIN, Roy, E. , FASOLI, Luca, G. , YAN, Tianhong
IPC分类号： G11C13/00 , G11C7/22
CPC分类号： G11C13/0007 , G11C7/12 , G11C7/22 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/71
摘要： A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The circuits for limiting the SET current provide a charge on one or more bit lines that is not sufficient to SET the memory cells, and then discharge the bit lines through the memory cells in order to SET the memory cells.
摘要翻译：存储器系统包括衬底，衬底上的控制电路，包括具有可逆电阻切换元件的多个存储器单元的三维存储器阵列（衬底上方），以及用于限制用于可逆电阻切换的SET电流的电路元素。用于限制SET电流的电路在不足以设置存储器单元的一个或多个位线上提供电荷，然后通过存储器单元放电位线以设置存储器单元。

6. 发明申请

WO2009158670A1 REVERSE SET WITH CURRENT LIMIT FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：随着非易失性存储的电流限制反向设置
公开(公告)号：WO2009158670A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/048945
申请日：2009-06-26
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E. , YAN, Tianhong
发明人： SCHEUERLEIN, Roy, E. , YAN, Tianhong
IPC分类号： G11C13/00
CPC分类号： G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C16/3481 , G11C2013/0078 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72
摘要： A storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The memory cell is SET in a reverse biased fashion.
摘要翻译：存储系统包括衬底，衬底上的控制电路，包括多个可逆电阻开关元件的三维存储器阵列（衬底上方），以及用于限制可逆电阻切换元件的SET电流的电路。以反向偏置的方式对存储器单元进行SET设置。

7. 发明申请

WO2009126492A1 SIDEWALL STRUCTURED SWITCHABLE RESISTOR CELL 审中-公开
标题翻译：小型结构可切换电阻器单元
公开(公告)号：WO2009126492A1
公开(公告)日：2009-10-15
申请号：PCT/US2009/039126
申请日：2009-04-01
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E.
发明人： SCHEUERLEIN, Roy, E.
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L45/04 , H01L27/2409 , H01L27/2418 , H01L27/2463 , H01L45/06 , H01L45/085 , H01L45/124 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/149 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1691
摘要： A method of making a memory device includes forming a first conductive electrode (28), forming an insulating structure (13) over the first conductive electrode, forming a resistivity switching element (14) on a sidewall of the insulating structure, forming a second conductive electrode (26) over the resistivity switching element, and forming a steering element (22) in series with the resistivity switching element between the first conductive electrode and the second conductive electrode, wherein a height of the resistivity switching element in a first direction from the first conductive electrode to the second conductive electrode is greater than a thickness of the resistivity switching element in second direction perpendicular to the first direction.
摘要翻译：一种制造存储器件的方法包括形成第一导电电极（28），在第一导电电极上形成绝缘结构（13），在绝缘结构的侧壁上形成电阻率切换元件（14），形成第二导电电极（26），并且形成与第一导电电极和第二导电电极之间的电阻率切换元件串联的操舵元件（22），其中电阻率切换元件在距第一导电电极第二导电电极的第一导电电极大于电阻率切换元件在垂直于第一方向的第二方向上的厚度。

8. 发明申请

WO2009058177A3 DIGITAL CONTENT KIOSK AND METHODS FOR USE THEREWITH 审中-公开
公开(公告)号：WO2009058177A3
公开(公告)日：2009-05-07
申请号：PCT/US2008/010732
申请日：2008-09-15
申请人： SANDISK CORPORATION , THOMPSON, E., Earle , SCHEUERLEIN, Roy, E. , TOOMBS, Thomas, N. , BARZILAI, Ron , BHATIA, Manish
发明人： THOMPSON, E., Earle , SCHEUERLEIN, Roy, E. , TOOMBS, Thomas, N. , BARZILAI, Ron , BHATIA, Manish
IPC分类号： G06F13/38 , G06K19/077
摘要： A digital content kiosk and methods for use therewith are disclosed. Various embodiments are disclosed relating to exemplary memory devices, memory architectures, and programming techniques that can be used with a digital content kiosk, exemplary mechanical and electrical components of a digital content kiosk, exemplary security aspects of a digital content kiosk, and exemplary uses of a digital content kiosk. Other embodiments are disclosed, and each of these embodiments can be used alone or in combination with one another.

9. 发明申请

WO2008016421A3 MIXED-USE MEMORY ARRAY WITH DIFFERENT DATA STATES AND METHOD FOR USE THEREWITH 审中-公开
标题翻译：具有不同数据状态的混合使用存储器阵列及其使用方法
公开(公告)号：WO2008016421A3
公开(公告)日：2008-05-02
申请号：PCT/US2007013772
申请日：2007-06-12
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , PETTI CHRISTOPHER J
发明人： SCHEUERLEIN ROY E , PETTI CHRISTOPHER J
IPC分类号： G11C11/56 , G11C13/02
CPC分类号： G11C17/165 , G11C11/56 , G11C11/5692 , G11C13/0002 , G11C17/16 , G11C29/76 , G11C2211/5641 , G11C2211/5646 , G11C2213/72
摘要： A mixed-use memory array with different data states and a method for use therewith are disclosed. In one preferred embodiment, a memory array is provided comprising a plurality of memory cells, each memory cell comprising a memory element comprising a switchable resistance material configurable to one of at least three resistivity states. A first set of memory cells uses X resistivity states to represent X respective data states, and a second set of memory cells uses Y resistivity states to represent Y respective data states, wherein X?Y.
摘要翻译：公开了具有不同数据状态的混合使用存储器阵列及其使用方法。在一个优选实施例中，提供了包括多个存储器单元的存储器阵列，每个存储器单元包括存储器元件，存储器元件包括可配置为至少三个电阻率状态中的一个的可切换电阻材料。第一组存储器单元使用X电阻率状态来表示X个相应的数据状态，并且第二组存储器单元使用Y电阻率状态来表示Y个相应的数据状态，其中X≥Y。

10. 发明申请

WO2008016932A2 METHOD AND APPARATUS FOR PASSIVE ELEMENT MEMORY ARRAY INCORPORATING REVERSIBLE POLARITY WORD LINE AND BIT LINE DECODERS 审中-公开
标题翻译：包含可逆极性字线和位线解码器的被动元件存储器阵列的方法和设备
公开(公告)号：WO2008016932A2
公开(公告)日：2008-02-07
申请号：PCT/US2007074883
申请日：2007-07-31
申请人： SANDISK 3D LLC , FASOLI LUCA G , PETTI CHRISTOPHER J , SCHEUERLEIN ROY E
发明人： FASOLI LUCA G , PETTI CHRISTOPHER J , SCHEUERLEIN ROY E
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C8/08 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C17/165
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程和在一些实施例中的可重写无源元件存储器单元的示例性存储器阵列的电路和方法，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。另外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择选定阵列块内的一个或多个字线和位线，用于向选定阵列块内的选定存储器单元传送数据信息并且用于将未选择的偏置条件传送给未选择的阵列块。

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