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1. 发明申请

WO2009158676A1 CAPACITIVE DISCHARGE METHOD FOR WRITING TO NON-VOLATILE MEMORY 审中-公开
标题翻译：用于写入非易失性存储器的电容式放电方法
公开(公告)号：WO2009158676A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/048955
申请日：2009-06-26
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E. , FASOLI, Luca, G. , YAN, Tianhong
发明人： SCHEUERLEIN, Roy, E. , FASOLI, Luca, G. , YAN, Tianhong
IPC分类号： G11C13/00 , G11C7/22
CPC分类号： G11C13/0007 , G11C7/12 , G11C7/22 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/71
摘要： A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The circuits for limiting the SET current provide a charge on one or more bit lines that is not sufficient to SET the memory cells, and then discharge the bit lines through the memory cells in order to SET the memory cells.
摘要翻译：存储器系统包括衬底，衬底上的控制电路，包括具有可逆电阻切换元件的多个存储器单元的三维存储器阵列（衬底上方），以及用于限制用于可逆电阻切换的SET电流的电路元素。用于限制SET电流的电路在不足以设置存储器单元的一个或多个位线上提供电荷，然后通过存储器单元放电位线以设置存储器单元。

2. 发明申请

WO2009158670A1 REVERSE SET WITH CURRENT LIMIT FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：随着非易失性存储的电流限制反向设置
公开(公告)号：WO2009158670A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/048945
申请日：2009-06-26
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E. , YAN, Tianhong
发明人： SCHEUERLEIN, Roy, E. , YAN, Tianhong
IPC分类号： G11C13/00
CPC分类号： G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C16/3481 , G11C2013/0078 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72
摘要： A storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The memory cell is SET in a reverse biased fashion.
摘要翻译：存储系统包括衬底，衬底上的控制电路，包括多个可逆电阻开关元件的三维存储器阵列（衬底上方），以及用于限制可逆电阻切换元件的SET电流的电路。以反向偏置的方式对存储器单元进行SET设置。

3. 发明申请

WO2012148852A1 NON-VOLATILE STORAGE SYSTEM WITH DUAL BLOCK PROGRAMMING 审中-公开
标题翻译：具有双块编程的非易失存储系统
公开(公告)号：WO2012148852A1
公开(公告)日：2012-11-01
申请号：PCT/US2012/034674
申请日：2012-04-23
申请人： SANDISK 3D LLC , YAN, Tianhong , LIU, Tz-yi , SCHEUERLEIN, Roy, E.
发明人： YAN, Tianhong , LIU, Tz-yi , SCHEUERLEIN, Roy, E.
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C5/02 , G11C13/0023 , G11C13/003 , G11C2213/71 , G11C2213/73 , G11C2213/77
摘要： A non-volatile storage system is disclosed that includes a plurality of blocks of non-volatile storage elements, a plurality of word lines connected to the blocks of non-volatile storage elements such that each word line is connected to adjacent blocks of non- volatile storage elements, a plurality of bit lines connected to the blocks of non-volatile storage elements, multiple sets of word lines drivers such that each set of word line drivers is positioned between two adjacent blocks for driving word lines connected to the two adjacent blocks, global data lines, local data lines in selective communication with the bit lines, one or more selection circuits that selectively connect the global data lines to selected local data lines and connect unselected local data lines to one or more unselected bit line signals and control circuitry in communication with the one or more selection circuits and the global data lines. The control circuitry concurrently programs non-volatile storage elements of two adjacent blocks by applying programming signals on word lines connected to the two adjacent blocks and applying programming signals on appropriate bit lines via the global data lines and the one or more selection circuits.
摘要翻译：公开了一种非易失性存储系统，其包括多个非易失性存储元件块，连接到非易失性存储元件的块的多个字线，使得每个字线连接到非易失性存储元件的相邻块存储元件，连接到非易失性存储元件块的多个位线，多组字线驱动器，使得每组字线驱动器位于两个相邻块之间，用于驱动连接到两个相邻块的字线，全局数据线，与位线选择性通信的本地数据线，一个或多个选择电路，其选择性地将全局数据线连接到选定的本地数据线，并将未选择的本地数据线连接到一个或多个未选位线信号和控制电路与一个或多个选择电路和全局数据线的通信。控制电路通过在连接到两个相邻块的字线上应用编程信号并经由全局数据线和一个或多个选择电路在适当的位线上施加编程信号来同时对两个相邻块的非易失性存储元件进行编程。

4. 发明申请

WO2012082654A2 ARCHITECTURE FOR THREE DIMESIONAL NON-VOLATILE STORAGE WITH VERTICAL BIT LINES 审中-公开
标题翻译：具有垂直位线的三维非易失性存储的架构
公开(公告)号：WO2012082654A2
公开(公告)日：2012-06-21
申请号：PCT/US2011/064493
申请日：2011-12-12
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E. , YAN, Tianhong , CERNEA, Raul-Adrian
发明人： SCHEUERLEIN, Roy, E. , YAN, Tianhong , CERNEA, Raul-Adrian
IPC分类号： G11C13/00 , H01L27/24
CPC分类号： G11C13/0033 , G11C5/025 , G11C8/08 , G11C13/0002 , G11C13/0026 , G11C13/0028 , G11C13/0069 , H01L27/0688 , H01L27/115 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/165 , H01L45/1683

5. 发明申请

WO2012067738A1 MEMORY SYSTEM WITH REVERSIBLE RESISTIVITY-SWITCHING USING PULSES OF ALTERNATE POLARITY 审中-公开
标题翻译：具有可逆电阻切换的存储器系统使用备用极性脉冲
公开(公告)号：WO2012067738A1
公开(公告)日：2012-05-24
申请号：PCT/US2011/056130
申请日：2011-10-13
申请人： SANDISK 3D LLC , RABKIN, Peter , SAMACHISA, George , SCHEUERLEIN, Roy, E.
发明人： RABKIN, Peter , SAMACHISA, George , SCHEUERLEIN, Roy, E.
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C2013/0073 , G11C2013/0078 , G11C2013/009 , G11C2013/0092
摘要： A memory system includes a plurality of non-volatile storage elements that each comprise a diode (or other steering device) in series with reversible resistance-switching material. One or more circuits in the memory system program the non-volatile storage elements by changing the reversible resistance-switching material of one or more non-volatile storage elements to a first resistance state. The memory system can also change the reversible resistance-switching material of one or more of the non-volatile storage elements from the first resistance state to a second resistance state by applying one or more pairs of opposite polarity voltage conditions (e.g., pulses) to the respective diodes (or other steering devices) such that current flows in the diodes (or other steering devices) without operating the diodes (or other steering devices) in breakdown condition.
摘要翻译：存储器系统包括多个非易失性存储元件，每个非易失性存储元件包括与可逆电阻切换材料串联的二极管（或其他转向装置）。存储器系统中的一个或多个电路通过将一个或多个非易失性存储元件的可逆电阻切换材料改变为第一电阻状态而对非易失性存储元件进行编程。存储系统还可以将一个或多个非易失性存储元件的可逆电阻切换材料从第一电阻状态改变到第二电阻状态，通过将一对或多对相反极性的电压条件（例如，脉冲）施加到相应的二极管（或其他转向装置）使得电流在二极管（或其他转向装置）中流动，而不会在击穿情况下操作二极管（或其他转向装置）。

6. 发明申请

WO2010123657A1 WRITE METHOD OF A CROSS POINT NON-VOLATILE MEMORY CELL WITH DIODE 审中-公开
标题翻译：具有二极管的交叉点非易失性存储单元的写入方法
公开(公告)号：WO2010123657A1
公开(公告)日：2010-10-28
申请号：PCT/US2010/029186
申请日：2010-03-30
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E.
发明人： SCHEUERLEIN, Roy, E.
IPC分类号： G11C13/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0078 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72
摘要： A memory system includes an X line, a first Y line, a second Y line, a semiconductor region of a first type running along the X line, first switching material and a first semiconductor region of a second type between the first Y line and the semiconductor region of the first type, second switching material and a second semiconductor region of the second type between the second Y line and the semiconductor region of the first type, and control circuitry. The control circuitry is in communication with the X line, the first Y line and the second Y line. The control circuitry changes the programming state of the first switching material to a first state by causing a first current to flow from the second Y line to the first Y line through the first switching material, the second switching material, the semiconductor region of the first type, the first semiconductor region of the second type and the second semiconductor region of the second type.
摘要翻译：存储系统包括X线，第一Y线，第二Y线，沿着X线延伸的第一类型的半导体区域，第一开关材料和第一Y线与第一Y线之间的第二类型的第一半导体区域第一类型的半导体区域，第二开关材料和第二类型的第二类型的第二半导体区域在第二Y线和第一类型的半导体区域之间，以及控制电路。控制电路与X线，第一Y线和第二Y线通信。控制电路通过使第一电流从第二Y线流过第一Y线，通过第一开关材料，第二开关材料，第一开关材料的半导体区域，将第一开关材料的编程状态改变到第一状态第二类型的第一半导体区域和第二类型的第二半导体区域。

7. 发明申请

WO2010005864A1 MEMORY CELL WITH MULTIPLE SERIES PASSIVE ELEMENT FOR THREE-DIMENSIONAL ARRAYS 审中-公开
标题翻译：具有多个系列的存储器单元，用于三维阵列的被动元件
公开(公告)号：WO2010005864A1
公开(公告)日：2010-01-14
申请号：PCT/US2009/049513
申请日：2009-07-02
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E.
发明人： SCHEUERLEIN, Roy, E.
IPC分类号： G11C13/00 , H01L27/24
CPC分类号： G11C13/003 , B82Y10/00 , G11C13/025 , G11C2213/16 , G11C2213/35 , G11C2213/72 , G11C2213/74 , H01L27/2409 , H01L27/2418 , H01L45/04 , H01L45/1233 , H01L45/149
摘要： A nonvolatile memory cell including at least two two-terminal non-linear steering elements arranged in series, and a resistivity switching storage element arranged in series with the at least two two-terminal non-linear steering elements. A memory array, comprising a plurality of the nonvolatile memory cells is also described. A method of forming a nonvolatile memory cell is also described.
摘要翻译：包括串联布置的至少两个两端非线性转向元件的非易失性存储单元和与所述至少两个两端非线性转向元件串联设置的电阻率切换存储元件。还描述了包括多个非易失性存储器单元的存储器阵列。还描述了形成非易失性存储单元的方法。

8. 发明申请

WO2008016948A2 METHOD AND APPARATUS FOR DUAL DATA-DEPENDENT BUSSES FOR COUPLING READ/WRITE CIRCUITS TO A MEMORY ARRAY 审中-公开
标题翻译：用于将读/写电路耦合到存储阵列的双数据相关总线的方法和装置
公开(公告)号：WO2008016948A2
公开(公告)日：2008-02-07
申请号：PCT/US2007/074901
申请日：2007-07-31
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E. , FASOLI, Luca, G.
发明人： SCHEUERLEIN, Roy, E. , FASOLI, Luca, G.
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C8/12 , G11C7/1048 , G11C7/18 , G11C8/08
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。

9. 发明申请

WO2008016421A2 MIXED-USE MEMORY ARRAY WITH DIFFERENT DATA STATES AND METHOD FOR USE THEREWITH 审中-公开
标题翻译：具有不同数据状态的混合使用存储器阵列及其使用方法
公开(公告)号：WO2008016421A2
公开(公告)日：2008-02-07
申请号：PCT/US2007/013772
申请日：2007-06-12
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E. , PETTI, Christopher, J.
发明人： SCHEUERLEIN, Roy, E. , PETTI, Christopher, J.
IPC分类号： G11C13/02
CPC分类号： G11C17/165 , G11C11/56 , G11C11/5692 , G11C13/0002 , G11C17/16 , G11C29/76 , G11C2211/5641 , G11C2211/5646 , G11C2213/72
摘要： A mixed-use memory array with different data states and a method for use therewith are disclosed. In one preferred embodiment, a memory array is provided comprising a plurality of memory cells, each memory cell comprising a memory element comprising a switchable resistance material configurable to one of at least three resistivity states. A first set of memory cells uses X resistivity states to represent X respective data states, and a second set of memory cells uses Y resistivity states to represent Y respective data states, wherein X≠Y.
摘要翻译：公开了具有不同数据状态的混合使用存储器阵列及其使用方法。在一个优选实施例中，提供包括多个存储单元的存储器阵列，每个存储单元包括存储元件，存储元件包括可配置为至少三个电阻率状态之一的可切换电阻材料。第一组存储器单元使用X电阻率状态来表示X个相应的数据状态，并且第二组存储器单元使用Y电阻率状态来表示Y个相应的数据状态，其中X≥Y。

10. 发明申请

WO2006130800A3 REWRITEABLE MEMORY CELL COMPRISING A TRANSISTOR AND RESISTANCE-SWITCHING MATERIAL IN SERIES 审中-公开
公开(公告)号：WO2006130800A3
公开(公告)日：2006-12-07
申请号：PCT/US2006/021372
申请日：2006-06-01
申请人： SANDISK 3D LLC , PETTI, Christopher, J. , SCHEUERLEIN, Roy, E.
发明人： PETTI, Christopher, J. , SCHEUERLEIN, Roy, E.
IPC分类号： H01L27/00 , H01L45/00
摘要： A nonvolatile memory cell is provided, the cell comprising a transistor in series with resistance- switching material, which can be switched between at least two stable resistance states, for example a high-resistance state and a low-resistance state. In preferred embodiments the transistor is a TFT, having a channel region not formed in a monocrystalline wafer substrate. In preferred embodiments the transistor may have' either a vertically oriented ch'annel or a laterally oriented channel. Either embodiment can be formed in a monolithic three dimensional memory array in which multiple memory levels can be formed above a single substrate, forming a highly dense nonvolatile memory array.

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