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    • 3. 发明申请
      WO99021215A2 METHODS OF FORMING POWER SEMICONDUCTOR DEVICES HAVING MERGED SPLIT-WELL BODY REGIONS THEREIN AND DEVICES FORMED THEREBY 审中-公开
    • METHODS OF FORMING POWER SEMICONDUCTOR DEVICES HAVING MERGED SPLIT-WELL BODY REGIONS THEREIN AND DEVICES FORMED THEREBY
    • 用于形成包含单独绝缘外壳的身体区域的融合的半导体功率器件的方法以及由此形成的器件
    • WO99021215A2
    • 1999-04-29
    • PCT/US1998/022041
    • 1998-10-16
    • H01L21/336 , H01L29/08 , H01L29/10 , H01L29/78 , H01L
    • H01L29/66719 , H01L29/0626 , H01L29/0878 , H01L29/1095 , H01L29/66712 , H01L29/7808 , H01L29/7813
    • Methods of forming power semiconductor devices having merged split-well body regions include the steps of forming a semiconductor substrate containing a drift region of first conductivity type (e.g., N-type) therein extending to a first face thereof. First and second split-well body regions of second conductivity type (e.g., P-type) may also be formed at spaced locations in the drift region. First and second source regions of first conductivity type are also formed in the first and second split-well body regions, respectively. A central body/contact region of second conductivity type is also formed in the drift region, at a location intermediate the first and second split-well body regions. The central body/contact region preferably forms non-rectifying junctions with the first and second split-well body regions and a P-N rectifying junction with the drift region at a central junction depth which is less than the maximum well junction depths of the split-well body regions. First and second insulated gate electrodes may also be formed on the first face, opposite respective portions of the first and second split-well regions. Proper choice of drift region resistivity and implant conditions can be used to form preferred dumbbell-shaped body region and move the location of breakdown within the device to a location which facilitates decoupling of device characteristics. A drift region extension of relatively high conductivity can also be provided along the bottom of the central body region to further limit the degree of coupling between device characteristics.
    • 本发明涉及制造功率半导体器件的方法，该功率半导体器件包括分离隔离盒的合并体区。 这些方法包括形成包含延伸到衬底的第一面的第一导电类型（例如，N型）的迁移区的半导体衬底。 通过第二导电类型（例如，P型）隔开的第一和第二隔离箱体也可以在与迁移区隔开的注入处形成。 第一导电类型的第一和第二源极区域也形成在第一和第二分离的隔离盒体区域中。 第二导电类型的中心接触/本体区域也形成在迁移区中，在分离隔离沉箱的第一和第二本体区域之间的中间位置处。 中心接触/本体区域优选与分离的隔离箱的第一和第二本体区域形成非直线接合部，并且PN接合部接合部具有在较低接合中心深度处的移动区域。 在分开的沉箱的身体区域的最大深度处。 第一绝缘栅电极和第二绝缘栅电极也可以形成在分离隔离沉箱的第一主体区域和第二主体区域的相应相对部分的第一面上。 迁移区的植入和电阻率条件的适当选择可用于形成哑铃体的优选区域并将装置的分解区的植入移动到植入物， 解耦所述装置的特性。 还可以沿着中央主体区域形成相对高电导率的迁移区延伸，以进一步限制装置的特征之间的耦合程度。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 7. 发明申请
      WO0072372A8 TRENCH SEMICONDUCTOR DEVICE HAVING GATE OXIDE LAYER WITH MULTIPLE THICKNESSES AND PROCESSES OF FABRICATING THE SAME 审中-公开
    • TRENCH SEMICONDUCTOR DEVICE HAVING GATE OXIDE LAYER WITH MULTIPLE THICKNESSES AND PROCESSES OF FABRICATING THE SAME
    • 具有多个厚度的栅极氧化物层的半导体器件及其制造方法
    • WO0072372A8
    • 2002-09-26
    • PCT/US0014363
    • 2000-05-24
    • WILLIAMS RICHARD K , GRABOWSKI WAYNE B
    • WILLIAMS RICHARD K , GRABOWSKI WAYNE B
    • H01L21/336 , H01L21/76 , H01L21/8242 , H01L29/08 , H01L29/10 , H01L29/423 , H01L29/78
    • H01L29/42368 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/4232 , H01L29/4238 , H01L29/66734 , H01L29/7397 , H01L29/7808 , H01L29/7811 , H01L29/7813 , H01L29/7828 , H01L29/8083
    • A trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench (250) is diminished by increasing the thickness of the gate oxide layer (244) at the bottom of the trench (250). Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide (272) is performed after a trench (268) has been etched, yielding a thick oxide layer (270) at the bottom of the trench (268). Any oxide which deposites on the walls of the trench (268) is removed before a thin gate oxide layer (276) is grown on the walls. The trench (268) is then filled with polysilicon (278) in one or more stages. In a variation of the process a small amount of photoresist (310) is deposited on an oxide (270) at the bottom of the trench (268) before the walls of the trench (268) are etched. Alternatively, polysilicon (320) can be deposited in a trench (268) and etched back until only a portion (322) remains at the bottom of the trench (268). The polysilicon (320) is then oxided and the trench (268) is filled with polysilicon. The processes can be combined, with a directional deposition of oxide being followed by a filling and oxidation of polysilicon. A process of forming a "keyhole" shaped gate electrode (634) includes depositing polysilicon at the bottom of the trench (606), oxidizing the top surface of the polysilicon, etching the oxided polysilicon, and filling the trench (606) with polysilicon.
    • 诸如功率MOSFET的沟槽半导体器件通过增加沟槽（250）底部的栅极氧化物层（244）的厚度来减小沟槽（250）拐角处的高电场。 描述了用于制造这种设备的几个过程。 在一组工艺中，在蚀刻了沟槽（268）之后进行氧化硅（272）的定向沉积，在沟槽（268）的底部产生厚的氧化物层（270）。 在薄壁氧化层（276）生长在壁上之前，去除沉积在沟槽（268）的壁上的任何氧化物。 然后在一个或多个阶段中，用多晶硅（278）填充沟槽（268）。 在该过程的变化中，在蚀刻沟槽（268）的壁之前，在沟槽（268）的底部的氧化物（270）上沉积少量的光致抗蚀剂（310）。 或者，多晶硅（320）可以沉积在沟槽（268）中并被回蚀，直到只有一部分（322）保留在沟槽（268）的底部。 然后氧化多晶硅（320），并且沟槽（268）被多晶硅填充。 该方法可以组合，随着氧化物的定向沉积，随后是多晶硅的填充和氧化。 形成“键孔”形栅电极（634）的过程包括在沟槽（606）的底部沉积多晶硅，氧化多晶硅的顶表面，蚀刻氧化多晶硅，以及用多晶硅填充沟槽（606）。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 8. 发明申请
      WO01067520A1 SEMICONDUCTOR DEVICE 审中-公开
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • WO01067520A1
    • 2001-09-13
    • PCT/JP2001/001672
    • 2001-03-05
    • H01L27/04 , H01L21/336 , H01L21/822 , H01L27/02 , H01L27/06 , H01L29/06 , H01L29/739 , H01L29/78
    • H01L29/66712 , H01L27/0255 , H01L27/0629 , H01L29/0619 , H01L29/7808 , H01L29/7811 , H01L2924/0002 , H01L2924/00
    • A semiconductor device includes a plurality of transistor cells (T) formed on a semiconductor layer (4). P-type rings (1b) and n-type rings (1a) of polysilicon are alternately formed on an insulating layer (6) outside the transistor cells (T) (toward chip edges) to form a protective diode (1). The protective diode (1) has a ringlike gate connection (2) of metal such as aluminum on its outermost side, and a metallic source connection on its innermost side. The protective diode (1) is connected between gate and source. The semiconductor device has a smaller chip size and utilizes vacant chip areas toward the border to form a protective diode that has a sufficiently low series resistance and functions satisfactorily.
    • 半导体器件包括形成在半导体层（4）上的多个晶体管单元（T）。 多晶硅的P型环（1b）和n型环（1a）交替地形成在晶体管单元（T）外侧（朝向芯片边缘）的绝缘层（6）上，形成保护二极管（1）。 保护二极管（1）在其最外侧具有诸如铝的金属的环状栅极连接（2），在其最内侧具有金属源极连接。 保护二极管（1）连接在栅极和源极之间。 半导体器件具有更小的芯片尺寸，并且利用朝向边界的空芯片区域形成具有足够低的串联电阻并令人满意地起作用的保护二极管。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 10. 发明申请
      WO9921215A3 METHODS OF FORMING POWER SEMICONDUCTOR DEVICES HAVING MERGED SPLIT-WELL BODY REGIONS THEREIN AND DEVICES FORMED THEREBY 审中-公开
    • METHODS OF FORMING POWER SEMICONDUCTOR DEVICES HAVING MERGED SPLIT-WELL BODY REGIONS THEREIN AND DEVICES FORMED THEREBY
    • 形成功能半导体器件的方法，其具有合并的分离的壳体区域及其形成的器件
    • WO9921215A3
    • 1999-10-14
    • PCT/US9822041
    • 1998-10-16
    • HARRIS CORP
    • ZENG JUN , WHEATLEY CARL FRANKLIN
    • H01L21/336 , H01L29/08 , H01L29/10 , H01L29/78
    • H01L29/66719 , H01L29/0626 , H01L29/0878 , H01L29/1095 , H01L29/66712 , H01L29/7808 , H01L29/7813
    • Methods of forming power semiconductor devices having merged split-well body regions include the steps of forming a semiconductor substrate containing a drift region of first conductivity type (e.g., N-type) therein extending to a first face thereof. First and second split-well body regions of second conductivity type (e.g., P-type) may also be formed at spaced locations in the drift region. First and second source regions of first conductivity type are also formed in the first and second split-well body regions, respectively. A central body/contact region of second conductivity type is also formed in the drift region, at a location intermediate the first and second split-well body regions. The central body/contact region preferably forms non-rectifying junctions with the first and second split-well body regions and a P-N rectifying junction with the drift region at a central junction depth which is less than the maximum well junction depths of the split-well body regions. First and second insulated gate electrodes may also be formed on the first face, opposite respective portions of the first and second split-well regions. Proper choice of drift region resistivity and implant conditions can be used to form preferred dumbbell-shaped body region and move the location of breakdown within the device to a location which facilitates decoupling of device characteristics. A drift region extension of relatively high conductivity can also be provided along the bottom of the central body region to further limit the degree of coupling between device characteristics.
    • 形成具有合并的分裂井体区域的功率半导体器件的方法包括以下步骤：在其第一面上形成包含第一导电类型（例如N型）的漂移区的半导体衬底。 第二导电类型的第一和第二分裂井体区域（例如P型）也可以形成在漂移区域中的间隔位置处。 第一导电类型的第一和第二源极区域也分别形成在第一和第二分裂阱体区域中。 第二导电类型的中心体/接触区域也形成在漂移区域中，在第一和第二分裂井体区域的中间位置处。 中心体/接触区域优选地与第一和第二分裂井体区域形成非整流结，以及在中心结深度处的漂移区域的PN整流结，其小于分裂井的最大井结深度 身体区域。 第一和第二绝缘栅极电极也可以形成在第一面上，与第一和第二分裂阱区域的相应部分相对。 漂移区电阻率和植入条件的适当选择可用于形成优选的哑铃形身体区域并将装置内的击穿位置移动到有利于器件特性解耦的位置。 还可以沿着中心体区域的底部提供相对高的导电性的漂移区域延伸，以进一步限制器件特性之间的耦合程度。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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