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1. 发明申请

WO2010061244A1 POWER MOS TRANSISTOR DEVICE AND SWITCH APPARATUS COMPRISING THE SAME 审中-公开
标题翻译：功率MOS晶体管器件和包括其的开关装置
公开(公告)号：WO2010061244A1
公开(公告)日：2010-06-03
申请号：PCT/IB2008/055655
申请日：2008-11-27
申请人： FREESCALE SEMICONDUCTOR, INC. , REYNES, Jean Michel , BERNOUX, Beatrice , ESCOFFIER, Rene , JALBAUD, Pierre , DERAM, Ivana
发明人： REYNES, Jean Michel , BERNOUX, Beatrice , ESCOFFIER, Rene , JALBAUD, Pierre , DERAM, Ivana
IPC分类号： H01L29/78 , H01L29/10 , H01L29/06 , H01L23/485
CPC分类号： H01L29/7808 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L29/0696 , H01L29/1095 , H01L29/7802 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/45014 , H01L2224/45124 , H01L2224/4813 , H01L2224/48137 , H01L2224/4847 , H01L2224/49171 , H01L2924/01005 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/12036 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00014
摘要： A transistor power switch device (700) comprising an array of vertical transistor elements (108) for carrying current between the first and second faces (104, 106) of a semiconductor body, the array of transistor elements (108) comprising at the first face (104) an array of source regions (114) of a first semiconductor type, at least one p region (122, 124, 126) of a second semiconductor type opposite to the first type interposed between the source regions (114) and the second face (106), and at least one control electrode (116) for switchably controlling flow of the current through the p region (122, 124, 126), and a conductive layer (110) contacting the source regions (114) and insulated from the control electrode (116) by at least one insulating layer (120). The switch device also comprises at least one reverse biased vertical avalanche diode (702) electrically in parallel with the array of transistors (108) for conducting breakdown current between the first and second faces (104, 106) in the off state of the device and having a first current carrying diode region (704) of the second semiconductor type in contact with the first face (104) and with the conductive layer (110) and a second semiconductor region (706) of the first semiconductor type electrically connected with the second face (106). The switch device also comprises electrical connection leads (128) bonded to the conductive layer (110) over each avalanche diode.
摘要翻译：一种晶体管功率开关装置（700），包括用于在半导体主体的第一和第二面（104,106）之间承载电流的垂直晶体管元件阵列（108），所述晶体管元件阵列（108）包括在第一面（104）第一半导体类型的源极区域（114）的阵列，插入在源极区域（114）和第二半导体区域（114）之间的与第一类型相反的第二半导体类型的至少一个p区域（122,124,126）面（106）和至少一个控制电极（116），用于可转换地控制通过该p区（122,124,126）的电流的流动，以及与该源极区（114）接触的导电层（110）所述控制电极（116）由至少一个绝缘层（120）构成。开关装置还包括与晶体管阵列（108）电并联的至少一个反向偏置垂直雪崩二极管（702），用于在器件的断开状态下在第一和第二面（104,106）之间传导击穿电流，以及具有与第一面（104）接触的第二半导体类型的第一载流二极管区域（704）和导电层（110）以及与第二半导体类型的第二半导体类型电连接的第二半导体区域（706）脸（106）。开关装置还包括在每个雪崩二极管上结合到导电层（110）的电连接引线（128）。

2. 发明申请

WO2010061245A1 POWER MOS TRANSISTOR DEVICE 审中-公开
标题翻译：功率MOS晶体管器件
公开(公告)号：WO2010061245A1
公开(公告)日：2010-06-03
申请号：PCT/IB2008/055656
申请日：2008-11-27
申请人： FREESCALE SEMICONDUCTOR, INC. , REYNES, Jean Michel , BERNOUX, Beatrice , ESCOFFIER, Rene , JALBAUD, Pierre , DERAM, Ivana
发明人： REYNES, Jean Michel , BERNOUX, Beatrice , ESCOFFIER, Rene , JALBAUD, Pierre , DERAM, Ivana
IPC分类号： H01L29/78 , H01L29/10 , H01L29/06 , H01L23/485
CPC分类号： H01L29/7808 , H01L24/02 , H01L24/05 , H01L29/0696 , H01L29/1095 , H01L29/7802 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/4813 , H01L2224/4847 , H01L2224/49171 , H01L2924/01079 , H01L2924/12036 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/30107 , H01L2924/3011 , H01L2924/00015 , H01L2924/00
摘要： A transistor power switch device (400, 700) comprising a semiconductor body (101 ) presenting opposite first and second faces (104, 106), the switch device comprising an array of vertical field-effect transistor elements (108) for carrying current between the first and second faces (104, 106), the array of transistor elements (108) comprising at the first face (104) an array of source regions (114) of a first semiconductor type, at least one body region (122, 124, 126) of a second semiconductor type opposite to the first type interposed between the source regions (114) and the second face (106), and at least one control electrode (116) for switchably controlling flow of the current through the second transistor region (122, 124, 126), and a conductive layer (1 10) contacting the source regions (114) and insulated from the control electrode (116) by at least one insulating layer (120, 121 ). The source region (114) of each of the vertical transistor elements (108) contacting the conductive layer (1 10) comprises a plurality of arms extending radially at the first face (104) towards an arm of a source region (114) of an adjacent vertical transistor element (108) of the array, the at least one body region (122, 124, 126) extending around and under the arms of the source regions (114) and extending up within each of the source regions to contact the conductive layer (110) at the first face (104) at a contact position (402) adjacent an end of each of the arms of the source regions (114).
摘要翻译：一种晶体管功率开关装置（400,700），包括呈现相对的第一和第二面（104,106）的半导体本体（101），所述开关装置包括一组垂直场效应晶体管元件（108），用于承载第一和第二面（104,106），所述晶体管元件阵列（108）在所述第一面（104）处包括第一半导体类型的源极区域（114）的阵列，至少一个体区（122,124， 126）与插入在源区（114）和第二面（106）之间的第一类型相反的第二半导体类型，以及用于可切换地控制流过第二晶体管区域的电流的至少一个控制电极（116） 122，124,126）和通过至少一个绝缘层（120,121）与源极区域（114）接触并与控制电极（116）绝缘的导电层（110）。每个垂直晶体管元件（108）的与导电层（110）接触的源极区域（114）包括多个臂，其在第一面（104）处径向延伸朝向源极区域（114）的臂所述阵列的相邻的垂直晶体管元件（108），所述至少一个主体区域（122,124,126）在所述源极区域（114）的臂周围和下方延伸并且在每个源极区域内向上延伸以接触所述导电在与源区域（114）的每个臂的端部相邻的接触位置（402）处在第一面（104）处的层（110）。

3. 发明申请

WO2006024322A1 POWER SEMICONDUCTOR DEVICE 审中-公开
标题翻译：功率半导体器件
公开(公告)号：WO2006024322A1
公开(公告)日：2006-03-09
申请号：PCT/EP2004/011074
申请日：2004-08-31
申请人： FREESCALE SEMICONDUCTOR, INC. , REYNES, Jean-Michel , ALVES, Stéphane , DERAM, Ivana , LOPES, Blandino , MARGHERITTA, Joël , MORANCHO, Frédéric
发明人： REYNES, Jean-Michel , ALVES, Stéphane , DERAM, Ivana , LOPES, Blandino , MARGHERITTA, Joël , MORANCHO, Frédéric
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/0878
摘要： A power semiconductor device comprising an array of cells distributed over a surface of a substrate (62), the source regions (37) of the individual cells of the array comprising a plurality of source region branches (80) each extending laterally outwards towards at least one source region branch (80) of an adjacent cell and presenting juxtaposed ends, the base regions (36) of the individual cells of the array comprising a corresponding plurality of base region branches merging together adjacent and between the juxtaposed ends of the source region branches (80) to form a single base region surrounding the source regions (37) of the individual cells of the array in the substrate. The junctions between the merged base region (36) and the drain region are solely concave laterally and define rounded current conduction path areas (39) for the on-state of the device between adjacent cells that are depleted in the off-state of the device to block flow of current from the source regions (37) to the drain electrode (83). Floating voltage regions (102) of opposite conductivity type to the drain region are buried in the substrate (62) beneath the merged base region (36) and present features (104) corresponding to and juxtaposed with features of the merged base region (36) in each cell so that the voltage of the floating voltage regions (102) tends to the voltage of the source regions (37) when depletion layers blocking the current conduction paths reach the floating voltage regions (102), whereby to enhance the development of the depletion layers. The features (104) of the floating voltage regions define rings of the opposite conductivity type to the drain region that surround the current conduction paths (39) of respective cells. The floating voltage regions (102) include respective islands (106) situated within the current conduction paths (39).
摘要翻译：一种功率半导体器件，包括分布在衬底（62）的表面上的电池阵列，所述阵列的各个单元的源极区（37）包括多个源极区分支（80），每个源极区分支（80）至少横向向外延伸相邻单元的一个源区域分支（80）并且呈现并置端，阵列的各个单元的基区（36）包括相邻的多个基本区域分支，所述多个基本区域分支在源区域分支的并置端（80）以形成围绕衬底中的阵列的各个单元的源极区域（37）的单个基极区域。合并的基极区域（36）和漏极区域之间的结点仅仅是侧向凹入的，并且限定用于在器件截止状态下耗尽的相邻单元之间的器件导通状态的圆形电流传导路径区域（39）阻止从源极区域（37）到漏电极（83）的电流。与漏极区相反的导电类型的浮动电压区域（102）被埋在合并的基极区域（36）下面的衬底（62）中，并且呈现与合并的基极区域（36）的特征对应并并置的特征（104）在每个单元中，当阻挡电流传导路径的耗尽层到达浮动电压区域（102）时，浮动电压区域（102）的电压趋向于源极区域（37）的电压，由此，耗尽层。浮动电压区域的特征（104）限定环绕相应电池的电流传导路径（39）的漏极区域的相反导电类型的环。浮动电压区域（102）包括位于电流传导路径（39）内的各自的岛（106）。

4. 发明申请

WO2008084278A1 SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件及形成半导体器件的方法
公开(公告)号：WO2008084278A1
公开(公告)日：2008-07-17
申请号：PCT/IB2007/000582
申请日：2007-01-10
申请人： FREESCALE SEMICONDUCTOR, INC. , EVGUENIY, Stefanov N , DERAM, Ivana , REYNES, Jean-Michel
发明人： EVGUENIY, Stefanov N , DERAM, Ivana , REYNES, Jean-Michel
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06 , H01L29/423
CPC分类号： H01L29/66719 , H01L29/0623 , H01L29/0634 , H01L29/42372 , H01L29/66712 , H01L29/7395 , H01L29/7811 , H01L29/8083
摘要： A method of forming a semiconductor device having an active area (2) and a termination area (3) surrounding the active area comprises providing a semiconductor substrate (4), providing a semiconductor layer (6) of a first conductivity type over the semiconductor substrate and forming a mask layer (52) over the semiconductor layer. The mask layer (52) outlines at least two portions (54, 56) of a surface of the semiconductor layer: a first outlined portion (54) outlining a floating region (8) in the active area (2) and a second outlined portion (56) outlining a termination region (12) in the termination area (3). Dopants of a second conductivity type are provided to the first (54) and second (56) outlined portions so as to provide a floating region (8) of the second conductivity type buried in the semiconductor layer (6) in the active area (2) and a first termination region (12) of the second conductivity type buried in the semiconductor layer (6) in the termination area (3) of the semiconductor device.
摘要翻译：形成具有有源区域（2）和围绕有源区域的端接区域（3）的半导体器件的方法包括提供半导体衬底（4），在半导体衬底上提供第一导电类型的半导体层（6）以及在所述半导体层上形成掩模层（52）。掩模层（52）概述半导体层的表面的至少两个部分（54,56）：概述有源区域（2）中的浮动区域（8）的第一轮廓部分（54）和第二轮廓部分（56）概述了终止区域（3）中的终止区域（12）。第二导电类型的掺杂剂被提供给第一（54）和第二（56）轮廓部分，以便提供掩埋在有源区域（2）中的半导体层（6）中的第二导电类型的浮动区域（8））和埋在半导体器件的端接区域（3）中的半导体层（6）中的第二导电类型的第一端接区域（12）。

5. 发明申请

WO2003107432A1 POWER SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：功率半导体器件及其制造方法
公开(公告)号：WO2003107432A1
公开(公告)日：2003-12-24
申请号：PCT/EP2003/006117
申请日：2003-06-10
申请人： MOTOROLA INC , REYNES, Jean-Michel , DERAM, Ivana , DELOUME, Pascal
发明人： REYNES, Jean-Michel , DERAM, Ivana , DELOUME, Pascal
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L29/0696
摘要： A low on-state resistance power semiconductor device has a shape and an arrangement that increase the channel density and the breakdown voltage. The power semiconductor device comprises a plurality of individual cells formed on a semiconductor substrate (62). Each individual cell comprises a plurality of radially extending branches (80) having source regions (37) within base regions (36). The plurality of individual cells are arranged such that at least one branch of each cell extends towards at least one branch of an adjacent cell and wherein the base region (36) of the extending branches merge together to form a single and substantially uniformly doped base region (36) surrounding drain islands (39) at the surface of the semiconductor substrate (62).
摘要翻译：低导通电阻功率半导体器件具有增加沟道密度和击穿电压的形状和布置。功率半导体器件包括形成在半导体衬底（62）上的多个单独电池。每个单个电池包括在基极区域（36）内具有源极区（37）的多个径向延伸的分支（80）。多个单个单元布置成使得每个单元的至少一个分支朝向相邻单元的至少一个分支延伸，并且其中延伸分支的基极区域（36）合并在一起以形成单个且基本均匀掺杂的基极区域（36）围绕在半导体衬底（62）的表面处的漏极岛（39）。

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