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1. 发明申请

WO2010117914A1 THREE-DIMENSIONAL ARRAY OF RE-PROGRAMMABLE NON-VOLATILE MEMORY ELEMENTS HAVING VERTICAL BIT LINES AND A SINGLE-SIDED WORD LINE ARCHITECTURE 审中-公开
标题翻译：具有垂直位线和单面字线结构的可重新编程的非易失性存储器元件的三维阵列
公开(公告)号：WO2010117914A1
公开(公告)日：2010-10-14
申请号：PCT/US2010/029857
申请日：2010-04-02
申请人： SANDISK 3D LLC , SAMACHISA, George , YAN, Tianhong
发明人： SAMACHISA, George , YAN, Tianhong
IPC分类号： G11C8/14 , G11C13/00 , G11C7/18 , H01L27/24
CPC分类号： G11C13/0007 , G11C7/18 , G11C8/14 , G11C13/0028 , G11C13/0064 , G11C13/0069 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/77 , H01L27/2436 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/142 , H01L45/143 , H01L45/146 , H01L45/148 , H01L45/149
摘要： A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.
摘要翻译：特别适用于响应于在其上施加电压差而可逆地改变电导水平的存储元件的三维阵列。存储元件跨越位于半导体衬底上方不同距离的多个平面形成。所有平面的存储元件连接到的位线的二维阵列从衬底垂直定向并穿过多个平面。单面字线架构为每行存储器元件专门提供字线，而不是在两行存储器元件之间共享一个字线，从而避免跨越字线跨越阵列链接存储元件。虽然存储器元件行也被对应的局部位线行访问，但是在局部位线的相邻行之间没有扩展耦合，因此没有扩展超出字线的漏电流。

2. 发明申请

WO2011156343A2 NON-VOLATILE MEMORY HAVING 3D ARRAY OF READ/WRITE ELEMENTS AND READ/WRITE CIRCUITS AND METHOD THEREOF 审中-公开
标题翻译：具有读取/写入元件的3D阵列的非易失性存储器及其读取/写入电路及其方法
公开(公告)号：WO2011156343A2
公开(公告)日：2011-12-15
申请号：PCT/US2011/039405
申请日：2011-06-07
申请人： SANDISK 3D LLC , SAMACHISA, George , FASOLI, Luca , LI, Yan , YAN, Tianhong
发明人： SAMACHISA, George , FASOLI, Luca , LI, Yan , YAN, Tianhong
IPC分类号： G11C11/16 , G11C13/02
CPC分类号： G11C13/0069 , G11C13/0007 , G11C13/004 , G11C13/0097 , G11C16/06 , G11C2013/0054 , G11C2213/32 , G11C2213/71 , G11C2213/77 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148 , H01L45/149 , H01L45/1675
摘要： A three-dimensional array is especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. During sensing, to compensate for word line resistance, a sense amplifier references a stored reference value during sensing of a memory element at a given location of the word line. A layout with a row of sense amplifiers between two memory arrays is provided to facilitate the referencing. A selected memory element is reset without resetting neighboring ones when it is subject to a bias voltage under predetermined conditions.
摘要翻译：三维阵列特别适合于响应于在其上施加电压差而可逆地改变电导水平的存储器元件。存储元件跨越位于半导体衬底上方不同距离的多个平面形成。所有平面的存储元件连接到的位线的二维阵列从衬底垂直定向并穿过多个平面。在感测期间，为了补偿字线电阻，读出放大器在对字线的给定位置处的存储元件的感测期间参考存储的参考值。提供了在两个存储器阵列之间具有一行读出放大器的布局以便于参考。当在预定条件下经受偏置电压时，选择的存储元件被复位而不重置相邻的存储元件。

3. 发明申请

WO2012118618A1 THREE DIMENSIONAL MEMORY SYSTEM WITH COLUMN PIPELINE 审中-公开
标题翻译：具有柱管的三维存储系统
公开(公告)号：WO2012118618A1
公开(公告)日：2012-09-07
申请号：PCT/US2012/025171
申请日：2012-02-15
申请人： SANDISK 3D LLC , YAN, Tianhong , BALAKRISHNAN, Gopinath , LEE, Jeffrey, Koon Yee , LIU, Tz-yi
发明人： YAN, Tianhong , BALAKRISHNAN, Gopinath , LEE, Jeffrey, Koon Yee , LIU, Tz-yi
IPC分类号： G11C7/10 , G11C7/18 , G11C13/00 , G11C17/16
CPC分类号： G11C7/1006 , G11C7/1012 , G11C7/1039 , G11C7/18 , G11C8/08 , G11C8/18 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/0069 , G11C17/16
摘要： A monolithic three dimensional array of non-volatile storage elements is arranged in blocks. The non-volatile storage elements are connected to bit lines and word lines. The bit lines for each block are grouped into columns of bit lines. The columns of bit lines include top columns of bit lines that are connected to selection circuits on a top side of a respective block and bottom columns of bit lines that are connected to selection circuits on a bottom side of the respective block. Programming of data is pipelined between two or more columns of bit lines in order to increase programming speed. One embodiment of the programming process includes selectively connecting two columns of bit lines to a set of one or more selection circuits, using the one or more selection circuits to selectively connect one of the two columns of bit lines to one or more signal sources, programming non-volatile storage elements for the column of bit lines that is currently connected to the one or more signal sources, and changing one of the columns of bit lines connected to the set of one or more selection circuits while another column of bit lines is being programmed.
摘要翻译：非易失性存储元件的单片三维阵列以块状排列。非易失性存储元件连接到位线和字线。每个块的位线被分组成位线列。位线列包括连接到相应块的顶侧上的选择电路的顶列和位于相应块的底侧上的选择电路的位线的底列。数据的编程在两列或更多列的位线之间流水线化，以提高编程速度。编程过程的一个实施例包括使用一个或多个选择电路选择性地将两列位线连接到一组或多个选择电路，以选择性地将两列位线中的一列连接到一个或多个信号源，编程用于当前连接到一个或多个信号源的位线列的非易失性存储元件，以及改变连接到一组或多个选择电路的位线的列之一，而另一列位线正在被程序。

4. 发明申请

WO2010042354A1 CONTINUOUS PROGRAMMING OF RESISTIVE MEMORY USING STAGGERED PRECHARGE 审中-公开
标题翻译：使用STAGGERED PRECHARGE连续编程电阻记忆
公开(公告)号：WO2010042354A1
公开(公告)日：2010-04-15
申请号：PCT/US2009/058890
申请日：2009-09-29
申请人： SANDISK 3D LLC , FASOLI, Luca , YAN, Tianhong
发明人： FASOLI, Luca , YAN, Tianhong
IPC分类号： G11C7/12 , G11C13/00
CPC分类号： G11C7/1078 , G11C7/12 , G11C13/0007 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72
摘要： A non-volatile storage system connects a signal driver to a first control line that is connected to a first non-volatile storage element, charges the first control line using the signal driver while the signal driver is connected to the first control line, disconnects the signal driver from the first control line while the first control line remains charged from the signal driver, connects the signal driver to a second control line that is connected to a second non-volatile storage element, charges the second control line using the signal driver while the signal driver is connected to the second control line, and disconnects the signal driver from the second control line. Charging the control lines causes the respective non-volatile storage elements to experience a program operation. The disconnecting of the signal driver from the first control line, the connecting the signal driver to the second control line and the charging of the second control line are performed without waiting for the first non- volatile storage element's program operation to complete.
摘要翻译：非易失性存储系统将信号驱动器连接到连接到第一非易失性存储元件的第一控制线，当信号驱动器连接到第一控制线时，使用信号驱动器对第一控制线充电，断开信号驱动器，而第一控制线保持从信号驱动器充电，将信号驱动器连接到连接到第二非易失性存储元件的第二控制线，使用信号驱动器对第二控制线进行充电，同时信号驱动器连接到第二控制线，并且将信号驱动器与第二控制线断开。对控制线进行充电导致相应的非易失性存储元件经历程序操作。在不等待第一非易失性存储元件的程序操作完成的情况下，执行信号驱动器与第一控制线的断开，将信号驱动器连接到第二控制线和第二控制线的充电。

5. 发明申请

WO2009158673A1 SIMULTANEOUS WRITE AND VERIFY IN A NON-VOLATILE STORAGE 审中-公开
标题翻译：在非易失性存储中同时写入和验证
公开(公告)号：WO2009158673A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/048951
申请日：2009-06-26
申请人： SANDISK 3D LLC , FASOLI, Luca, G. , YAN, Tianhong , LEE, Jeffrey Koon, Yee
发明人： FASOLI, Luca, G. , YAN, Tianhong , LEE, Jeffrey Koon, Yee
IPC分类号： G11C13/00
CPC分类号： G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C16/3481 , G11C2013/0066 , G11C2213/32 , G11C2213/72
摘要： A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and a circuit for detecting the setting and resetting of the reversible resistance-switching elements.
摘要翻译：存储器系统包括衬底，衬底上的控制电路，包括具有可逆电阻切换元件的多个存储单元的三维存储器阵列（衬底上方），以及用于检测可逆电阻的设置和复位的电路开关元件

6. 发明申请

WO2010123517A1 MEMORY SYSTEM WITH DATA LINE SWITCHING SCHEME 审中-公开
标题翻译：具有数据线切换方案的存储器系统
公开(公告)号：WO2010123517A1
公开(公告)日：2010-10-28
申请号：PCT/US2009/058889
申请日：2009-09-29
申请人： SANDISK 3D LLC , YAN, Tianhong , FASOLI, Luca
发明人： YAN, Tianhong , FASOLI, Luca
IPC分类号： G11C8/12 , G11C13/00
CPC分类号： G11C8/12 , G11C13/0064 , G11C13/0069 , G11C2013/0066
摘要： A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry. To increase the performance of memory operations, the second selections circuits can change their selections independently of each other. For example, a memory operation is performed concurrently on a first non-volatile storage element of each group of a plurality of groups of non-volatile storage elements. Completion of the memory operation for the first non-volatile storage element of each group is independently detected. A memory operation on a second non-volatile storage element of each group is independently commenced for each group upon independently detecting completion of the memory operation for the first non-volatile storage element of the respective group.
摘要翻译：存储系统包括具有分组成块的多层非易失性存储元件的三维存储器阵列。每个块包括用于选择性地将第一类型的阵列线（例如位线）的子集耦合到相应的本地数据线的第一选择电路的子集。每个块包括用于选择性地将各个本地数据线的子集耦合到连接到控制电路的全局数据线的第二选择电路的子集。为了增加存储器操作的性能，第二选择电路可以彼此独立地改变它们的选择。例如，在多组非易失性存储元件的每组的第一非易失性存储元件上同时执行存储器操作。独立检测每组的第一非易失性存储元件的存储器操作的完成。在独立地检测对相应组的第一非易失性存储元件的存储器操作的完成时，对于每个组，在每个组的第二非易失性存储元件上的存储器操作被独立地开始。

7. 发明申请

WO2009158676A1 CAPACITIVE DISCHARGE METHOD FOR WRITING TO NON-VOLATILE MEMORY 审中-公开
标题翻译：用于写入非易失性存储器的电容式放电方法
公开(公告)号：WO2009158676A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/048955
申请日：2009-06-26
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E. , FASOLI, Luca, G. , YAN, Tianhong
发明人： SCHEUERLEIN, Roy, E. , FASOLI, Luca, G. , YAN, Tianhong
IPC分类号： G11C13/00 , G11C7/22
CPC分类号： G11C13/0007 , G11C7/12 , G11C7/22 , G11C13/0026 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2213/32 , G11C2213/34 , G11C2213/71
摘要： A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The circuits for limiting the SET current provide a charge on one or more bit lines that is not sufficient to SET the memory cells, and then discharge the bit lines through the memory cells in order to SET the memory cells.
摘要翻译：存储器系统包括衬底，衬底上的控制电路，包括具有可逆电阻切换元件的多个存储器单元的三维存储器阵列（衬底上方），以及用于限制用于可逆电阻切换的SET电流的电路元素。用于限制SET电流的电路在不足以设置存储器单元的一个或多个位线上提供电荷，然后通过存储器单元放电位线以设置存储器单元。

8. 发明申请

WO2009158670A1 REVERSE SET WITH CURRENT LIMIT FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：随着非易失性存储的电流限制反向设置
公开(公告)号：WO2009158670A1
公开(公告)日：2009-12-30
申请号：PCT/US2009/048945
申请日：2009-06-26
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E. , YAN, Tianhong
发明人： SCHEUERLEIN, Roy, E. , YAN, Tianhong
IPC分类号： G11C13/00
CPC分类号： G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C16/3481 , G11C2013/0078 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72
摘要： A storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The memory cell is SET in a reverse biased fashion.
摘要翻译：存储系统包括衬底，衬底上的控制电路，包括多个可逆电阻开关元件的三维存储器阵列（衬底上方），以及用于限制可逆电阻切换元件的SET电流的电路。以反向偏置的方式对存储器单元进行SET设置。

9. 发明申请

WO2012148852A1 NON-VOLATILE STORAGE SYSTEM WITH DUAL BLOCK PROGRAMMING 审中-公开
标题翻译：具有双块编程的非易失存储系统
公开(公告)号：WO2012148852A1
公开(公告)日：2012-11-01
申请号：PCT/US2012/034674
申请日：2012-04-23
申请人： SANDISK 3D LLC , YAN, Tianhong , LIU, Tz-yi , SCHEUERLEIN, Roy, E.
发明人： YAN, Tianhong , LIU, Tz-yi , SCHEUERLEIN, Roy, E.
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C5/02 , G11C13/0023 , G11C13/003 , G11C2213/71 , G11C2213/73 , G11C2213/77
摘要： A non-volatile storage system is disclosed that includes a plurality of blocks of non-volatile storage elements, a plurality of word lines connected to the blocks of non-volatile storage elements such that each word line is connected to adjacent blocks of non- volatile storage elements, a plurality of bit lines connected to the blocks of non-volatile storage elements, multiple sets of word lines drivers such that each set of word line drivers is positioned between two adjacent blocks for driving word lines connected to the two adjacent blocks, global data lines, local data lines in selective communication with the bit lines, one or more selection circuits that selectively connect the global data lines to selected local data lines and connect unselected local data lines to one or more unselected bit line signals and control circuitry in communication with the one or more selection circuits and the global data lines. The control circuitry concurrently programs non-volatile storage elements of two adjacent blocks by applying programming signals on word lines connected to the two adjacent blocks and applying programming signals on appropriate bit lines via the global data lines and the one or more selection circuits.
摘要翻译：公开了一种非易失性存储系统，其包括多个非易失性存储元件块，连接到非易失性存储元件的块的多个字线，使得每个字线连接到非易失性存储元件的相邻块存储元件，连接到非易失性存储元件块的多个位线，多组字线驱动器，使得每组字线驱动器位于两个相邻块之间，用于驱动连接到两个相邻块的字线，全局数据线，与位线选择性通信的本地数据线，一个或多个选择电路，其选择性地将全局数据线连接到选定的本地数据线，并将未选择的本地数据线连接到一个或多个未选位线信号和控制电路与一个或多个选择电路和全局数据线的通信。控制电路通过在连接到两个相邻块的字线上应用编程信号并经由全局数据线和一个或多个选择电路在适当的位线上施加编程信号来同时对两个相邻块的非易失性存储元件进行编程。

10. 发明申请

WO2012082654A2 ARCHITECTURE FOR THREE DIMESIONAL NON-VOLATILE STORAGE WITH VERTICAL BIT LINES 审中-公开
标题翻译：具有垂直位线的三维非易失性存储的架构
公开(公告)号：WO2012082654A2
公开(公告)日：2012-06-21
申请号：PCT/US2011/064493
申请日：2011-12-12
申请人： SANDISK 3D LLC , SCHEUERLEIN, Roy, E. , YAN, Tianhong , CERNEA, Raul-Adrian
发明人： SCHEUERLEIN, Roy, E. , YAN, Tianhong , CERNEA, Raul-Adrian
IPC分类号： G11C13/00 , H01L27/24
CPC分类号： G11C13/0033 , G11C5/025 , G11C8/08 , G11C13/0002 , G11C13/0026 , G11C13/0028 , G11C13/0069 , H01L27/0688 , H01L27/115 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/165 , H01L45/1683

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