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1. 发明申请

WO2012148852A1 NON-VOLATILE STORAGE SYSTEM WITH DUAL BLOCK PROGRAMMING 审中-公开
标题翻译：具有双块编程的非易失存储系统
公开(公告)号：WO2012148852A1
公开(公告)日：2012-11-01
申请号：PCT/US2012/034674
申请日：2012-04-23
申请人： SANDISK 3D LLC , YAN, Tianhong , LIU, Tz-yi , SCHEUERLEIN, Roy, E.
发明人： YAN, Tianhong , LIU, Tz-yi , SCHEUERLEIN, Roy, E.
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C5/02 , G11C13/0023 , G11C13/003 , G11C2213/71 , G11C2213/73 , G11C2213/77
摘要： A non-volatile storage system is disclosed that includes a plurality of blocks of non-volatile storage elements, a plurality of word lines connected to the blocks of non-volatile storage elements such that each word line is connected to adjacent blocks of non- volatile storage elements, a plurality of bit lines connected to the blocks of non-volatile storage elements, multiple sets of word lines drivers such that each set of word line drivers is positioned between two adjacent blocks for driving word lines connected to the two adjacent blocks, global data lines, local data lines in selective communication with the bit lines, one or more selection circuits that selectively connect the global data lines to selected local data lines and connect unselected local data lines to one or more unselected bit line signals and control circuitry in communication with the one or more selection circuits and the global data lines. The control circuitry concurrently programs non-volatile storage elements of two adjacent blocks by applying programming signals on word lines connected to the two adjacent blocks and applying programming signals on appropriate bit lines via the global data lines and the one or more selection circuits.
摘要翻译：公开了一种非易失性存储系统，其包括多个非易失性存储元件块，连接到非易失性存储元件的块的多个字线，使得每个字线连接到非易失性存储元件的相邻块存储元件，连接到非易失性存储元件块的多个位线，多组字线驱动器，使得每组字线驱动器位于两个相邻块之间，用于驱动连接到两个相邻块的字线，全局数据线，与位线选择性通信的本地数据线，一个或多个选择电路，其选择性地将全局数据线连接到选定的本地数据线，并将未选择的本地数据线连接到一个或多个未选位线信号和控制电路与一个或多个选择电路和全局数据线的通信。控制电路通过在连接到两个相邻块的字线上应用编程信号并经由全局数据线和一个或多个选择电路在适当的位线上施加编程信号来同时对两个相邻块的非易失性存储元件进行编程。

2. 发明申请

WO2012118618A1 THREE DIMENSIONAL MEMORY SYSTEM WITH COLUMN PIPELINE 审中-公开
标题翻译：具有柱管的三维存储系统
公开(公告)号：WO2012118618A1
公开(公告)日：2012-09-07
申请号：PCT/US2012/025171
申请日：2012-02-15
申请人： SANDISK 3D LLC , YAN, Tianhong , BALAKRISHNAN, Gopinath , LEE, Jeffrey, Koon Yee , LIU, Tz-yi
发明人： YAN, Tianhong , BALAKRISHNAN, Gopinath , LEE, Jeffrey, Koon Yee , LIU, Tz-yi
IPC分类号： G11C7/10 , G11C7/18 , G11C13/00 , G11C17/16
CPC分类号： G11C7/1006 , G11C7/1012 , G11C7/1039 , G11C7/18 , G11C8/08 , G11C8/18 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/0069 , G11C17/16
摘要： A monolithic three dimensional array of non-volatile storage elements is arranged in blocks. The non-volatile storage elements are connected to bit lines and word lines. The bit lines for each block are grouped into columns of bit lines. The columns of bit lines include top columns of bit lines that are connected to selection circuits on a top side of a respective block and bottom columns of bit lines that are connected to selection circuits on a bottom side of the respective block. Programming of data is pipelined between two or more columns of bit lines in order to increase programming speed. One embodiment of the programming process includes selectively connecting two columns of bit lines to a set of one or more selection circuits, using the one or more selection circuits to selectively connect one of the two columns of bit lines to one or more signal sources, programming non-volatile storage elements for the column of bit lines that is currently connected to the one or more signal sources, and changing one of the columns of bit lines connected to the set of one or more selection circuits while another column of bit lines is being programmed.
摘要翻译：非易失性存储元件的单片三维阵列以块状排列。非易失性存储元件连接到位线和字线。每个块的位线被分组成位线列。位线列包括连接到相应块的顶侧上的选择电路的顶列和位于相应块的底侧上的选择电路的位线的底列。数据的编程在两列或更多列的位线之间流水线化，以提高编程速度。编程过程的一个实施例包括使用一个或多个选择电路选择性地将两列位线连接到一组或多个选择电路，以选择性地将两列位线中的一列连接到一个或多个信号源，编程用于当前连接到一个或多个信号源的位线列的非易失性存储元件，以及改变连接到一组或多个选择电路的位线的列之一，而另一列位线正在被程序。

3. 发明申请

WO2012087518A3 CHARGE PUMP SYSTEM THAT DYNAMICALLY SELECTS NUMBER OF ACTIVE STAGES 审中-公开
公开(公告)号：WO2012087518A3
公开(公告)日：2012-06-28
申请号：PCT/US2011/062662
申请日：2011-11-30
申请人： SANDISK 3D LLC , CAZZANIGA, Marco , LIU, Tz-Yi
发明人： CAZZANIGA, Marco , LIU, Tz-Yi
IPC分类号： H02M3/07 , G11C5/14
摘要： A multi-stage charge pump selects the number of active stages dynamically. In the exemplary embodiment, this is done by having a multi-stage master charge pump section (703) in which the number of active stages is settable and a slave charge pump section (723) that is of the same design as the master section. The master section (703) is used drive the external load (Vout), while the slave section drives an adjustable internal load (733). The adjustable load is set by control logic (749) by comparing the operation of the two sections. The control logic then operates the slave sections with a different number of active stages than the master stage in order to determine whether the master stage is using the optimal number of active stages. The control logic (749) can then change the number of active stages accordingly.

4. 发明申请

WO2011075453A1 PROGRAM CYCLE SKIP 审中-公开
标题翻译：程序循环跳
公开(公告)号：WO2011075453A1
公开(公告)日：2011-06-23
申请号：PCT/US2010/060155
申请日：2010-12-13
申请人： SANDISK 3D LLC , BALAKRISHNAN, Gopinath , FASOLI, Luca , LIU, Tz-yi , ZHANG, Yuheng , LI, Yan
发明人： BALAKRISHNAN, Gopinath , FASOLI, Luca , LIU, Tz-yi , ZHANG, Yuheng , LI, Yan
IPC分类号： G11C16/10 , G11C16/32 , G11C13/00 , G11C5/02 , G11C17/16
CPC分类号： G11C13/0069 , G11C5/02 , G11C13/0007 , G11C13/0061 , G11C17/165 , G11C17/18 , G11C2013/0076 , G11C2013/0085 , G11C2213/71
摘要： A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non¬ volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.
摘要翻译：非易失性存储系统包括在编程页面（或其他单元）数据时跳过编程周期的技术。在对页面（或其他单元）数据的当前子集进行编程时，系统将评估页面（或其他单元）的下一个子集是否应编程为非易失性存储元素或跳过。不应该跳过的页面（或其他单元）的子集被编程到非易失性存储元件中。一些实施例包括将适当数据传送到临时锁存器/寄存器，以准备编程，同时评估是编程还是跳过编程。

5. 发明申请

WO2010002753A1 ADJUSTABLE READ LATENCY FOR MEMORY DEVICE PAGE-MODE ACCESS 审中-公开
标题翻译：用于存储器设备页面访问的可调整读取延迟
公开(公告)号：WO2010002753A1
公开(公告)日：2010-01-07
申请号：PCT/US2009/048991
申请日：2009-06-29
申请人： SANDISK 3D LLC , LIU, Tz-yi
发明人： LIU, Tz-yi
IPC分类号： G11C7/10
CPC分类号： G11C7/22 , G11C7/1012 , G11C7/1021 , G11C7/1039 , G11C7/1051 , G11C7/1063 , G11C2207/2272
摘要： A read process in a memory device is optimized. Sub-pages of a page of data are read from storage elements by an internal controller of the memory device at a read speed of the internal controller. At a specific time, the controller sets a READY signal to inform an external host to start reading out data from the buffer in a continuous burst, at the associated read speed of the host, which can differ from the controller's read speed, and asynchronous to the internal controller. The READY signal is set so that the host can complete its burst before the buffer runs out of data, while overall read time is minimized. The controller can also be configured for use with hosts having different read speeds. A host may communicate an identifier to the controller for use in determining an optimum time to set the READY signal.
摘要翻译：存储器件中的读取过程被优化。以内部控制器的读取速度由存储器件的内部控制器从存储元件读取数据页面的子页面。在特定时间，控制器设置READY信号以通知外部主机以连续脉冲串中的缓冲器读取数据，该数据以主机的相关读取速度与控制器的读取速度不同，并且异步到内部控制器。 READY信号被设置为使得主机可以在缓冲器用尽数据之前完成其突发，同时总体读取时间最小化。也可以将控制器配置为与具有不同读取速度的主机一起使用。主机可以向控制器通信标识符，以用于确定设置就绪信号的最佳时间。

6. 发明申请

WO2012129083A9 CONDITIONAL PROGRAMMING OF MULTIBIT MEMORY CELLS 审中-公开
标题翻译：多位记忆细胞的有条件编程
公开(公告)号：WO2012129083A9
公开(公告)日：2012-12-27
申请号：PCT/US2012029416
申请日：2012-03-16
申请人： SANDISK 3D LLC , COSTA XIYING , NIAN YIBO , SCHEUERLEIN ROY , LIU TZ-YI , GORLA CHANDRASEKHAR REDDY
发明人： COSTA XIYING , NIAN YIBO , SCHEUERLEIN ROY , LIU TZ-YI , GORLA CHANDRASEKHAR REDDY
IPC分类号： G11C11/56 , G11C13/00
CPC分类号： G11C13/0069 , G11C11/56 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0007 , G11C13/0064 , G11C2013/0071 , G11C2013/0073 , G11C2013/0076 , G11C2013/0092 , G11C2213/32
摘要： Improved methods for programming multi-level metal oxide memory cells balance applied voltage and current to provide improved performance. Set programming, which transitions the memory cell to a lower resistance state, is accomplished by determining an appropriate programming voltage and current limit for the objective resistance state to be achieved in the programming and then applying a pulse having the determined set electrical characteristics. Reset programming, which transitions the memory cell to a higher resistance state, is accomplished by determining an appropriate programming voltage and optionally current limit for the state to be achieved in the programming and then applying a pulse having the determined electrical characteristics. The algorithm used to determine the appropriate set or reset programming voltage and current values provides for effective programming without stressing the memory element. The electrical characteristics for programming pulses may be stored in a data table used in a table look up algorithm.
摘要翻译：用于编程多级金属氧化物存储器单元的改进方法平衡施加的电压和电流以提供改进的性能。通过确定在编程中要实现的客观电阻状态的合适的编程电压和电流限制，然后施加具有确定的设定电特性的脉冲，来完成将存储单元转换到较低电阻状态的设置编程。通过确定编程中要实现的状态的合适的编程电压和可选的电流限制，然后施加具有所确定的电特性的脉冲，来完成将存储单元转换到较高电阻状态的复位编程。用于确定适当的设置或重置编程电压和电流值的算法提供了有效的编程，而不会对存储元件造成压力。用于编程脉冲的电特性可以存储在查表算法中使用的数据表中。

7. 发明申请

WO2012129083A1 CONDITIONAL PROGRAMMING OF MULTIBIT MEMORY CELLS 审中-公开
标题翻译：多位记忆细胞的条件编程
公开(公告)号：WO2012129083A1
公开(公告)日：2012-09-27
申请号：PCT/US2012/029416
申请日：2012-03-16
申请人： SANDISK 3D LLC , COSTA, Xiying , NIAN, Yibo , SCHEUERLEIN, Roy , LIU, Tz-Yi , GORLA, Chandrasekhar, Reddy
发明人： COSTA, Xiying , NIAN, Yibo , SCHEUERLEIN, Roy , LIU, Tz-Yi , GORLA, Chandrasekhar, Reddy
IPC分类号： G11C11/56 , G11C13/00
CPC分类号： G11C13/0069 , G11C11/56 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0007 , G11C13/0064 , G11C2013/0071 , G11C2013/0073 , G11C2013/0076 , G11C2013/0092 , G11C2213/32
摘要： Improved methods for programming multi-level metal oxide memory cells balance applied voltage and current to provide improved performance. Set programming, which transitions the memory cell to a lower resistance state, is accomplished by determining an appropriate programming voltage and current limit for the objective resistance state to be achieved in the programming and then applying a pulse having the determined set electrical characteristics. Reset programming, which transitions the memory cell to a higher resistance state, is accomplished by determining an appropriate programming voltage and optionally current limit for the state to be achieved in the programming and then applying a pulse having the determined electrical characteristics. The algorithm used to determine the appropriate set or reset programming voltage and current values provides for effective programming without stressing the memory element. The electrical characteristics for programming pulses may be stored in a data table used in a table look up algorithm.
摘要翻译：改进的多级金属氧化物存储单元的编程方法平衡施加的电压和电流，以提供更好的性能。通过为编程中要实现的目标电阻状态确定适当的编程电压和电流限制，然后施加具有确定的设定电气特性的脉冲来实现将存储器单元转换到较低电阻状态的设置编程。将存储器单元转换到较高电阻状态的复位编程通过确定编程中要实现的状态的适当编程电压和可选的电流限制，然后施加具有确定的电特性的脉冲来实现。用于确定适当的设置或复位编程电压和电流值的算法提供有效的编程，而不会对存储元件造成影响。编程脉冲的电气特性可以存储在表查找算法中使用的数据表中。

8. 发明申请

WO2012087518A2 CHARGE PUMP SYSTEM THAT DYNAMICALLY SELECTS NUMBER OF ACTIVE STAGES 审中-公开
标题翻译：充电泵系统动态选择有效阶段数量
公开(公告)号：WO2012087518A2
公开(公告)日：2012-06-28
申请号：PCT/US2011062662
申请日：2011-11-30
申请人： SANDISK 3D LLC , CAZZANIGA MARCO , LIU TZ-YI
发明人： CAZZANIGA MARCO , LIU TZ-YI
IPC分类号： H02M3/07
CPC分类号： H02M3/073 , G11C5/145 , G11C29/021 , H02M2001/008 , H02M2003/077
摘要： A multi-stage charge pump selects the number of active stages dynamically. In the exemplary embodiment, this is done by having a multi-stage master charge pump section in which the number of active stages is settable and a slave charge pump section that is of the same design as the master section. The master section is used drive the external load, while the slave section drives an adjustable internal load. The adjustable load is set by control logic by comparing the operation of the two sections. The control logic then operates the slave sections with a different number of active stages than the master stage in order to determine whether the master stage is using the optimal number of active stages. The control logic can then change the number of active stages accordingly.
摘要翻译：多级电荷泵动态选择有效级数。在该示例性实施例中，这通过具有其中活动级数可设置的多级主电荷泵部分和与主部分具有相同设计的从电荷泵部分来完成。主部分用于驱动外部负载，而从部分驱动可调内部负载。可调负载由控制逻辑通过比较两部分的操作来设定。然后，控制逻辑以与主级不同数量的有效级操作从部件，以便确定主级是使用最佳数量的有效级。然后，控制逻辑可以相应地改变活动阶段的数量。

9. 发明申请

WO2011075452A1 3D MEMORY DEVICE WITH PAGE REGISTER NOT LIKE SENSE AMPLIFIER CIRCUITS AND SENSE AMPLIFIER INTERFACE UNDERNEATH MEMORY ARRAY 审中-公开
标题翻译：具有页面寄存器的3D存储器件不像感测放大器电路和感测放大器接口下的存储器阵列
公开(公告)号：WO2011075452A1
公开(公告)日：2011-06-23
申请号：PCT/US2010/060153
申请日：2010-12-13
申请人： SANDISK 3D LLC , BALAKRISHNAN, Gopinath , LEE, Jeffrey, Koon Yee , ZHANG, Yuheng , LIU, Tz-yi , FASOLI, Luca
发明人： BALAKRISHNAN, Gopinath , LEE, Jeffrey, Koon Yee , ZHANG, Yuheng , LIU, Tz-yi , FASOLI, Luca
IPC分类号： G11C5/02 , G11C17/16 , G11C13/02 , G11C13/00
CPC分类号： G11C5/025 , B82Y10/00 , G11C5/02 , G11C13/0002 , G11C13/0007 , G11C13/025 , G11C17/16 , G11C2213/19 , G11C2213/32 , G11C2213/33 , G11C2213/34 , G11C2213/71
摘要： A non-volatile storage device includes a substrate, a monolithic three- dimensional memory array of non-volatile storage elements arranged above a portion of the substrate, a plurality of sense amplifiers in communication with the non-volatile storage elements, a plurality of temporary storage devices in communication with the sense amplifiers, a page register in communication with the temporary storage devices, and one or more control circuits. The one or more control circuits are in communication with the page register, the temporary storage devices and the sense amplifiers. The sense amplifiers are arranged on the substrate underneath the monolithic three-dimensional memory array. The temporary storage devices are arranged on the substrate underneath the monolithic three-dimensional memory array. The page register is arranged on the substrate in an area that is not underneath the monolithic three- dimensional memory array. Data read from the non-volatile storage elements by the sense amplifiers is transferred to the temporary storage devices and then to the page register in response to the one or more control circuits. Data to be programmed into the non-volatile storage elements is transferred to the temporary storage devices from the page register in response to the one or more control circuits.
摘要翻译：非易失性存储装置包括衬底，布置在衬底的一部分上方的非易失性存储元件的单片三维存储器阵列，与非易失性存储元件通信的多个读出放大器，多个临时与读出放大器通信的存储装置，与临时存储装置通信的页寄存器，以及一个或多个控制电路。一个或多个控制电路与页寄存器，临时存储设备和读出放大器通信。读出放大器布置在单片三维存储器阵列下方的衬底上。临时存储装置布置在单片三维存储器阵列下面的衬底上。页面寄存器布置在基板上的不在单片三维存储器阵列下方的区域中。由感测放大器从非易失性存储元件读取的数据响应于一个或多个控制电路传送到临时存储设备，然后传送到页寄存器。要编程到非易失性存储元件中的数据响应于一个或多个控制电路从页寄存器传送到临时存储设备。

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