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81. 发明申请

WO2008059350A2 SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCTION THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2008059350A2
公开(公告)日：2008-05-22
申请号：PCT/IB2007/003477
申请日：2007-11-13
申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA , TANAKA, Hiroaki
发明人： TANAKA, Hiroaki
IPC分类号： H01L29/739 , H01L29/10 , H01L21/331
CPC分类号： H01L29/7397 , H01L29/1095 , H01L29/66348
摘要： A semiconductor device has a drift region (20) (third semiconductor region) of an n-type (first conductivity type); a body region (50) (second semiconductor region) of a p-type (second conductivity type) provided on the drift region (20); an emitter region (60) (first semiconductor region) of the n-type formed in the top surface of the body region (50) and separated from the drift region (20) by the body region (50); a trench (14) extending from the top surface of the emitter region (60) through the body region (50) into the drift region (20); a trench gate electrode (13) filled in the trench (14); and a semiconductor region (70) (fourth semiconductor region) of the p-type formed in contact with side faces of the trench protruding into the drift region (20). Therefore, the semiconductor device can suppress a surge voltage at turn-off, and can be produced easily.
摘要翻译：半导体器件具有n型（第一导电型）的漂移区域（20）（第三半导体区域）; 设置在漂移区域（20）上的p型（第二导电型）的体区（50）（第二半导体区域）; 所述n型的发射极区域（60）（第一半导体区域）形成在所述主体区域（50）的顶表面中并且通过所述主体区域（50）与所述漂移区域（20）分离。从所述发射极区域（60）的顶表面延伸通过所述体区（50）延伸到所述漂移区域（20）中的沟槽（14）。填充在沟槽（14）中的沟槽栅电极（13）; 以及形成为与突出到漂移区域（20）中的沟槽的侧面接触的p型半导体区域（第四半导体区域）（第四半导体区域）。因此，半导体装置能够抑制关断时的浪涌电压，能够容易地制造。

82. 发明申请

WO2003023863A2 TRENCH-GATE SEMICONDUCTOR DEVICES AND THEIR MANUFACTURE 审中-公开
标题翻译： TRENCH-GATE半导体器件及其制造
公开(公告)号：WO2003023863A2
公开(公告)日：2003-03-20
申请号：PCT/IB2002/003733
申请日：2002-09-11
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V.
发明人： PEAKE, Steven, T. , PETKOS, Georgios , RUTTER, Philip , GROVER, Raymond, J.
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/4232 , H01L29/42372 , H01L29/4238 , H01L29/66348 , H01L29/66734 , H01L29/7811 , H01L2924/13055 , H01L2924/13091 , H01L2924/30105
摘要： A device termination structure, and/or a gate bus-bar structure, and/or other end structure is provided for at least one group of cells in a cellular trench-gate semiconductor device, for example a power MOSFET. In this end structure, a conductive layer (11c), for example of polysilicon gate material, extends on an intermediate insulating layer (55) over a higher-doped (P+) end region (150) of the channel-accommodating region (15). This insulating layer (55) comprises an area (51e) of a trench-etch mask (51), preferably comprising silicon nitride, that is of greater thickness than the gate dielectric layer (17). A window (51a) extends through the trench-etch mask (51) ata location where an end trench (20e) extends into the P+ region (150). The end trench (20e) is an extension of the insulated gate trench (20) into the P+ region (150) and accommodates an extension (11e) of the trench-gate (11). The conductive layer (11c) is connected to the trench-gate extension (11e) via the window (51e). The lateral extent of the conductive layer (11c) terminates in an edge (11a,11b) that is defined on the trench-etch mask (51).
摘要翻译：为蜂窝状沟槽栅极半导体器件（例如功率MOSFET）中的至少一组电池提供器件端接结构和/或栅极汇流条结构和/或其它端部结构。在该端部结构中，例如多晶硅栅极材料的导电层（11c）在通道容纳区域（15）的较高掺杂（P +）端部区域（150）上的中间绝缘层（55）上延伸，。该绝缘层（55）包括沟槽蚀刻掩模（51）的优选地包括氮化硅的区域（51e），其厚度大于栅极电介质层（17）的厚度。窗口（51a）在端部沟槽（20e）延伸到P +区域（150）的位置处延伸穿过沟槽蚀刻掩模（51）。端部沟槽（20e）是绝缘栅极沟槽（20）延伸到P +区域（150）中并且容纳沟槽栅极（11）的延伸部分（11e）的延伸。导电层（11c）经由窗口（51e）连接到沟槽栅延伸部（11e）。导电层（11c）的横向延伸终止在限定在沟槽蚀刻掩模（51）上的边缘（11a，11b）中。

83. 发明申请

WO2003010812A1 MANUFACTURE OF SEMICONDUCTOR DEVICES WITH SCHOTTKY BARRIERS 审中-公开
标题翻译：半导体器件与肖特基屏障的制造
公开(公告)号：WO2003010812A1
公开(公告)日：2003-02-06
申请号：PCT/IB2002/002892
申请日：2002-07-24
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V.
发明人： GROVER, Raymond, J. , PEAKE, Steven, T.
IPC分类号： H01L21/329
CPC分类号： H01L29/7813 , H01L21/266 , H01L29/0619 , H01L29/0692 , H01L29/0696 , H01L29/407 , H01L29/66143 , H01L29/66348 , H01L29/7806 , H01L29/872 , H01L29/8725
摘要： In the manufacture of trench-gate power MOSFETs, trenched Schottky rectifiers and other devices including a Schottky barrier, a guard region (15s), trenched insulated electrode (11s) and the Schottky barrier (80) are self-aligned with respect to each other by providing spacers (52) to form a narrow window (52a) at a wider window (51a) in a mask pattern (51, 51s) that masks where the Schottky barrier (80) is to be formed. The trenched insulated electrode (11s) is formed by etching a trench (20) at the narrow window (52a) and by providing insulating material (17) and then electrode material (11s) in the trench. The guard region (15s) is provided by introducing dopant (61) via the wider window (51a). The mask pattern (51, 51s) masks the underlying body portion against this dopant introduction and is sufficiently wide (y8) to prevent the dopant (61) from extending laterally into the area where the Schottky barrier (80) is to be formed. Then at least the mask pattern (51, 51s) is removed before depositing a Schottky electrode (33).
摘要翻译：在沟槽栅功率MOSFET的制造中，沟槽肖特基整流器和其它器件包括肖特基势垒，保护区（15s），沟槽绝缘电极（11s）和肖特基势垒（80）彼此自对准通过在掩模图案（51,51s）中的宽窗口（51a）处形成窄窗口（52a）以形成肖特基势垒（80）的掩模（52,51）。沟槽绝缘电极（11s）通过在窄窗口（52a）处蚀刻沟槽（20）并且通过在沟槽中提供绝缘材料（17）和电极材料（11s）来形成。通过较宽窗口（51a）引入掺杂剂（61）来提供保护区域（15s）。掩模图案（51,51s）掩盖下面的主体部分抵抗该掺杂剂引入，并且足够宽（y8）以防止掺杂剂（61）横向延伸到要形成肖特基势垒（80）的区域中。然后在沉积肖特基电极（33）之前至少除去掩模图案（51,51s）。

84. 发明申请

WO0237569A9 MOS-GATED POWER DEVICE HAVING SEGMENTED TRENCH AND EXTENDED DOPING ZONE AND PROCESS FOR FORMING SAME 审中-公开
标题翻译：具有分段式铁路和扩展区域的MOS选通电力装置及其形成方法
公开(公告)号：WO0237569A9
公开(公告)日：2002-12-05
申请号：PCT/US0131840
申请日：2001-10-11
申请人： FAIRCHILD SEMICONDUCTOR
发明人： KOCON CHRISTOPHER B , GREBS THOMAS E , CUMBO JOSEPH L , RIDLEY RODNEY S
IPC分类号： H01L29/749 , H01L21/331 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/423 , H01L29/739 , H01L29/78 , H01L29/00
CPC分类号： H01L29/66348 , H01L29/0619 , H01L29/0634 , H01L29/0653 , H01L29/1095 , H01L29/42368 , H01L29/7397 , H01L29/749 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A trench MOS-gated device comprises a doped monocrystalline semiconductor substrate that includes an upper layer and is of a first conduction type. An extended trench in the substrate in the upper layer comprises two segments having differing widths relative to one another: a bottom segment of lesser width filled with a dielectric material, and an upper segment of greater width lined with a dielectric material and substantially filled with a conductive material, the filled upper segment of the trench forming a gate region. An extended doped zone of a second opposite conduction type extends from an upper surface into the upper layer of the substrate only on one side of the trench, and a doped well region of the second conduction type overlying a drain zone of the first conduction type is disposed in the upper layer on the opposite side of the trench. The drain zone is substantially insulated from the extended zone by the dielectric-filled bottom segment of the trench. A heavily doped source region of the first conduction type and a heavily doped body region of the second conduction type is disposed at the upper surface of the well region only on the side of said trench opposite doped extended zone. An interlevel dielectric layer is disposed on the upper surface overlying the gate and source regions, and a metal layer disposed on the upper surface of the upper layer and the interlevel dielectric layer is in electrical contact with the source and body regions and the extended zone. A process for constructing a trench MOS-gated device comprises: forming in a semiconductor substrate an extended trench that comprises an upper segment and a bottom segment, wherein the bottom segment has a lesser width relative to a greater width of the trench upper segment and extends to a depth corresponding to the total depth of the extended trench. The bottom segment of the trench is substantially filled with dielectric material. The trench upper segment has a floor and sidewalls comprising dielectric material and is substantially filled with a conductive material to form a gate region. A heavily doped source region of the first conduction type and a heavily doped body region of the second conduction type are formed in a surface well region on the side of the extended trench opposite an extended doped zone.
摘要翻译：沟槽MOS门控器件包括掺杂的单晶半导体衬底，其包括上层并且是第一导电类型。在上层中的衬底中的延伸沟槽包括相对于彼此具有不同宽度的两个区段：填充有介电材料的较小宽度的底部区段和宽度较大的上部区段，其内衬有电介质材料并基本上填充有导电材料，填充的沟槽的上部段形成栅极区域。第二相对导电类型的扩展掺杂区仅在沟槽的一侧从上表面延伸到衬底的上层，并且覆盖第一导电类型的漏极区的第二导电类型的掺杂阱区是设置在沟槽相对侧的上层中。漏极区域通过沟槽的电介质填充的底部区段与延伸区域基本绝缘。第一导电类型的重掺杂源极区域和第二导电类型的重掺杂体区域仅在阱区域相对的掺杂延伸区域的侧面上设置在阱区域的上表面。层叠电介质层设置在覆盖栅极和源极区域的上表面上，并且设置在上层的上表面上的金属层和层间电介质层与源区和主体区域以及延伸区域电接触。用于构造沟槽MOS门控器件的工艺包括：在半导体衬底中形成包括上部段和底部段的延伸沟槽，其中底部区段相对于沟槽上段的较大宽度具有较小的宽度，并且延伸达到对应于延伸沟槽的总深度的深度。沟槽的底部段基本上被介电材料填充。沟槽上段具有包括电介质材料的底板和侧壁，并且基本上填充有导电材料以形成栅极区域。第一导电类型的重掺杂源极区域和第二导电类型的重掺杂体区域形成在与延伸掺杂区域相对的延伸沟槽侧的表面阱区域中。

85. 发明申请

WO2002063695A1 絶縁ゲート型バイポーラトランジスタ、半導体装置、絶縁ゲート型バイポーラトランジスタの製造方法、および半導体装置の製造方法审中-公开
标题翻译：绝缘栅双极晶体管，半导体器件，制造绝缘栅双极晶体管的方法和制造半导体器件的方法
公开(公告)号：WO2002063695A1
公开(公告)日：2002-08-15
申请号：PCT/JP2001/000777
申请日：2001-02-02
申请人：三菱電機株式会社 , 高橋英樹 , 田畑光晴 , 友松佳史
发明人：高橋英樹 , 田畑光晴 , 友松佳史
IPC分类号： H01L29/78
CPC分类号： H01L29/66333 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/072 , H01L29/0834 , H01L29/66348 , H01L29/7395 , H01L29/7397 , H01L2224/45124 , H01L2224/48091 , H01L2224/48137 , H01L2224/48139 , H01L2224/48247 , H01L2224/49109 , H01L2224/49111 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01029 , H01L2924/01041 , H01L2924/01058 , H01L2924/01074 , H01L2924/12036 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19107 , H01L2924/3011 , H02M7/003 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： The invention relates to an insulated-gate bipolar transistor, a semiconductor device using it, and a method of manufacture thereof. It is an object of the invention to eliminate the need of connecting a freewheel diode for bypassing back current. The impurity concentration in an N buffer layer (12) cooperating with a P collector layer (11) to form a junction is increased to lower the avalanche breakdown voltage of a parasitic diode (D) formed of N-base layers (12, 13) and the P collector layer (11). This decreases the reverse breakdown voltage of an IGBT (101) below five times the saturation voltage (VCE(sat)) between collector and emitter.
摘要翻译：本发明涉及绝缘栅双极晶体管，使用它的半导体器件及其制造方法。本发明的目的是消除连接续流二极管以绕过回流电流的需要。增加与P +集电极层（11）配合以形成结的N +缓冲层（12）中的杂质浓度，以降低由N-碱形成的寄生二极管（D）的雪崩击穿电压层（12,13）和P +集电极层（11）。这降低了IGBT（101）的反向击穿电压低于集电极和发射极之间饱和电压（VCE（sat））的五倍。

86. 发明申请

WO0225700A3 SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件及形成半导体器件的方法
公开(公告)号：WO0225700A3
公开(公告)日：2002-06-06
申请号：PCT/GB0104211
申请日：2001-09-20
申请人： CAMBRIDGE SEMICONDUCTOR LTD
发明人： UDREA FLORIN , AMARATUNGA GEHAN ANIL JOSEPH
IPC分类号： H01L21/329 , H01L21/331 , H01L21/336 , H01L21/76 , H01L21/762 , H01L21/764 , H01L21/8234 , H01L27/08 , H01L27/088 , H01L29/06 , H01L29/08 , H01L29/12 , H01L29/20 , H01L29/24 , H01L29/32 , H01L29/423 , H01L29/739 , H01L29/78 , H01L29/786 , H01L29/861
CPC分类号： H01L29/7816 , H01L21/76289 , H01L21/764 , H01L29/0619 , H01L29/0634 , H01L29/0657 , H01L29/0661 , H01L29/0696 , H01L29/083 , H01L29/1608 , H01L29/2003 , H01L29/42368 , H01L29/66325 , H01L29/66333 , H01L29/66348 , H01L29/7393 , H01L29/7394 , H01L29/7395 , H01L29/7397 , H01L29/7801 , H01L29/7802 , H01L29/7812 , H01L29/7813 , H01L29/7824 , H01L29/7831 , H01L2924/0002 , H01L2924/00
摘要： A power semiconductor device (10) has an active region that includes a drift region (20). At least a portion of the drift region (20) is provided in a membrane )16) which has opposed top and bottom surfaces (15, 17). In one embodiment, the top surface (15) of the membrane (16) has electrical terminals connected directly or indirectly thereto to allow a voltage to be applied laterally across the drift region (20). In another embodiment, at least one electrical terminal is connected directly or indirectly to the top surface (15) and at least one electrical terminal is connected directly or indirectly to the bottom surface (17) to allow a voltage to be applied vertically across the drift region (20). In each of these embodiments, the bottom surface (17) of the membrane (16) does not have a semiconductor substrate positioned adjacent thereto.
摘要翻译：功率半导体器件（10）具有包括漂移区（20）的有源区。漂移区域（20）的至少一部分设置在具有相对的顶表面和底表面（15,17）的膜（16）中。在一个实施例中，膜（16）的顶表面（15）具有直接或间接连接到其上的电端子，以允许跨越漂移区域（20）横向施加电压。在另一个实施例中，至少一个电端子直接或间接地连接到顶表面（15），并且至少一个电端子直接或间接地连接到底表面（17），以允许垂直地施加电压跨越漂移区域（20）。在这些实施例的每一个中，膜（16）的底表面（17）不具有与其相邻定位的半导体衬底。

87. 发明申请

WO0141206A2 MANUFACTURE OF TRENCH-GATE SEMICONDUCTOR DEVICES 审中-公开
标题翻译： TRANCH-GATE半导体器件的制造
公开(公告)号：WO0141206A2
公开(公告)日：2001-06-07
申请号：PCT/EP0011290
申请日：2000-11-10
申请人： KONINKL PHILIPS ELECTRONICS NV
发明人： HIJZEN ERWIN A , TIMMERING CORNELIS E , CUTTER JOHN R
IPC分类号： H01L29/78 , H01L21/331 , H01L21/336 , H01L21/338
CPC分类号： H01L29/66848 , H01L29/66348 , H01L29/66666
摘要： In the manufacture of a trench-gate semiconductor device, for example a MOSFET or an IGBT, a starting semiconductor body (10) has two top layers (13, 15) provided for forming the source and body regions. Gate material (11') is provided in a trench (20) with a trench etchant mask (51, Figure 2) still present so that the gate material (11') forms a protruding step (30) from the adjacent surface (10a) of the semiconductor body, and a side wall spacer (32) is then formed in the step (30) to replace the mask (51). The source region (13) is formed self-aligned with the protruding trench-gate structure with a lateral extent determined by the spacer (32, Figure 5), and the gate (11) is then provided with an insulating overlayer (18, Figure 6). Forming the sidewall spacer (32) when the protruding trench-gate structure has a well-defined edge provided by the gate material (11') allows better definition of the source region (13) compared with a prior-art process in which the gate insulating overlayer is provided in the trench before causing the trench-gate structure to have the protruding step for the sidewall spacer.
摘要翻译：在制造沟槽栅极半导体器件例如MOSFET或IGBT时，起始半导体本体（10）具有两个用于形成源极和体区的顶层（13,15）。栅极材料（11'）设置在沟槽（20）中，其沟槽蚀刻剂掩模（图2）仍然存在，使得栅极材料（11'）从邻近的表面（10a）形成突出的台阶（30）并且在步骤（30）中形成侧壁间隔物（32）以更换掩模（51）。源极区域（13）形成为与突出的沟槽栅极结构自对准，具有由间隔物（32，图5）确定的横向范围，并且栅极（11）然后设置有绝缘覆盖层 6）。当突出的沟槽栅极结构具有由栅极材料（11'）提供的良好限定的边缘时，形成侧壁间隔物（32）允许源区域（13）的更好的定义与现有技术的工艺相比，其中栅极在使沟槽栅结构具有侧壁间隔物的突出步骤之前，在沟槽中设置绝缘覆层。

88. 发明申请

WO2017069873A1 VERTICAL POWER TRANSISTOR WITH THIN BOTTOM EMITTER LAYER AND DOPANTS IMPLANTED IN TRENCHES IN SHIELD AREA AND TERMINATION RINGS 审中-公开
标题翻译：垂直功率晶体管，带有底部发射极薄层和多种植入屏蔽区域和终端环中的沟槽
公开(公告)号：WO2017069873A1
公开(公告)日：2017-04-27
申请号：PCT/US2016/051679
申请日：2016-09-14
申请人： MAXPOWER SEMICONDUCTOR, INC.
发明人： YILMAZ, Hamza
IPC分类号： H01L29/732 , H01L21/04 , H01L21/08 , H01L21/22 , H01L21/324 , H01L29/66
CPC分类号： H01L29/0634 , H01L21/2253 , H01L21/26513 , H01L21/304 , H01L21/30604 , H01L21/324 , H01L29/0619 , H01L29/0623 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/66348 , H01L29/66734 , H01L29/7397 , H01L29/7811 , H01L29/7813
摘要： Various improvements in vertical transistors, such as IGBTs, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the top surface region of a growth substrate, followed by growing the various transistor layers, followed by grounding down the bottom surface of the substrate, followed by a wet etch of the bottom surface to expose the heavily doped p+ layer. A metal contact is then formed over the p+ layer. In another improvement, edge termination structures utilize p-dopants implanted in trenches to create deep p-regions for shaping the electric field, and shallow p-regions between the trenches for rapidly removing holes after turn-off. In another improvement, a dual buffer layer using an n-layer and distributed n+ regions improves breakdown voltage and saturation voltage. In another improvement, p-zones of different concentrations in a termination structure are formed by varying pitches of trenches. In another improvement, beveled saw streets increase breakdown voltage.
摘要翻译：公开了诸如IGBT的垂直晶体管的各种改进。这些改进包括在生长衬底的顶表面区域中形成周期性高掺杂p型发射极点，然后生长各种晶体管层，然后使衬底的底表面接地，然后湿法蚀刻底部表面以暴露重掺杂p +层。然后在p +层上形成金属接触。在另一改进中，边缘终端结构利用注入沟槽中的p型掺杂剂来形成用于成形电场的深p型区域和用于在关闭之后快速移除空穴的沟槽之间的浅p型区域。在另一个改进中，使用n层和分布n +区的双缓冲层提高了击穿电压和饱和电压。在另一改进中，通过改变沟槽的间距形成终端结构中不同浓度的p区。在另一个改进中，斜切的街道增加了击穿电压。

89. 发明申请

WO2016204126A1 半導体装置审中-公开
标题翻译：半导体器件
公开(公告)号：WO2016204126A1
公开(公告)日：2016-12-22
申请号：PCT/JP2016/067597
申请日：2016-06-13
申请人：富士電機株式会社
发明人：今川　鉄太郎
IPC分类号： H01L29/78 , H01L21/265 , H01L21/336 , H01L29/739
CPC分类号： H01L29/1095 , H01L21/265 , H01L29/32 , H01L29/66348 , H01L29/7397 , H01L29/78
摘要：スイッチング時の発振の抑制と、大電流短絡耐量の向上とを両立させることは難しい。第１の面と第１の面の反対側に位置する第２の面とを有する第１導電型の半導体層と、第１導電型の半導体層の第１の面に接して設けられた第２導電型の半導体層とを備え、第１導電型の半導体層は、第１の面から第２の面への第１方向の異なる位置において、複数の不純物濃度ピークを有し、第１方向における第１導電型の半導体層と第２導電型の半導体層との接合界面である第１の面から、複数の不純物濃度ピークのうち第１の面に１番目に近い第１番目の不純物濃度ピークと、第１の面に２番目に近い第２番目の不純物濃度ピークとの境界までにおける積分濃度が、臨界積分濃度以下である、半導体装置を提供する。
摘要翻译：实现对开关中的振荡的抑制和对大电流短路的耐受性的改善是困难的。提供一种半导体器件，包括：第一导电型半导体层，其具有位于与第一表面相对的第一表面和第二表面; 以及第二导电型半导体层，设置成与第一导电型半导体层的第一表面接触，其中第一导电类型半导体层在第一方向上的不同位置处具有多个杂质浓度峰值从第一表面到第二表面的第一表面，以及作为第一方向上的第一导电型半导体层和第二导电型半导体层之间的接合边界面的第一表面的积分浓度，第一杂质浓度峰值和第二杂质浓度峰值等于或小于临界积分浓度，其中第一杂质浓度峰值最接近第一表面，第二杂质浓度峰值是最接近第一表面的第二杂质浓度峰值，的多个杂质浓度峰。

90. 发明申请

WO2016199390A1 INSULATED GATE SWITCHING DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：绝缘闸门开关装置及其制造方法
公开(公告)号：WO2016199390A1
公开(公告)日：2016-12-15
申请号：PCT/JP2016/002704
申请日：2016-06-03
申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA , DENSO CORPORATION
发明人： TAKAYA, Hidefumi , MIZUNO, Shoji , WATANABE, Yukihiko , AOI, Sachiko
IPC分类号： H01L21/336 , H01L29/78 , H01L29/12 , H01L29/06 , H01L29/423
CPC分类号： H01L29/1608 , H01L21/02529 , H01L21/046 , H01L21/0475 , H01L21/049 , H01L29/0623 , H01L29/1095 , H01L29/36 , H01L29/4236 , H01L29/42368 , H01L29/66068 , H01L29/66348 , H01L29/66734 , H01L29/7397 , H01L29/7813
摘要： A method for manufacturing an insulated gate switching device is provided. The method includes: forming a first trench in a surface of a first SiC semiconductor layer; implanting p-type impurities into a bottom surface of the first trench; depositing a second SiC semiconductor layer on an inner surface of the first trench to form a second trench; and forming a gate insulating layer, a gate electrode, a first region and a body region so that the gate insulating layer covers an inner surface of the second trench, the gate electrode is located in the second trench, the first region is of n-type and in contact with the gate insulating layer, the body region is of p-type, separated from the implanted region, and in contact with the gate insulating layer under the first region.
摘要翻译：提供一种制造绝缘栅极开关装置的方法。该方法包括：在第一SiC半导体层的表面中形成第一沟槽; 将p型杂质注入第一沟槽的底表面; 在所述第一沟槽的内表面上沉积第二SiC半导体层以形成第二沟槽; 以及形成栅极绝缘层，栅电极，第一区域和主体区域，使得栅极绝缘层覆盖第二沟槽的内表面，栅电极位于第二沟槽中，第一区域为n- 类型并与栅极绝缘层接触，主体区域为p型，与注入区域分离，并且与第一区域下的栅极绝缘层接触。

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