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1. 发明申请

WO2005088695A1 TRENCH FIELD EFFECT TRANSISTOR AND METHOD OF MAKING IT 审中-公开
标题翻译： TRENCH场效应晶体管及其制作方法
公开(公告)号：WO2005088695A1
公开(公告)日：2005-09-22
申请号：PCT/IB2005/050653
申请日：2005-02-23
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PEAKE, Steven, T.
发明人： PEAKE, Steven, T.
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L29/0634
摘要： A method of manufacturing an insulated gate field effect transistor includes providing a substrate (2) having a low-doped region (4), forming insulated gate trenches (8) and implanting dopants of a first conductivity type at the base of the trenches (8). A body implant is implanted in the low-doped regions between the trenches; and diffused to form an insulated gate transistor structure in which the body implant diffuses to form a p-n junction between a body region (22) doped to have the second conductivity type above a drain region (20) doped to have the first conductivity type, the p-n junction being deeper below the first major surface between the trenches than at the trenches. The difference in doping concentration between the low-doped region (4) and the implanted region at the base of the trenches causes the difference in depth of the body-drain p-n junction formed in the diffusion step.
摘要翻译：制造绝缘栅场效应晶体管的方法包括提供具有低掺杂区域（4）的衬底（2），在沟槽（8）的底部形成绝缘栅极沟槽（8）和注入第一导电类型的掺杂剂）。体沟植入植入沟槽之间的低掺杂区域; 并且扩散以形成绝缘栅极晶体管结构，其中主体注入扩散以在被掺杂以具有第一导电类型的漏极区域（20）之上的掺杂具有第二导电类型的体区域（22）之间形成pn结， pn结在沟槽之间比在沟槽处比第一主表面更深。在低掺杂区域（4）和沟槽底部的注入区域之间的掺杂浓度的差异导致在扩散步骤中形成的体 - 漏p-n结的深度差。

2. 发明申请

WO2003034500A3 TRENCH-GATE SEMICONDUCTOR DEVICES AND THEIR MANUFACTURE 审中-公开
公开(公告)号：WO2003034500A3
公开(公告)日：2003-04-24
申请号：PCT/IB2002/004145
申请日：2002-10-09
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V.
发明人： CURRY, Steven, J. , PEAKE, Steven, T.
IPC分类号： H01L29/78
摘要： Trench-gate field-effect semiconductor devices, for example cellular power MOSFETs with compact geometries, comprise a semiconductor body (10) into which the trench-gate (11) extends from a surface-adjacent source region (13) through a channel-accommodating region (15) of opposite conductivity type (p) and into an underlying drain drift region (14). This invention provides the gate trench (20) with a width (w) that is smaller than its depth (d) and that tapers increasingly towards the bottom of the gate trench (20) to reduce the width (w) of the trench-gate (11) at a greater rate in the drain drift region (14) than in the channel-accommodating region (15).

3. 发明申请

WO2006027739A2 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：WO2006027739A2
公开(公告)日：2006-03-16
申请号：PCT/IB2005/052899
申请日：2005-09-06
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PEAKE, Steven, T.
发明人： PEAKE, Steven, T.
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/41741 , H01L29/66712 , H01L29/7813
摘要： A method of manufacturing a semiconductor device comprising source and drain regions (13, 14, 14a) of a first conductivity type, and a channelaccommodating region (15) of a second, opposite conductivity type which separates the source and drain regions. The device comprises a gate (11, 42) which extends adjacent to the channel-accommodating region. The method includes the steps of etching a trench (27) into the semiconductor body of the device at a location laterally spaced from that of the gate (11, 42); and implanting a second conductivity type dopant into the body through the bottom (27b) of the trench to form a second conductivity type localised region (37) in the drain region. The dimensions and doping level of the localised level of the localised region (37) in the finished device is such that the localised region and adjacent portions of the drain region provide a voltage-sustaining spacecharge zone when depleted. This serves to substantially improve the trade-off between on-resistance and breakdown voltage in the resulting device in a cost effective manner.
摘要翻译：一种制造半导体器件的方法，该半导体器件包括第一导电类型的源极和漏极区域（13,14,14a），以及分隔源极和漏极区域的第二相反导电类型的沟道容纳区域（15）。该装置包括邻近通道容纳区延伸的门（11,42）。该方法包括以下步骤：在与栅极（11,42）的横向间隔开的位置处将沟槽（27）蚀刻到器件的半导体本体中; 以及通过所述沟槽的底部（27b）将第二导电类型的掺杂剂注入到所述主体中，以在所述漏极区域中形成第二导电类型的定位区域（37）。成品装置中的局部区域（37）的局部化水平的尺寸和掺杂水平使得漏极区域的局部区域和相邻部分在耗尽时提供电压维持空间充电区。这用于以成本有效的方式大大改善所得器件中的导通电阻和击穿电压之间的折衷。

4. 发明申请

WO2006013540A2 MOSFET DEVICE AND RELATED METHOD OF OPERATION 审中-公开
标题翻译： MOSFET器件和相关的操作方法
公开(公告)号：WO2006013540A2
公开(公告)日：2006-02-09
申请号：PCT/IB2005/052538
申请日：2005-07-28
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , HEPPENSTALL, Keith , BROWN, Adam, R. , KENNEDY, Ian , KOH, Adrian, C., H. , PEAKE, Steven, T.
发明人： HEPPENSTALL, Keith , BROWN, Adam, R. , KENNEDY, Ian , KOH, Adrian, C., H. , PEAKE, Steven, T.
IPC分类号： H03K17/00
CPC分类号： H03K17/161 , H03K17/08122
摘要： The present invention provides for a MOSFET device (10) having a body diode structure (22) and provided with biasing means arranged to provide a bias voltage selectively applied to the gate of the MOSFET (12) during reverse recovery of the body diode structure (22) so as to reduce reverse recovery transient signals associated with the body diode structure (22), the biasing means comprising a diode device (16) located in the gate path of the device (10).
摘要翻译：本发明提供了一种具有体二极管结构（22）并且设置有偏置装置的MOSFET器件（10），该偏置装置被布置为在期间提供选择性地施加到MOSFET（12）的栅极的偏置电压反向恢复体二极管结构（22）以便减少与体二极管结构（22）相关的反向恢复瞬态信号，所述偏置装置包括位于器件（10）的栅极路径中的二极管器件（16）。

5. 发明申请

WO2005038927A1 TRENCH INSULATED GATE FIELD EFFECT TRANSISTOR 审中-公开
标题翻译： TRENCH绝缘栅场效应晶体管
公开(公告)号：WO2005038927A1
公开(公告)日：2005-04-28
申请号：PCT/IB2004/052061
申请日：2004-10-12
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , GROVER, Raymond, J. , PEAKE, Steven, T.
发明人： GROVER, Raymond, J. , PEAKE, Steven, T.
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/1095
摘要： A trench insulated gate field effect transistor having a reduced mesa width between adjacent trenches to obtain desirable performance characteristics, in particular low Rds(on), with a suitable channel length and/or gate trench depth. The transistor has a nominal one-dimensional maximum lateral depletion width w 9 at the gate-body region interface at the threshold voltage, a nominal vertical depletion length w a in the body region (4) adjacent to the drain region (2) when the design breakdown voltage Vbdss is applied between source and drain, and a nominal vertical depletion length w as in the body region (4) adjacent to the source region (14), wherein the channel length I is given by I a + w as ) and the mesa width w is given by w 9 ).
摘要翻译：具有相邻沟槽之间的台面宽度减小的沟槽绝缘栅场效应晶体管，以获得期望的性能特性，特别是具有合适沟道长度和/或栅极沟槽深度的低Rds（on）。晶体管在阈值电压下的栅极 - 体区界面处具有标称的一维最大横向耗尽宽度w9，当设计击穿时在与漏极区域（2）相邻的体区（4）中的标称垂直耗尽长度wa 电压Vbdss被施加在源极和漏极之间，并且标称垂直耗尽长度在与源极区域（14）相邻的体区（4）中，其中沟道长度I由I <2（Wa +为）和台面宽度w由w <1（W9）给出。

6. 发明申请

WO2003023863A3 TRENCH-GATE SEMICONDUCTOR DEVICES AND THEIR MANUFACTURE 审中-公开
公开(公告)号：WO2003023863A3
公开(公告)日：2003-03-20
申请号：PCT/IB2002/003733
申请日：2002-09-11
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V.
发明人： PEAKE, Steven, T. , PETKOS, Georgios , RUTTER, Philip , GROVER, Raymond, J.
IPC分类号： H01L29/78
摘要： A device termination structure, and/or a gate bus-bar structure, and/or other end structure is provided for at least one group of cells in a cellular trench-gate semiconductor device, for example a power MOSFET. In this end structure, a conductive layer (11c), for example of polysilicon gate material, extends on an intermediate insulating layer (55) over a higher-doped (P+) end region (150) of the channel-accommodating region (15). This insulating layer (55) comprises an area (51e) of a trench-etch mask (51), preferably comprising silicon nitride, that is of greater thickness than the gate dielectric layer (17). A window (51a) extends through the trench-etch mask (51) ata location where an end trench (20e) extends into the P+ region (150). The end trench (20e) is an extension of the insulated gate trench (20) into the P+ region (150) and accommodates an extension (11e) of the trench-gate (11). The conductive layer (11c) is connected to the trench-gate extension (11e) via the window (51e). The lateral extent of the conductive layer (11c) terminates in an edge (11a,11b) that is defined on the trench-etch mask (51).

7. 发明申请

WO2003019673A1 A SEMICONDUCTOR RECTIFIER 审中-公开
标题翻译：半导体整流器
公开(公告)号：WO2003019673A1
公开(公告)日：2003-03-06
申请号：PCT/IB2002/003153
申请日：2002-07-29
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V.
发明人： HUANG, Eddie , PEAKE, Steven, T.
IPC分类号： H01L29/872
CPC分类号： H01L29/872
摘要： A semiconductor rectifier includes an intermediate semiconductor region (29) extending between anode (9) and cathode (7) contacts. A trenched gate (19) with insulated sidewalls (15) and base (17) can deplete the intermediate region. However, a shield region (23) acts to shield the intermediate region (29) from the gate (19) to allow current to flow in dependence on the polarity of the voltage applied between anode and cathode contacts (9, 7).
摘要翻译：半导体整流器包括在阳极（9）和阴极（7）之间延伸的中间半导体区域（29）。具有绝缘侧壁（15）和基座（17）的沟槽浇口（19）可以消耗中间区域。然而，屏蔽区域（23）用于屏蔽来自栅极（19）的中间区域（29），以允许电流根据施加在阳极和阴极触点（9,7）之间的电压的极性而流动。

8. 发明申请

WO2007129261A3 TRENCH FIELD EFFECT TRANSISTORS 审中-公开
公开(公告)号：WO2007129261A3
公开(公告)日：2007-11-15
申请号：PCT/IB2007/051636
申请日：2007-05-02
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PEAKE, Steven, T.
发明人： PEAKE, Steven, T.
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06 , H01L29/40 , H01L29/423 , H01L29/417
摘要： Trench field effect transistors (trench FETs) include alternating gate trenches (20) and source trenches (22). The gate trenches (20) include insulated gates (16). The source trenches (22) include a source connected conductive layer (30) and insulated sidewalls (32). A source electrode (36) extends into the top of the source trenches (22) to contact the source connected conductive layer (30) as well as the source electrode (8) and body (6), the latter being contacted at the side of the source trenches (22). The field effect transistors can deliver a useful combination of switching speed, specific on-resistance and breakdown voltage.

9. 发明申请

WO2006038201A2 POWER SEMICONDUCTOR DEVICES 审中-公开
标题翻译：功率半导体器件
公开(公告)号：WO2006038201A2
公开(公告)日：2006-04-13
申请号：PCT/IB2005/053289
申请日：2005-10-06
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PEAKE, Steven, T.
发明人： PEAKE, Steven, T.
IPC分类号： H01L29/78 , H02M3/335
CPC分类号： H01L29/7802 , H01L29/402 , H01L29/7396 , H01L29/7831
摘要： A semiconductor device includes a channel-accommodating region (15) extending from a first major surface (10a) of its semiconductor body and separating source and drain regions. The channel-accommodating region defines junctions (15a, 15b) with the source and drain drift regions at the first major surface. First and second gates (33, 35) extend laterally over the first major surface (10a) which are isolated from each other so as to be independently operable. The first gate (33) extends part way across the channel-accommodating region (15) from over said source region junction (15a) towards said drain drift region junction (15b), and the second gate (35) extends over the channel-accommodating region (15) from adjacent to the first gate (33) to over said drain drift region junction (15b) such that the first and second gates are operable to form a conduction channel in the channelaccommodating region between the source and drain regions. In use of the device, a modulating potential is applied to the first gate (33), and a fixed potential is applied to the second gate (35). The device is therefore turned on by application of a sufficient bias potential to the first gate, in combination with a sufficient fixed potential at the second gate. The controlling first gate is spaced from the drain drift region (14) by the associated insulating layer and also a portion of the channelaccommodating region (15). The gate-drain capacitance of the device is therefore negligible, providing a substantial reduction in switching losses.
摘要翻译：半导体器件包括从其半导体主体的第一主表面（10a）延伸并分离源极和漏极区域的沟道容纳区域（15）。通道容纳区限定了在第一主表面处具有源极和漏极漂移区的结（15a，15b）。第一和第二门（33,35）横向延伸穿过第一主表面（10a），彼此隔离以便可独立操作。第一栅极（33）从所述源极区域结（15a）上方朝向所述漏极漂移区结（15b）部分地延伸穿过所述沟道容纳区（15），并且所述第二栅极（35）在所述沟道容纳区区域（15）从所述第一栅极（33）相邻到所述漏极漂移区结（15b），使得所述第一和第二栅极可操作以在所述源极和漏极区域之间的所述沟道容纳区域中形成导电沟道。在使用该器件时，将调制电位施加到第一栅极（33），并且固定电位施加到第二栅极（35）。因此，该器件通过向第一栅极施加足够的偏置电位而与第二栅极处的足够的固定电位相结合地被接通。控制的第一栅极与漏极漂移区域（14）间隔相关联的绝缘层以及通道容纳区域（15）的一部分。因此，器件的栅极 - 漏极电容可以忽略不计，从而大大降低了开关损耗。

10. 发明申请

WO2005088722A2 TRENCH FIELD EFFECT TRANSISTOR AND METHOD OF MAKING IT 审中-公开
标题翻译： TRENCH场效应晶体管及其制作方法
公开(公告)号：WO2005088722A2
公开(公告)日：2005-09-22
申请号：PCT/IB2005/050651
申请日：2005-02-23
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , RUTTER, Philip , PEAKE, Steven, T.
发明人： RUTTER, Philip , PEAKE, Steven, T.
IPC分类号： H01L29/78
CPC分类号： H01L29/0878 , H01L29/0847 , H01L29/1095 , H01L29/41766 , H01L29/42368 , H01L29/7802 , H01L29/7813
摘要： A trench FET includes drain region (20), source region (18) and body region (22) extending between the source region (18) and the drain region (20). Insulated gate trenches (10) control conduction. Deep pillars (32) of opposite conductivity type to the drain face one another below the bottom of the trench. The pillars (32) extend in the example about 0.6 micron below the bottom of the trench into the drain region (20). The pillars are provided to create depletion regions at the p-n junction between the pillars (32) and drain (20). When a source-drain voltage is applied the depletion regions from the pillars (32) on either side of the trench extend towards one another to shield the trench region from the drain (20).
摘要翻译：沟槽FET包括在源极区域（18）和漏极区域（20）之间延伸的漏极区域（20），源极区域（18）和主体区域（22）。绝缘栅沟（10）控制导通。在沟槽底部下方的排水面相反导电类型的深柱（32）。支柱（32）在该示例中在沟槽底部下方延伸0.6μm至漏极区域（20）。提供柱以在柱（32）和排水（20）之间的p-n结处形成耗尽区。当施加源极 - 漏极电压时，来自沟槽两侧的柱（32）的耗尽区域朝向彼此延伸以屏蔽沟槽区域与漏极（20）。

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