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1. 发明申请

WO2010096261A3 STRUCTURES AND METHODS FOR IMPROVING TRENCH-SHIELDED SEMICONDUCTOR DEVICES AND SCHOTTKY BARRIER RECTIFIER DEVICES 审中-公开
标题翻译：用于改进TRENCH-SFETED半导体器件和肖特基栅栏整流器器件的结构和方法
公开(公告)号：WO2010096261A3
公开(公告)日：2010-11-18
申请号：PCT/US2010022830
申请日：2010-02-02
申请人： FAIRCHILD SEMICONDUCTOR , GREBS THOMAS E , RINEHIMER MARK , YEDINAK JOSEPH , PROBST DEAN E , DOLNY GARY , BENJAMIN JOHN
发明人： GREBS THOMAS E , RINEHIMER MARK , YEDINAK JOSEPH , PROBST DEAN E , DOLNY GARY , BENJAMIN JOHN
IPC分类号： H01L29/872 , H01L21/027 , H01L29/78
CPC分类号： H01L29/872 , H01L23/544 , H01L29/0657 , H01L29/66143 , H01L29/7811 , H01L29/8725 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Various structures and methods for improving the performance of trench-shielded power semiconductor devices and the like are described.
摘要翻译：描述了用于改善沟槽屏蔽功率半导体器件等的性能的各种结构和方法。

2. 发明申请

WO0237569A9 MOS-GATED POWER DEVICE HAVING SEGMENTED TRENCH AND EXTENDED DOPING ZONE AND PROCESS FOR FORMING SAME 审中-公开
标题翻译：具有分段式铁路和扩展区域的MOS选通电力装置及其形成方法
公开(公告)号：WO0237569A9
公开(公告)日：2002-12-05
申请号：PCT/US0131840
申请日：2001-10-11
申请人： FAIRCHILD SEMICONDUCTOR
发明人： KOCON CHRISTOPHER B , GREBS THOMAS E , CUMBO JOSEPH L , RIDLEY RODNEY S
IPC分类号： H01L29/749 , H01L21/331 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/423 , H01L29/739 , H01L29/78 , H01L29/00
CPC分类号： H01L29/66348 , H01L29/0619 , H01L29/0634 , H01L29/0653 , H01L29/1095 , H01L29/42368 , H01L29/7397 , H01L29/749 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A trench MOS-gated device comprises a doped monocrystalline semiconductor substrate that includes an upper layer and is of a first conduction type. An extended trench in the substrate in the upper layer comprises two segments having differing widths relative to one another: a bottom segment of lesser width filled with a dielectric material, and an upper segment of greater width lined with a dielectric material and substantially filled with a conductive material, the filled upper segment of the trench forming a gate region. An extended doped zone of a second opposite conduction type extends from an upper surface into the upper layer of the substrate only on one side of the trench, and a doped well region of the second conduction type overlying a drain zone of the first conduction type is disposed in the upper layer on the opposite side of the trench. The drain zone is substantially insulated from the extended zone by the dielectric-filled bottom segment of the trench. A heavily doped source region of the first conduction type and a heavily doped body region of the second conduction type is disposed at the upper surface of the well region only on the side of said trench opposite doped extended zone. An interlevel dielectric layer is disposed on the upper surface overlying the gate and source regions, and a metal layer disposed on the upper surface of the upper layer and the interlevel dielectric layer is in electrical contact with the source and body regions and the extended zone. A process for constructing a trench MOS-gated device comprises: forming in a semiconductor substrate an extended trench that comprises an upper segment and a bottom segment, wherein the bottom segment has a lesser width relative to a greater width of the trench upper segment and extends to a depth corresponding to the total depth of the extended trench. The bottom segment of the trench is substantially filled with dielectric material. The trench upper segment has a floor and sidewalls comprising dielectric material and is substantially filled with a conductive material to form a gate region. A heavily doped source region of the first conduction type and a heavily doped body region of the second conduction type are formed in a surface well region on the side of the extended trench opposite an extended doped zone.
摘要翻译：沟槽MOS门控器件包括掺杂的单晶半导体衬底，其包括上层并且是第一导电类型。在上层中的衬底中的延伸沟槽包括相对于彼此具有不同宽度的两个区段：填充有介电材料的较小宽度的底部区段和宽度较大的上部区段，其内衬有电介质材料并基本上填充有导电材料，填充的沟槽的上部段形成栅极区域。第二相对导电类型的扩展掺杂区仅在沟槽的一侧从上表面延伸到衬底的上层，并且覆盖第一导电类型的漏极区的第二导电类型的掺杂阱区是设置在沟槽相对侧的上层中。漏极区域通过沟槽的电介质填充的底部区段与延伸区域基本绝缘。第一导电类型的重掺杂源极区域和第二导电类型的重掺杂体区域仅在阱区域相对的掺杂延伸区域的侧面上设置在阱区域的上表面。层叠电介质层设置在覆盖栅极和源极区域的上表面上，并且设置在上层的上表面上的金属层和层间电介质层与源区和主体区域以及延伸区域电接触。用于构造沟槽MOS门控器件的工艺包括：在半导体衬底中形成包括上部段和底部段的延伸沟槽，其中底部区段相对于沟槽上段的较大宽度具有较小的宽度，并且延伸达到对应于延伸沟槽的总深度的深度。沟槽的底部段基本上被介电材料填充。沟槽上段具有包括电介质材料的底板和侧壁，并且基本上填充有导电材料以形成栅极区域。第一导电类型的重掺杂源极区域和第二导电类型的重掺杂体区域形成在与延伸掺杂区域相对的延伸沟槽侧的表面阱区域中。

3. 发明申请

WO2006017376A3 SEMICONDUCTOR POWER DEVICE HAVING A TOP-SIDE DRAIN USING A SINKER TRENCH 审中-公开
标题翻译：具有SINKER TRENCH的顶端排水的半导体功率器件
公开(公告)号：WO2006017376A3
公开(公告)日：2007-08-09
申请号：PCT/US2005026928
申请日：2005-07-29
申请人： FAIRCHILD SEMICONDUCTOR , GREBS THOMAS E , DOLNY GARY M
发明人： GREBS THOMAS E , DOLNY GARY M
IPC分类号： H01L21/332 , H01L21/338
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/0696 , H01L29/41741 , H01L29/41766 , H01L29/42368 , H01L29/7809 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device includes a substrate of a first conductivity type and an epitaxial layer of the first conductivity type over and in contact with the substrate. A first trench extends into and terminates within the epitaxial layer. A sinker trench extends from the top surface of the epitaxial layer through the epitaxial layer and terminates within the substrate. The sinker trench is laterally spaced from the first trench, and is wider and extends deeper than the first trench. The sinker trench is lined with an insulator only along the sinker trench sidewalls so that a conductive material filling the sinker trench makes electrical contact with the substrate along the bottom of the trench and makes electrical contact with an interconnect layer along the top of the trench.
摘要翻译：半导体功率器件包括第一导电类型的衬底和与衬底接触的第一导电类型的外延层。第一沟槽延伸到外延层中并终止于外延层内。沉降沟从外延层的顶表面延伸穿过外延层并终止于衬底内。沉降沟与第一沟槽横向间隔开，并且比第一沟槽更宽并且延伸得更深。沉陷沟槽沿着沉降片沟槽侧壁排列有绝缘体，使得填充沉陷沟槽的导电材料沿着沟槽的底部与衬底电接触，并且沿着沟槽的顶部与互连层电接触。

4. 发明申请

WO02058159A3 MOS-GATED POWER DEVICE WITH DOPED POLYSILICON BODY AND PROCESS FOR FORMING SAME 审中-公开
标题翻译：具有掺杂多晶硅体的MOS栅极电源装置及其形成方法
公开(公告)号：WO02058159A3
公开(公告)日：2003-08-28
申请号：PCT/US0144374
申请日：2001-11-28
申请人： FAIRCHILD SEMICONDUCTOR
发明人： KOCON CHRISTOPHER B , RIDLEY RODNEY S , GREBS THOMAS E
IPC分类号： H01L21/336 , H01L29/04 , H01L29/10 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7816 , H01L29/04 , H01L29/1095 , H01L29/7395 , H01L29/7801 , H01L29/7813 , Y10S438/914
摘要： An improved MOS-gated power device on a substrate having an upper layer, said substrate comprising in said upper layer doped monocrystalline silicon of a first conduction type and including a doped well region of a second conduction type, said substrate further comprising at least one heavily doped source region of said first conduction type disposed in said well region at an upper surface of said upper layer, a gate region comprising a conductive material electrically insulated from said source region by a dielectric material, a patterned interlevel dielectric layer on said upper surface overlying said gate amd source regions, and a heavily doped drain region of sqaid first conduction type; wherein the improvement comprises: At least one body region of said second conduction type disposed in said well region at said upper surface of said substrate, said body region comprising heavily doped polysilicon.
摘要翻译：一种在具有上层的衬底上的改进的MOS门控功率器件，所述衬底包括在第一导电类型的所述上层掺杂单晶硅中，并且包括第二导电类型的掺杂阱区，所述衬底还包括至少一个大的在所述上层的上表面处设置在所述阱区中的所述第一导电类型的掺杂源极区，包括通过电介质材料与所述源极区域电绝缘的导电材料的栅极区域，所述上表面上的图案化层间电介质层所述栅极源极区和均匀第一导电类型的重掺杂漏极区; 其中所述改进包括：所述第二导电类型的至少一个体区设置在所述衬底的所述上表面处的所述阱区中，所述体区包括重掺杂多晶硅。

5. 发明申请

WO2010080296A2 LATERAL MOSFET WITH SUBSTRATE DRAIN CONNECTION 审中-公开
标题翻译：横向MOSFET与衬底漏极连接
公开(公告)号：WO2010080296A2
公开(公告)日：2010-07-15
申请号：PCT/US2009067151
申请日：2009-12-08
申请人： FAIRCHILD SEMICONDUCTOR , GREBS THOMAS E , DOLNY GARY M , KINZER DANIEL M
发明人： GREBS THOMAS E , DOLNY GARY M , KINZER DANIEL M
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L21/26506 , H01L29/0696 , H01L29/0878 , H01L29/1054 , H01L29/1095 , H01L29/402 , H01L29/4175 , H01L29/41766 , H01L29/456 , H01L29/4933 , H01L29/513 , H01L29/66696 , H01L29/7816
摘要： In one form a lateral MOSFET includes an active gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, and a non-active gate positioned above the drain region. In another form the lateral MOSFET includes a gate positioned laterally between a source region and a drain region, the drain region extending from an upper surface of a monocrystalline semiconductor body to a bottom surface of the monocrystalline semiconductor body, the source region and the drain region being of a first conductivity type, a heavy body region of a second conductivity type in contact with and below the source region, and the drain region comprising a lightly doped drain (LDD) region proximate an edge of the gate and a sinker extending from the upper surface of the monocrystalline body to the bottom surface of the monocrystalline semiconductor body.
摘要翻译：在一种形式中，横向MOSFET包括横向位于源极区和漏极区之间的有源栅极，漏极区从单晶半导体主体的上表面延伸到单晶半导体主体的底表面，以及非有源栅极位于漏极区域上方。在另一种形式中，横向MOSFET包括横向位于源极区域和漏极区域之间的栅极，漏极区域从单晶半导体主体的上表面延伸到单晶半导体主体的底表面，源极区域和漏极区域具有第一导电类型，与所述源极区域接触并位于所述源极区域下方的第二导电类型的重体区域，并且所述漏极区域包括接近所述栅极的边缘的轻掺杂漏极（LDD）区域和从所述单晶体的上表面到单晶半导体主体的底表面。

6. 发明申请

WO2007002857A9 STRUCTURES AND METHODS FOR FORMING SHIELDED GATE FIELD EFFECT TRANSISTORS 审中-公开
标题翻译：用于形成屏蔽栅场效应晶体管的结构和方法
公开(公告)号：WO2007002857A9
公开(公告)日：2009-07-23
申请号：PCT/US2006025432
申请日：2006-06-29
申请人： FAIRCHILD SEMICONDUCTOR , GREBS THOMAS E , RIDLEY RODNEY S , KRAFT NATHAN LAWRENCE , DOLNY GARY M , YEDINAK JOSEPH A , KOCON CHRISTOPHER BOGUSLAW , CHALLA ASHOK B
发明人： GREBS THOMAS E , RIDLEY RODNEY S , KRAFT NATHAN LAWRENCE , DOLNY GARY M , YEDINAK JOSEPH A , KOCON CHRISTOPHER BOGUSLAW , CHALLA ASHOK B
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/338 , H01L21/8242 , H01L29/76
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0865 , H01L29/0869 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A field effect transistor is formed as follows. A trench is formed in a semiconductor region. A dielectric layer lining the trench sidewalls and bottom is formed. The trench is filled with a conductive material. The conductive material is recessed into the trench to thereby form a shield electrode in a bottom portion of the trench. The recessing of the conductive material includes isotropic etching of the conductive material. An inter-electrode dielectric (IED) is formed over the recessed shield electrode.
摘要翻译：场效应晶体管如下形成。在半导体区域中形成沟槽。形成衬在沟槽侧壁和底部的电介质层。沟槽填充有导电材料。导电材料凹陷到沟槽中，从而在沟槽的底部形成屏蔽电极。导电材料的凹陷包括导电材料的各向同性蚀刻。在凹形屏蔽电极上形成电极间电介质（IED）。

7. 发明申请

WO2006127914A3 TRENCH-GATE FIELD EFFECT TRANSISTORS AND METHODS OF FORMING THE SAME 审中-公开
标题翻译： TRENCH-GATE场效应晶体管及其形成方法
公开(公告)号：WO2006127914A3
公开(公告)日：2009-05-22
申请号：PCT/US2006020274
申请日：2006-05-24
申请人： FAIRCHILD SEMICONDUCTOR , YILMAZ HAMZA , CALAFUT DANIEL , KOCON CHRISTOPHER BOGUSLAW , SAPP STEVEN P , PROBST DEAN E , KRAFT NATHAN L , GREBS THOMAS E , RIDLEY RODNEY S , DOLNY GARY M , MARCHANT BRUCE D , YEDINAK JOSEPH A
发明人： YILMAZ HAMZA , CALAFUT DANIEL , KOCON CHRISTOPHER BOGUSLAW , SAPP STEVEN P , PROBST DEAN E , KRAFT NATHAN L , GREBS THOMAS E , RIDLEY RODNEY S , DOLNY GARY M , MARCHANT BRUCE D , YEDINAK JOSEPH A
IPC分类号： H01L27/102 , H01L21/322 , H01L21/336 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/7827 , H01L21/26586 , H01L29/0878 , H01L29/402 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/7813 , H01L29/872
摘要： A field effect transistor includes a body region of a first conductivity type over a semiconductor region of a second conductivity type. A gate trench extends through the body region and terminates within the semiconductor region. At least one conductive shield electrode is disposed in the gate trench. A gate electrode is disposed in the gate trench over but insulated from the at least one conductive shield electrode. A shield dielectric layer insulates the at lease one conductive shield electrode from the semiconductor region. A gate dielectric layer insulates the gate electrode from the body region. The shield dielectric layer is formed such that it flares out and extends directly under the body region.
摘要翻译：场效应晶体管包括在第二导电类型的半导体区域上的第一导电类型的体区。栅极沟槽延伸穿过身体区域并终止在半导体区域内。至少一个导电屏蔽电极设置在栅极沟槽中。栅极电极设置在栅极沟槽中，但与至少一个导电屏蔽电极绝缘。屏蔽介电层绝缘至少一个导电屏蔽电极与半导体区域。栅极电介质层使栅电极与体区绝缘。屏蔽电介质层形成为使其伸出并直接延伸到身体区域下方。

8. 发明申请

WO02058159A9 MOS-GATED POWER DEVICE WITH DOPED POLYSILICON BODY AND PROCESS FOR FORMING SAME 审中-公开
标题翻译：具有掺杂多晶硅体的MOS栅极电源装置及其形成方法
公开(公告)号：WO02058159A9
公开(公告)日：2003-04-17
申请号：PCT/US0144374
申请日：2001-11-28
申请人： FAIRCHILD SEMICONDUCTOR
发明人： KOCON CHRISTOPHER B , RIDLEY RODNEY S , GREBS THOMAS E
IPC分类号： H01L21/336 , H01L29/04 , H01L29/10 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7816 , H01L29/04 , H01L29/1095 , H01L29/7395 , H01L29/7801 , H01L29/7813 , Y10S438/914
摘要： An improved MOS-gated power device comprises a substrate having an upper layer of doped monocrystalline silicon of a first conduction type that includes a doped well region of a second conduction type. The substrate further comprises at least one heavily doped source region of the first conduction type disposed in the well region at an upper surface of the upper layer, a gate region comprising a conductive material electrically insulated from the source region by a dielectric material, a patterned interlevel dielectric layer on the upper surface overlying the gate and source regions, and a heavily doped drain region of the first conduction type. The improvement comprises: body regions comprising heavily doped polysilicon of the second conduction type disposed in the well region at the upper surface of the monocrystalline silicon substrate. A process for forming an improved MOS-gated power device comprises: providing a substrate having an upper layer of doped monocrystalline silicon of a first conduction type that includes a doped well region of a second conduction type. The substrate further comprises a heavily doped source regions of the first conduction type disposed in the well region at an upper surface of the upper layer, a gate region comprising a conductive material electrically insulated from the source region by a dielectric material, heavily doped drain region of the first conduction type, a patterned interlevel dielectric layer on the upper surface overlying the gate and source regions. The process further comprises: forming a body mask on the substrate, and selectively removing portions of the source region and underlying well region remotely disposed from the gate region, thereby forming at least one body hollow in the substrate; removing the body mask, and forming a blanket layer of heavily doped polysilicon of the the second conduction type that overlies the substrate and interlevel dielectric layer aned fills the body hollow; selectively removing portions of the polysilicon blanket layer from the source region and interlevel dielectric layer, leaving heavily doped polysilicon filling the body hollow and thereby forming a body region; depositing over the upper surface and interlevel dielectric layer a source metal in electrical contact with the source and body regions; and forming a drain metal layer in contact with the drain region in the substrate.
摘要翻译：改进的MOS门控功率器件包括具有第一导电类型的掺杂单晶硅的上层的衬底，其包括第二导电类型的掺杂阱区。衬底还包括设置在上层的上表面的阱区中的第一导电类型的至少一个重掺杂源极区，包括通过电介质材料与源极区域电绝缘的导电材料的栅极区域，图案化覆盖栅极和源极区域的上表面上的层间电介质层，以及第一导电类型的重掺杂漏极区域。该改进包括：设置在单晶硅衬底的上表面的阱区中的包括第二导电类型的重掺杂多晶硅的主体区域。用于形成改进的MOS门控功率器件的工艺包括：提供具有第一导电类型的掺杂单晶硅上层的衬底，该第一导电类型的上层包括第二导电类型的掺杂阱区。衬底还包括设置在上层的上表面处的阱区中的第一导电类型的重掺杂源极区，包括通过电介质材料与源极区域电绝缘的导电材料的栅区，重掺杂漏极区的第一导电类型，在覆盖栅极和源极区域的上表面上的图案化层间电介质层。所述方法还包括：在所述基底上形成人体掩模，并且选择性地去除所述源极区域和从所述栅极区域远离设置的下部阱区域的部分，从而在所述基底中形成至少一个主体中空部分; 去除身体掩模，以及形成覆盖在衬底上的第二导电类型的重掺杂多晶硅的覆盖层，并且层叠介电层填充主体空心; 选择性地从源极区和层间电介质层去除多晶硅覆盖层的部分，留下重掺杂的多晶硅，将体中空填充，从而形成体区; 在上表面和层间介质层上沉积与源极和体区电接触的源极金属; 以及形成与衬底中的漏极区域接触的漏极金属层。

9. 发明申请

WO2007117312A3 POWER DEVICE UTILIZING CHEMICAL MECHANICAL PLANARIZATION 审中-公开
标题翻译：电力设备利用化学机械平面化
公开(公告)号：WO2007117312A3
公开(公告)日：2011-05-26
申请号：PCT/US2006061423
申请日：2006-11-30
申请人： FAIRCHILD SEMICONDUCTOR , MARCHANT BRUCE DOUGLAS , GREBS THOMAS E , RIDLEY RODNEY S , KRAFT NATHAN LAWRENCE
发明人： MARCHANT BRUCE DOUGLAS , GREBS THOMAS E , RIDLEY RODNEY S , KRAFT NATHAN LAWRENCE
IPC分类号： H01L21/00
CPC分类号： H01L29/7811 , H01L21/3083 , H01L29/0696 , H01L29/407 , H01L29/42368 , H01L29/4238 , H01L29/7813 , Y10S438/942 , Y10S438/95
摘要： A trench-gated field effect transistor (FET) is formed as follows. Using one mask, a plurality of active gate trenches and at least one gate runner trench are defined and simultaneously formed in a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench.
摘要翻译：沟槽门控场效应晶体管（FET）如下形成。使用一个掩模，多个有源栅极沟槽和至少一个栅极流道沟槽被限定并同时形成在硅区域中，使得（i）至少一个栅极流道沟槽的宽度大于多个栅极沟槽的宽度的有源栅极沟槽，以及（ii）多个有源栅极沟槽与至少一个栅极流道沟槽邻接。

10. 发明申请

WO2007002857A3 STRUCTURES AND METHODS FOR FORMING SHIELDED GATE FIELD EFFECT TRANSISTORS 审中-公开
标题翻译：形成屏蔽栅场效应晶体管的结构和方法
公开(公告)号：WO2007002857A3
公开(公告)日：2009-04-23
申请号：PCT/US2006025432
申请日：2006-06-29
申请人： FAIRCHILD SEMICONDUCTOR , GREBS THOMAS E , RIDLEY RODNEY S , KRAFT NATHAN LAWRENCE , DOLNY GARY M , YEDINAK JOSEPH A , KOCON CHRISTOPHER BOGUSLAW , CHALLA ASHOK B
发明人： GREBS THOMAS E , RIDLEY RODNEY S , KRAFT NATHAN LAWRENCE , DOLNY GARY M , YEDINAK JOSEPH A , KOCON CHRISTOPHER BOGUSLAW , CHALLA ASHOK B
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/338 , H01L21/8242 , H01L29/76
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0865 , H01L29/0869 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A field effect transistor is formed as follows. A trench is formed in a semiconductor region. A dielectric layer lining the trench sidewalls and bottom is formed. The trench is filled with a conductive material. The conductive material is recessed into the trench to thereby form a shield electrode in a bottom portion of the trench. The recessing of the conductive material includes isotropic etching of the conductive material. An inter-electrode dielectric (IED) is formed over the recessed shield electrode.
摘要翻译：场效应晶体管如下形成。沟槽形成在半导体区域中。形成沟槽侧壁和底部的电介质层。沟槽填充有导电材料。导电材料凹入沟槽中，从而在沟槽的底部形成屏蔽电极。导电材料的凹陷包括导电材料的各向同性蚀刻。在凹陷的屏蔽电极上形成电极间电介质（IED）。

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