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1. 发明申请

WO2003107172A3 FIFO-REGISTER 审中-公开
公开(公告)号：WO2003107172A3
公开(公告)日：2003-12-24
申请号：PCT/IB2003/002350
申请日：2003-05-27
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SALTERS, Roelof, H., W. , WIELAGE, Paul
发明人： SALTERS, Roelof, H., W. , WIELAGE, Paul
IPC分类号： G06F5/06
摘要： A FIFO-register (10) according to the invention comprises a sequence of register cells (10.1,...,10.m), which register cells have a data section (40) and a status section (30). Data (Din) provided at an input (20) is shifted via the data sections (40) in the register cells to an output (50). The status section (30) of each cell indicates whether the data section (40) of that cell contains valid data. The status section of a cell comprises a control unit (37) coupled to a status input (32), to a status output (33) and to a clock input (31), and generates an output clock signal (Cl i ), which controls charge controlling elements (35, 36) coupled to the status input and the status output and controls the data section (40). The status output (33) of a status section (30) and the status input (32') of its successor (30') share a common capacitive node (33).

2. 发明申请

WO03001529A3 METHOD AND CIRCUIT ARRANGEMENT FOR MEMORY REDUNDANCY SYSTEM 审中-公开
标题翻译：存储器冗余系统的方法和电路布置
公开(公告)号：WO03001529A3
公开(公告)日：2003-04-10
申请号：PCT/IB0202334
申请日：2002-06-18
申请人： KONINKL PHILIPS ELECTRONICS NV , SALTERS ROELOF H W , CUPPENS ROGER , DITEWEG ANTHONIE M H
发明人： SALTERS ROELOF H W , CUPPENS ROGER , DITEWEG ANTHONIE M H
IPC分类号： G11C29/00
CPC分类号： G11C29/802 , G11C29/812
摘要： The present invention relates to a method and circuit arrangement for performing an error recovery in a memory arrangement comprising at least two separate memories. The memory arrangement comprises a central storage for storing a faulty-address information of the at least two separate memories. Each memory has its own local address comparison unit and local volatile memory for addresses. The faulty-address information is transported from the central storage to the local volatile memories for address comparison of a redundancy system. Thereby, overhead and complexity can be reduced and flexibility of the architecture enhanced.
摘要翻译：本发明涉及一种用于在包括至少两个分开的存储器的存储器装置中执行错误恢复的方法和电路装置。存储器装置包括用于存储至少两个单独存储器的故障地址信息的中央存储器。每个存储器都有自己的本地地址比较单元和用于地址的本地易失性存储器。故障地址信息从中央存储器传送到本地易失性存储器，用于冗余系统的地址比较。因此，可以降低开销和复杂性并增强架构的灵活性。

3. 发明申请

WO2008015603A1 DEVICE AND METHOD FOR GENERATING A RANDOM BIT STRING 审中-公开
标题翻译：用于产生随机位字符串的装置和方法
公开(公告)号：WO2008015603A1
公开(公告)日：2008-02-07
申请号：PCT/IB2007/052821
申请日：2007-07-16
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SKORIC, Boris , TUYLS, Pim, T. , SALTERS, Roelof, H., W. , TUINHOUT, Hans, P. , AKKERMANS, Antonius, H., M.
发明人： SKORIC, Boris , TUYLS, Pim, T. , SALTERS, Roelof, H., W. , TUINHOUT, Hans, P. , AKKERMANS, Antonius, H., M.
IPC分类号： G06F7/58
CPC分类号： G06F7/588 , H04L9/0866
摘要： The invention relates to generating a bit string based on the circumstances of a breakdown of a diode or a number of diodes (11, 21, 31, 41, 51). One or more diodes (11, 21, 31, 41, 51) are fed with a voltage exceeding a breakdown voltage of the diodes (11, 21, 31, 41, 51) connected to a diode breakdown processor (13, 23, 33, 43, 53), which detects the breakdown and optionally relevant circumstances such as an exact breakdown voltage, and generates a bit string based on the detection, which may be used as a unique identifier or as a secret key.
摘要翻译：本发明涉及基于二极管或多个二极管（11,21,31,41,51）的击穿情况来产生位串。一个或多个二极管（11,21,31,41,51）被馈送超过连接到二极管击穿处理器（13,23,33）的二极管（11,21,31,41,51）的击穿电压的电压，43,53），其检测故障和可选的相关情况，例如精确击穿电压，并且基于检测生成可以用作唯一标识符或秘密密钥的位串。

4. 发明申请

WO2007119190A3 SEMICONDUCTOR DEVICE IDENTIFIER GENERATION METHOD AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件识别器生成方法和半导体器件
公开(公告)号：WO2007119190A3
公开(公告)日：2008-01-17
申请号：PCT/IB2007051213
申请日：2007-04-04
申请人： KONINKL PHILIPS ELECTRONICS NV , SALTERS ROELOF H W , VAN VEEN RUTGER S , HEILIGERS MANUEL P C , KRUSEMAN ABRAHAM C , TUYLS PIM T , SCHRIJEN GEERT J , SKORIC BORIS
发明人： SALTERS ROELOF H W , VAN VEEN RUTGER S , HEILIGERS MANUEL P C , KRUSEMAN ABRAHAM C , TUYLS PIM T , SCHRIJEN GEERT J , SKORIC BORIS
IPC分类号： G11C7/24 , G11C16/20 , G11C16/22
CPC分类号： G11C7/24 , G06F21/30 , G06F21/73 , G11C7/20 , G11C16/20 , G11C16/22 , G11C2029/0407 , G11C2029/4402 , G11C2029/5002 , H04L9/0866
摘要： A method (100) is disclosed of generating an identifier from a semiconductor device (600) comprising a volatile memory (610) having a plurality of memory cells. The method comprises causing (110) the memory cells to assume a plurality of pseudo-random bit values inherent to variations in the microstructure of the memory cells; retrieving (120) the bit values from at least a subset of the plurality of memory cells; and generating the identifier from the retrieved bit values. The method (100) is based on the realization that a substantial amount of the cells of a volatile memory can assume a bit value that is governed by underlying variations in manufacturing process parameters; this for instance occurs at power-up for an SRAM or after a time period without refresh for a DRAM. This can be used for several identification purposes, such as identifying a semiconductor device (600) comprising the volatile memory (610), or for secure key generation by mapping error- correcting code words onto the identifier bit locations. The present invention further includes a semiconductor device (600, 1000) configured to be subjectable to the method (100) of the present invention.
摘要翻译：公开了一种从包括具有多个存储器单元的易失性存储器（610）的半导体器件（600）生成标识符的方法（100）。该方法包括使（110）存储器单元呈现存储器单元的微结构变化所固有的多个伪随机位值; 从所述多个存储器单元的至少一个子集中检索（120）所述位值; 以及从所检索的位值生成所述标识符。方法（100）基于以下认识：易失性存储器的大量单元可以采用受制造工艺参数的潜在变化控制的位值; 这例如在SRAM的上电时或者在不刷新DRAM的时间段之后发生。这可以用于多个识别目的，诸如识别包括易失性存储器（610）的半导体器件（600），或者通过将纠错码字映射到标识符位置上来进行安全密钥生成。本发明还包括被配置为可受本发明的方法（100）的半导体器件（600,1000）。

5. 发明申请

WO2004021353A1 DEVICE WRITING TO A PLURALITY OF ROWS IN A MEMORY MATRIX SIMULTANEOUSLY 审中-公开
标题翻译：在存储器矩阵中同时写入多个行的多个设备的设备
公开(公告)号：WO2004021353A1
公开(公告)日：2004-03-11
申请号：PCT/IB2003/003729
申请日：2003-07-31
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SALTERS, Roelof, H., W.
发明人： SALTERS, Roelof, H., W.
IPC分类号： G11C7/12
CPC分类号： G11C7/1078 , G11C7/12 , G11C8/12 , G11C11/419 , G11C15/00 , G11C15/04
摘要： A word line driver circuit (10) is coupled to word lines (18) of a memory matrix, for example a matrix of content addressable cells (12). The word line driver circuit is capable of selecting a plurality of word lines simultaneously to permit writing into memory cells in a plurality of rows via the same bit line simultaneously. Cell strength control circuitry (17) reduces a drive strength required to write data into the cells, relative to a drive strength of the bit line driver circuits (15), at least during writing data into memory cells in a plurality of rows of memory cells. Preferably, the drive strength control circuitry (17) contain a resistive element in the power supply lines of the memory cells in a column, so that the supply voltage of the cells in the column is increasingly reduced when more current is drawn during writing of more cells simultaneously.
摘要翻译：字线驱动器电路（10）耦合到存储器矩阵的字线（18），例如内容寻址单元（12）的矩阵。字线驱动电路能够同时选择多个字线，以允许通过同一位线同时写入多行的存储单元。至少在将数据写入多行存储器单元中的存储单元时，单元强度控制电路（17）相对于位线驱动电路（15）的驱动强度，将数据写入单元中所需的驱动强度降低。优选地，驱动强度控制电路（17）在列中的存储单元的电源线中包含电阻元件，使得当写入更多的电流时更多的电流被拉伸时，列中的单元的电源电压逐渐减小细胞同时进行。

6. 发明申请

WO2007119190A2 SEMICONDUCTOR DEVICE IDENTIFIER GENERATION METHOD AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件识别器生成方法和半导体器件
公开(公告)号：WO2007119190A2
公开(公告)日：2007-10-25
申请号：PCT/IB2007/051213
申请日：2007-04-04
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SALTERS, Roelof, H., W. , VAN VEEN, Rutger, S. , HEILIGERS, Manuel, P., C. , KRUSEMAN, Abraham, C. , TUYLS, Pim, T. , SCHRIJEN, Geert, J. , SKORIC, Boris
发明人： SALTERS, Roelof, H., W. , VAN VEEN, Rutger, S. , HEILIGERS, Manuel, P., C. , KRUSEMAN, Abraham, C. , TUYLS, Pim, T. , SCHRIJEN, Geert, J. , SKORIC, Boris
IPC分类号： G11C7/24 , G11C16/20 , G11C16/22
CPC分类号： G11C7/24 , G06F21/30 , G06F21/73 , G11C7/20 , G11C16/20 , G11C16/22 , G11C2029/0407 , G11C2029/4402 , G11C2029/5002 , H04L9/0866
摘要： A method (100) is disclosed of generating an identifier from a semiconductor device (600) comprising a volatile memory (610) having a plurality of memory cells. The method comprises causing (110) the memory cells to assume a plurality of pseudo-random bit values inherent to variations in the microstructure of the memory cells; retrieving (120) the bit values from at least a subset of the plurality of memory cells; and generating the identifier from the retrieved bit values. The method (100) is based on the realization that a substantial amount of the cells of a volatile memory can assume a bit value that is governed by underlying variations in manufacturing process parameters; this for instance occurs at power-up for an SRAM or after a time period without refresh for a DRAM. This can be used for several identification purposes, such as identifying a semiconductor device (600) comprising the volatile memory (610), or for secure key generation by mapping error- correcting code words onto the identifier bit locations. The present invention further includes a semiconductor device (600, 1000) configured to be subjectable to the method (100) of the present invention.
摘要翻译：公开了一种从包括具有多个存储单元的易失性存储器（610）的半导体器件（600）生成标识符的方法（100）。该方法包括使（110）存储器单元呈现存储器单元的微结构变化所固有的多个伪随机位值; 从所述多个存储器单元的至少一个子集中检索（120）所述位值; 以及从所检索的位值生成所述标识符。方法（100）基于以下认识：易失性存储器的大量单元可以采用受制造工艺参数的潜在变化控制的位值; 这例如在SRAM的上电时或者在不刷新DRAM的时间段之后发生。这可以用于多个识别目的，例如识别包括易失性存储器（610）的半导体器件（600），或者通过将纠错码字映射到标识符位置上来进行安全密钥生成。本发明还包括被配置为可受本发明的方法（100）的半导体器件（600,1000）。

7. 发明申请

WO2003107172A2 FIFO-REGISTER AND DIGITAL SIGNAL PROCESSOR COMPRISING A FIFO-REGISTER 审中-公开
标题翻译：包含FIFO寄存器的FIFO寄存器和数字信号处理器
公开(公告)号：WO2003107172A2
公开(公告)日：2003-12-24
申请号：PCT/IB2003/002350
申请日：2003-05-27
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SALTERS, Roelof, H., W. , WIELAGE, Paul
发明人： SALTERS, Roelof, H., W. , WIELAGE, Paul
IPC分类号： G06F5/06
CPC分类号： G06F5/08
摘要： A FIFO-register (10) according to the invention comprises a sequence of register cells (10.1,...,10.m), which register cells have a data section (40) and a status section (30). Data (Din) provided at an input (20) is shifted via the data sections (40) in the register cells to an output (50). The status section (30) of each cell indicates whether the data section (40) of that cell contains valid data. The status section of a cell comprises a control unit (37) coupled to a status input (32), to a status output (33) and to a clock input (31), and generates an output clock signal (Cli), which controls charge controlling elements (35, 36) coupled to the status input and the status output and controls the data section (40). The status output (33) of a status section (30) and the status input (32') of its successor (30') share a common capacitive node (33).
摘要翻译：根据本发明的FIFO寄存器（10）包括寄存器单元（10.1，...，10.m）的序列，该寄存器单元具有数据段（40）和状态段（30）。提供在输入（20）处的数据（Din）经由寄存器单元中的数据部分（40）移位到输出（50）。每个单元的状态部分（30）指示该单元的数据段（40）是否包含有效数据。单元的状态部分包括耦合到状态输入（32）到状态输出（33）和时钟输入（31）的控制单元（37），并且产生输出时钟信号（Cli），其控制耦合到状态输入和状态输出的电荷控制元件（35,36）并且控制数据部分（40）。状态部分（30）的状态输出（33）和其后继（30'）的状态输入（32'）共享公共电容节点（33）。

8. 发明申请

WO2003001529A2 METHOD AND CIRCUIT ARRANGEMENT FOR MEMORY ERROR RECOVERY 审中-公开
标题翻译：用于存储器错误恢复的方法和电路布置
公开(公告)号：WO2003001529A2
公开(公告)日：2003-01-03
申请号：PCT/IB2002/002334
申请日：2002-06-18
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SALTERS, Roelof, H., W. , CUPPENS, Roger , DITEWEG, Anthonie, M., H.
发明人： SALTERS, Roelof, H., W. , CUPPENS, Roger , DITEWEG, Anthonie, M., H.
IPC分类号： G11C
CPC分类号： G11C29/802 , G11C29/812
摘要： The present invention relates to a method and circuit arrangement for performing an error recovery in a memory arrangement comprising at least two separate memories. The memory arrangement comprises a central storage for storing a faulty-address information of the at least two separate memories. Each memory has its own local address comparison unit and local volatile memory for addresses. The faulty-address information is transported from the central storage to the local volatile memories for address comparison of a redundancy system. Thereby, overhead and complexity can be reduced and flexibility of the architecture enhanced.
摘要翻译：本发明涉及一种用于在包括至少两个分开的存储器的存储器装置中执行错误恢复的方法和电路装置。存储器装置包括用于存储至少两个单独存储器的故障地址信息的中央存储器。每个存储器都有自己的本地地址比较单元和用于地址的本地易失性存储器。故障地址信息从中央存储器传送到本地易失性存储器，用于冗余系统的地址比较。因此，可以降低开销和复杂性并增强架构的灵活性。

9. 发明申请

WO2003001381A1 METHOD AND CIRCUIT ARRANGEMENT FOR MEMORY ERROR PROCESSING 审中-公开
标题翻译：用于存储器错误处理的方法和电路布置
公开(公告)号：WO2003001381A1
公开(公告)日：2003-01-03
申请号：PCT/IB2002/002333
申请日：2002-06-18
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , DITEWIG, Anthonie, M., H. , CUPPENS, Roger , SALTERS, Roelof, H., W.
发明人： DITEWIG, Anthonie, M., H. , CUPPENS, Roger , SALTERS, Roelof, H., W.
IPC分类号： G06F11/10
CPC分类号： G11C29/785 , G06F11/1016
摘要： The present invention relates to a method and circuit arrangement for performing an error correction in a memory arrangement in which a redundancy system is used. The addresses of faulty cells are recorded redundantly by applying a corresponding coding. Then, an error correction is applied to the faulty-address information before it is compared to an externally applied address. Thereby, errors due to faulty redundancy addresses can be prevented.
摘要翻译：本发明涉及一种用于在其中使用冗余系统的存储装置中执行纠错的方法和电路装置。通过应用相应的编码来冗余地记录故障单元的地址。然后，在将故障地址信息与外部施加的地址进行比较之前，将错误校正应用于故障地址信息。因此，可以防止由于冗余地址故障引起的错误。

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